82C50A

® 82C50A Data Sheet August 24, 2006 FN2958.5 CMOS Asynchronous The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil’s advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE’s receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1,1.5, or 2 stop bits. The Baud Rate Generator divides the clock by a divisor programmable from 1 to 216-1 to provide standard RS232C baud rates when using any one of three industry standard baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use. To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals RTS, CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design. Features • Single Chip UART/BRG • DC to 625K Baud (DC to 10MHz Clock) • Crystal or External Clock Input • On Chip Baud Rate Generator 1 to 65535 Divisor Generates 16X Clock • Prioritized Interrupt Mode • Fully TTL/CMOS Compatible • Microprocessor Bus Oriented Interface • 80C86/80C88 Compatible • Scaled SAJI IV CMOS Process • Low Power - 1mA/MHz Typical • Modem Interface • Line Break Generation and Detection • Loopback and Echo Modes • Doubled Buffered Transmitter and Receiver • Single 5V Supply • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information 625K BAUD CP82C50A-5 CP82C50A-5Z (Note) CS82C50A-596 PART MARKING CP82C50A-5 CP82C50A-5Z CS82C50A-5 TEMP RANGE (°C) 0 to +70 0 to +70 0 to +70 PACKAGE 40 Ld PDIP 40 Ld PDIP (Pb-free) PKG. DWG. # E40.6 E40.6 44 Ld PLCC N44.65 Tape and Reel 44 Ld PLCC N44.65 (Pb-free) 44 Ld PLCC N44.65 Tape and Reel (Pb-free) CS82C50A-5Z (Note) CS82C50A-5Z 0 to +70 0 to +70 CS82C50A-5Z96 CS82C50A-5Z (Note) IS82C50A-5 IS82C50A-5Z (Note) IS82C50A-5 IS82C50A-5Z -40 to +85 44 Ld PLCC N44.65 -40 to +85 44 Ld PLCC N44.65 (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 82C50A Functional Diagram CSO CS1 CS2 ADS A0 A1 A2 MR DISTR DISTR 12 13 14 25 28 27 26 35 22 21 MICROPROCESSOR INTERFACE 24 CSOUT 23 DDIS INTERRUPT 30 INTRPT ENABLE, ID, & CONTROL UART RECEIVER DIVISOR LATCH LINE STATUS AND CONTROL AND BAUD RATE GENERATOR TRANSMITTER MODEM MODEM CONTROL 10 9 16 17 11 32 33 34 31 36 37 38 39 SIN RCLK XTAL1 XTAL2 SOUT RTS DTR OUT1 OUT2 CTS DSR DCD RI 15 BAUDOUT DOSTR 19 DOSTR 18 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 MODEM STATUS 2 FN2958.5 August 24, 2006 82C50A Pinout 82C50A (PDIP) TOP VIEW D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2 BAUDOUT XTAL1 XTAL2 DOSTR DOSTR GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VCC 39 RI 38 DCD 37 DSR 36 CTS 35 MR 34 OUT1 33 DTR 32 RTS 31 OUT2 30 INTRPT 29 NC 28 A0 27 A1 26 A2 25 ADS 24 CSOUT 23 DDIS 22 DISTR 21 DISTR 82C50A (PLCC) TOP VIEW DCD DSR CTS VCC NC D4 D3 D2 D1 D0 RI 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D5 D6 D7 RCLK SIN NC 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MR OUT1 DTR RTS OUT2 NC SOUT CS0 CS1 CS2 BAUDOUT INTRP NC A0 A1 A2 DOSTR DOSTR CSOUT XTAL1 XTAL2 DISTR DISTR DDIS GND 3 ADS NC FN2958.5 August 24, 2006 82C50A Pin Description SYMBOL DISTR, DISTR PIN NUMBER 22 21 TYPE I I ACTIVE LEVEL H L DESCRIPTION DATA IN STROBE, DATA IN STROBE: DISTR, DISTR are read inputs which cause the 82C50A to output data to the data bus (D0-D7). The data output depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DISTR, DISTR inputs. Only an active DISTR or DISTR, not both, is used to receive data from the 82C50A during a read operation. If DISTR is used as the read input, DlSTR should be tied high. If DISTR is used as the active read input, DISTR should be tied low. DATA OUT STROBE, DATA OUT STROBE: DOSTR, DOSTR are write inputs which cause data from the data bus (D0-D7) to be input to the 82C50A. The data input depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DOSTR, DOSTR inputs. Only an active DOSTR or DOSTR, not both, is used to transmit data to the 82C50A during a write operation. If DOSTR is used as the write input, DOSTR should be tied high. If DOSTR is used as the write input, DOSTR should be tied low. DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data, control and status information between the 82C50A and the CPU. For character formats of less than 8 bits, D7, D6 and D5 are “don’t cares” for data write operations and 0 for data read operations. These lines are normally in a high impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the first serial data bit to be received or transmitted. REGISTER SELECT: The address lines select the internal registers during CPU bus operations. See Table 1. CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. XTAL1 can also be used as an external clock input, in which case XTAL2 should be left open. SERIAL DATA OUTPUT: Serial data output from the 82C50A transmitter circuitry. A Mark (1) is a logic one (high) and Space (0) is a logic zero (low). SOUT is held in the Mark condition when the transmitter is disabled, MR is true, the Transmitter Register is empty, or when in the Loop Mode. SOUT is not affected by the CTS input. GROUND: Power supply ground connection (VSS). CLEAR TO SEND: The logical state of the CTS pin is reflected in the CTS bit of the (MSR) Modem Status Register (CTS is bit 4 of the MSR, written MSR (4)). A change of state in the CTS pin since the previous reading of the MSR causes the setting of DCTS (MSR(O)) of the Modem Status Register. When CTS pin is ACTIVE (low), the modem is indicating that data on SOUT can be transmitted on the communications link. If CTS pin goes INACTIVE (high), the 82C50A should not be allowed to transmit data out of SOUT. CTS pin does not affect Loop Mode operation. DATA SET READY: The logical state of the DSR pin is reflected in MSR(5) of the Modem Status Register. DDSR (MSR(1)) indicates whether the DSR pin has changed state since the previous reading of the MSR. When the DSR pin is ACTIVE (low), the modem is indicating that it is ready to exchange data with the 82C50A, while the DSR Pin INACTIVE (high) indicates that the modem is not ready for data exchange. The ACTIVE condition indicates only the condition of the local Data Communications Equipment (DCE), and does not imply that a data circuit as been established with remote equipment. DATA TERMINAL READY: The DTR pin can be set (low) by writing a logic 1 to MCR(0), Modem Control Register bit 0. This signal is cleared (high) by writing a logic 0 to the DTR bit (MCR(0)) or whenever a MR ACTIVE (high) is applied to the 82C50A. When ACTIVE (low), DTR pin indicates to the DCE that the 82C50A is ready to receive data. In some instances, DTR pin is used as a power on indicator. The INACTIVE (high) state causes the DCE to disconnect the modem from the telecommunications circuit. REQUEST TO SEND: The RTS signal is an output used to enable the modem. The RTS pin is set low by writing a logic 1 to MCR (1) bit 1 of the Modem Control Register. The RTS pin is reset high by Master Reset. When ACTIVE, the RTS pin indicates to the DCE that the 82C50A has data ready to transmit. In half duplex operations, RTS is used to control the direction of the line. BAUDOUT: This output is a 16X clock out used for the transmitter section (16X = 16 times the data rate). The BAUDOUT clock rate is equal to the reference oscillator frequency divided by the specified divisor in the Baud Rate Generator Divisor Latches DLL and DLM. BAUDOUT may be used by the Receiver section by tying this output to RCLK. DOSTR, DOSTR 19 18 I I H L D0-D7 1-8 I/O A0, A1, A2 XTAL1, XTAL2 SOUT 28, 27, 26 16 17 11 I I I O O H GND CTS 20 36 I L L DSR 37 I L DTR 33 O L RTS 32 O L BAUDOUT 15 O 4 FN2958.5 August 24, 2006 82C50A Pin Description SYMBOL OUT1 PIN NUMBER 34 (Continued) TYPE O ACTIVE LEVEL L DESCRIPTION OUTPUT 1: This is a general purpose output that can be programmed ACTIVE (low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The OUT1 pin is set high by Master Reset. The OUT1 pin is INACTIVE (high) during loop mode operation. OUTPUT 2: This is a general purpose output that can be programmed ACTIVE (low) by setting MCR(3) (OUT1) of the Modem Control Register to a high level. The OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during loop mode operation. RING INDICATOR: When low, RI indicates that a telephone ringing signal has been received by the modem or data set. The RI signal is a modem control input whose condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI (MSR(2)) indicates whether the RI input has changed from a Low to High since the previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) and RI changes from a Low to High, an interrupt is generated. The ACTIVE (low) state of RI indicates that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE state of RI will occur during the INACTIVE segments not detected by the DCE. This circuit is not disabled by the INACTIVE condition of DTR. DATA CARRIER DETECT: When ACTIVE (low), DCD indicates that the data carrier has been detected by the modem or data set. DCD is a modem input whose condition can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Register. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD input has changed since the previous reading of the MSR. DOD has no effect on the receiver. If the DCD changes state with the modem status interrupt enabled, an interrupt is generated. When DCD is ACTIVE (low), the received line signal from the remote terminal is within the limits specified by the DCE manufacturer. The INACTIVE (high) signal indicates that the signal is not within the specified limits, or is not present. MASTER RESET: The MR input forces the 82C50A into an idle mode in which all serial data activities are suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The Line Status Register (LSR) is cleared except for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state until programmed to resume serial data activities. The MR input is a Schmitt trigger input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage levels. See Table 7 for a summary of Master Reset’s effect on 82C50A operation. INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt Enable Register: Receiver Error flag, Received Data Available, Transmitter Holding Register Empty, and Modem Status. The lNTRPT is reset low upon appropriate service or a MR operation. See Figure 1. Interrupt Control Structure. SERIAL DATA INPUT: The SIN input is the serial data input from the communication line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0) is low. Data inputs on SIN are disabled when operating in the loop mode. VCC: +5V positive power supply pin. A 0.1μA decoupling capacitor from VCC (pin 40) to GND (pin 20) is recommended. CHIP SELECT: The Chip Select inputs act as enable signals for the write (DOSTR, DOSTR) and read (DlSTR, DlSTR) input signals. The Chip Select inputs are latched by the ADS input. Do Not Connect CHIP SELECT OUT: When ACTIVE (high), this pin indicates that the chip has been selected by active CS0, CS1, and CS2 inputs. No data transfer can be initiated until CSOUT is a logic 1, ACTIVE (high). DRIVER DISABLE: This output is INACTIVE (low) when the CPU is reading data from the 82C50A. An ACTIVE (high) Dells output can be used to disable an external transceiver when the CPU is reading data. ADDRESS STROBE: When ACTIVE (low), ADS latches the Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) inputs. An active ADS is required when the Register Select pins are not stable for the duration of the read or write operation, multiplexed mode. If not required, the ADS input should be tied low, non-multiplexed mode. This input is the 16X Baud Rate Clock for the receiver section of the 82C50A. This input may be provided from the BAUDOUT output or an external clock. OUT2 31 O L RI 39 1 L DCD 38 I L MR 35 1 H lNTRPT 30 O H SIN 10 I H VCC CS0, CS1, CS2 NC CSOUT 40 12,13, 14 29 24 I I H H, H, L O H DDIS 23 O H ADS 25 I L RCLK 9 I 5 FN2958.5 August 24, 2006 82C50A Block Diagram RECEIVER BUFFER REGISTER (10) RECEIVER SHIFT RECEIVER (9) RCLK SIN (1 - 8) D7 - D0 DATA BUS BUFFER (40) +5V GND (20) POWER LINE CONTROL REGISTER SUPPLY RECEIVER TIMING & CONTROL (28) A0 (27) A1 (26) A2 GENERATOR DIVISOR LATCH (MS) (12) CS0 (13) CS1 (14) CS2 (25) ADS (35) MR (22) DISTR (21) DISTR (19) DOSTR (18) DOSTR (23) DDIS (24) CSOUT (16) XTAL1 (17) XTAL2 MODEM STATUS REGISTER MODEM CONTROL REGISTER MODEM CONTROL LOGIC (37) DSR (38) DCD (39) RI (34) OUT1 (31) OUT2 (36) CTS (33) DTR (32) RTS TRANSMITTER SHIFT REGISTER HOLDING REGISTER TRANSMITTER (11) SOUT CONTROL LOGIC SELECT & LINE STATUS REGISTER TRANSMITTER TIMING & CONTROL LATCH (LS) BAUD RATE (15) BAUDOUT DIVISOR SCRATCH REGISTER INTERRUPT ENABLE REGISTER INTERRUPT CONTROL INTERRUPT IO REGISTER LOGIC (30) INTRPT 6 FN2958.5 August 24, 2006 82C50A Accessible Registers The three types of internal registers in the 82C50A used in the operation of the device are control, status, and data registers. The control registers are the Bit Rate Select Register DLL and DLM, Line Control Register, Interrupt Enable Register and the Modem Control registers, while the status registers are the Line Status Registers and the Modem Status Register. The data registers are the Receiver Buffer Register and Transmitter Holding Register. The Address, Read, and Write inputs are used in conjunction with the Divisor Latch Access Bit in the Line Control Register (LCR(7)) to select the register to be written or read (see Table 1.). Individual bits within these registers are referred to by the register mnemonic and the bit number in parenthesis. An example, LCR(7) refers to Line Control Register Bit 7. The Transmitter Buffer Register and Receiver Buffer Register are data registers holding from 5-8 data bits. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted. The 82C50A data registers are double buffered so that read and write operations can be performed at the same time the UART is performing the parallel to serial and serial to parallel conversion. This provides the microprocessor with increased flexibility in its read and write timing. Line Control Register (LCR) LCR 7 LCR 6 LCR 5 LCR 4 LCR 3 LCR 2 LCR 1 LCR 0 Word Length Select Stop Bit Select Parity Enable Even Parity Select Stick Parity 0 0 1 1 0 = 5 Data Bits 1 = 6 Data Bits 0 = 7 Data Bits 1 = 8 Data Bits TABLE 1. ACCESSING 82C50A INTERNAL REGISTERS DLAB 0 0 0 X A2 0 0 0 0 A1 0 0 0 1 A0 0 0 1 0 MNEMONIC RBR THR lER IIR REGISTER Receiver Buffer Register (read only) Transmitter Holding Register (write only) Interrupt Enable Register Interrupt Identification Register (read only) Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch (LSB) Divisor Latch (MSB) X X X X X 1 1 NOTE: 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 LCR MCR LSR MSR SCR DLL DLM X = “Don’t Care”, 0 = Logic Low, 1 = Logic High 0 = 1 Stop Bit 1 = 1.5 Stop Bits if 5 Data Bit Word Length is Selected 2 Stop Bits if 6, 7, or 8 Data Bit Word Length is Selected 0 = Parity Disabled 1 = Parity Enabled (Generated & Checked) 0 = Odd Parity When Parity is Enabled 1 = Even Parity When Parity is Enabled 0 = Stick Parity Disabled 1 = When Parity is Enabled Forces the Transmission and Checking of a Parity Bit of a Known State. Parity Bit Forced to a Logic 1 if LCR (4) = 0 or to a Logic 0 If LCR (4) = 1. 0 = Break Disabled 1 = Break Enabled. The Serial Output (SOUT) is Forced to the Spacing (Logic 0) State. Break Control Divisor Latch 0 = Must be Low to Access the Receiver Buffer. Transmitter Holding Access Bit Register or the Interrupt Enable Register. 1 = Must be High to Access the Divisor Latches DLL and DLM of the Baud Rate Generator During a Read or Write Operation. 7 FN2958.5 August 24, 2006 82C50A LINE CONTROL REGISTER (LCR) The format of the data character is controlled by the Line Control Register. The contents of the LCR may be read, eliminating the need for separate storage of the line characteristics in system memory. The contents of the LCR are described below. LCR BITS 0 THRU 7 LCR (0) Word Length Select Bit 0 (WLS0) LCR (1) Word Length Select Bit 1 (WLS1) LCR (2) Stop Bit Select (STB) LCR (3) Parity Enable (PEN) LCR (4) Even Parity Select (EPS) LCR (5) Stick Parity LCR (6) Set Break LCR (7) Divisor Latch Access Bit (DLAB) LCR(0) and LCR(1) Word Length Select Bit 0, Word Length Select Bit 1: The number of bits in each transmitted or received serial character is programmed as follows: LCR(1) 0 0 1 1 LCR(0) 0 1 0 1 WORD LENGTH 5 Bits 6 Bits 7 Bits 8 Bits 1. Load an all Os pad character in response to THRE. 2. Set break in response to the next THRE. 3. Wait for the transmitter to be idle, (TEMT = 1), and clear break when normal transmission has to be restored. During the break, the transmitter can be used as a character timer to accurately establish the break duration. LCR(7) Divisor Latch Access Bit (DLAB): LCR(7) must be set high (logic 1) to access the Divisor Latches DLL and DLM of the Baud Rate Generator during a read or write operation. LCR(7) must be input low to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. LINE STATUS REGISTER (LSR) The LSR is a single register that provides status indications. The LSR is usually the first register read by the CPU to determine the cause of an interrupt or to poll the status of the 82C50A. Three error flags OE, FE, and PE provide the status of any error conditions detected in the receiver circuitry. During reception of the stop bits, the error flags are set high by an error condition. The error flags are not reset by the absence of an error condition in the next received character. The flags reflect the last character only if no overrun occurred. The Overrun Error (OE) indicates that a character in the Receiver Buffer Register has been overwritten by a character from the Receiver Shift Register before being read by the CPU. The character is lost. Framing Error (FE) indicates that the last character received contained incorrect (low) stop bits. This is caused by the absence of the required stop bit or by a stop bit too short to be detected. Parity Error (PE) indicates that the last character received contained a parity error based on the programmed and calculated parity of the received character. The Break Interrupt (BI) status bit indicates that the last character received was a break character. A break character is an invalid data character, with the entire character, including parity and stop bits, logic zero. The Transmitter Holding Register Empty (THRE) bit indicates that the THR register is empty and ready to receive another character. The Transmission Shift Register Empty (TEMT) bit indicates that the Transmitter Shift Register is empty, and the 82C50A has completed transmission of the last character. If the interrupt is enabled (lER(1)), an active THRE causes an interrupt (INTRPT). The Data Ready (DR) bit indicates that the RBR has been loaded with a received character (including Break) and that the CPU may access this data. Reading the LSR clears LSR (1) - LSR (4). (OE, PE, FE and BI). LCR(2) Stop Bit Select: LCR(2) specifies the number of stop bits in each transmitted character. If LCR(2) is a logic 0, one stop bit is generated in the transmitted data. If LCR(2) is a logic 1 when a 5-bit word length is selected, 1.5 stop bits are generated. If LCR(2) is a logic 1 when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. The receiver checks for two stop bits if programmed. LCR(3) Parity Enable: When LCR(3) is high, a parity bit between the last data word bit and stop bit is generated and checked. LCR(4) Even Parity Select: When parity is enabled (LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1 selects even parity. LCR(5) Stick Parity: When parity is enabled (LCR(3) = 1), LCR(5) = 1 causes the transmission and reception of a parity bit to be in the opposite state from that indicated by LCR(4). This allows the user to force parity to a known state and for the receiver to check the parity bit in a known state. LCR(6) Break Control: When LCR(6) is set to logic-1, the serial output (SOUT) is forced to the spacing (logic 0) state. The break is disabled by setting LCR(6) to a logic-0. The Break Control bit acts only on SOUT and has no effect on the transmitter logic. Break Control enables the CPU to alert a terminal in a computer communications system. If the following sequence is used, no erroneous or extraneous characters will be transmitted because of the break. 8 FN2958.5 August 24, 2006 82C50A LSR BITS 0 THRU 7 LOGIC 1 LSR LSR LSR LSR LSR LSR LSR LSR (0) Data Ready (DR) (1) Overrun Error (OE) (2) Parity Error (PE) (3) Framing Error (FE) (4) Break Interrupt (BI) (5) Transmitter Holding Register Empty (THRE) (6) Transmitter Empty (TEMT) (7) Not Used Ready Error Error Error Break Empty Empty LOGIC 0 Not Ready No Error No Error No Error No Break Not Empty Not Empty Register into the Transmitter Shift Register. LSR(5) is reset low by the loading of the Transmitter Holding Register by the CPU. LSR(5) is not reset by a CPU read of the LSR. When the THRE interrupt is enabled (IER(1) = 1), THRE causes a priority 3 interrupt in the lIR. If THRE is the interrupt source indicated in IIR, lNTRPT is cleared by a read of the IIR. LSR(6) Transmitter Empty (TEMT): TEMT is set high when the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty. LSR(6) is reset low when a character is loaded into the THR and remains low until the character is transferred out of SOUT. TEMT is not reset low by a CPU read of the LSR. LSR(7): This bit is permanently set to logic 0. The contents of the Line Status Register are indicated in the above table and are described below. LSR(0) Data Ready (DR): Data Ready is set high when an incoming character has been received and transferred into the Receiver Buffer Register. LSR(0) is reset low by a CPU read of the data in the Receiver Buffer Register. LSR(1) Overrun Error (OE): Overrun Error indicates that data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, overwriting the previous character. The OE indicator is reset whenever the CPU reads the contents of the Line Status Register. LSR(2) Parity Error (PE): Parity Error indicates that the received data character does not have the correct even or odd parity, as selected by the Even Parity Select bit (LCR (4)). The PE bit is set high upon detection of a parity error, and is reset low when the CPU reads the contents of the LSR. LSR(3) Framing Error (FE): Framing Error indicates that the received character did not have a valid stop bit. LSR(3) is set high when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). The FE indicator is reset low when the CPU reads the contents of the LSR. LSR(4) Break Interrupt (BI): Break Interrupt is set high when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The B indicator is reset when the CPU reads the contents of the Line Status Register. LSR(1) - LSR(4) are the error conditions that produce a Receiver Line Status interrupt (priority 1 interrupt in the Interrupt Identification Register (IIR)) when any of the conditions are detected. This interrupt is enabled by setting lER (2) = 1 in the Interrupt Enable Register. LSR(5) Transmitter Holding Register Empty (THRE): THRE indicates that the 82C50A is ready to accept a new character for transmission. The THRE bit is set high when a character is transferred from the Transmitter Holding 9 MODEM CONTROL REGISTER (MCR) The MCR controls the interface with the modem or data set as described below. The MCR can be written and read. The RTS, DTR, OUT1 and OUT2 outputs are directly controlled by their control bits in this register. A high input asserts a low (true) at the output pins. MCR BITS 0 THRU 7 MCR BIT LOGIC 1 MCR MCR MCR MCR MCR MCR MCR MCR (0) Data Terminal Ready DTR (DTR) Output Low (1) Request to Send (RTS) (2) OUT1 (3) OUT2 (4) LOOP (5) 0 (6) 0 (7) 0 RTS Output Low OUT1 Output Low OUT2 Output Low LOOP Enabled MCR BIT LOGIC 0 DTR Output High RTS Output High OUT1 Output High OUT2 Output High LOOP Disabled MCR(0): When MCR(0) is set high, the DTR output is forced low. When MCR(0) is reset low, the DTR output is forced high. The DTR output of the 82C50A may be input into an ElA inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. MCR(1): When MCR(1) is set high, the RTS output is forced low. When MCR(1) is reset low, the RTS output is forced high. The RTS output of the 82C50A may be input into an ElA inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. MCR(2): When MCR(2) is set high, the OUT1 output is forced low. When MCR(2) is reset low, the OUT1 output is forced high. OUT1 is an user designated output. FN2958.5 August 24, 2006 82C50A MCR(3): When MCR(3) is set high, the OUT2 output is forced low. When MCR(3) is reset low, the OUT2 output is forced high. OUT2 is an user designated output. MCR(4): MCR(4) provides a local loopback feature for diagnostic testing of the 62C50A. When MCR(4) is set high, Serial Output (SOUT) is set to the marking (logic 1) state, and the receiver data input Serial Input (SIN) is disconnected. The output of the Transmitter Shift Register is looped back into the Receiver Shift Register input. The four modem control inputs (CTS, DSR, DC, and RI) are disconnected. The four modem control outputs (DTR, RTS, OUT1 and OUT2) are internally connected to the four modem control inputs. The modem control output pins are forced to their inactive state (high). In the diagnostic mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive data paths of the 82C50A. In the diagnostic mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the MCR instead of the four modem control inputs. The interrupts are still controlled by the Interrupt Enable Register. MCR(5) - MCR(7): These bits are permanently set to logic 0. MODEM CONTROL REGISTER (MCR) MCR MCR MCR MCR MCR MCR MCR MCR 7 6 5 4 3 2 1 0 Data Terminal Ready Request to Send Out 1 Out 2 Loop 0 = DTR Output High (Inactive) 1 = DTR Output Low (Active) 0 = RTS Output High (Inactive) 1 = RTS Output Low (Active) 0 = OUT 1 Output High (Inactive) 1 = OUT 1 Output Low (Active) 0 = OUT 2 Output High (Inactive) 1 = OUT 2 Output Low (Active) 0 = Loop Disabled 1 = Loop Enabled These Bits are Permanently Set to a Logic 0. MODEM STATUS REGISTER (MSR) The MSR provides the CPU with status of the modem input lines from the modem or peripheral device. The MSR allows the CPU to read the modem signal inputs by accessing the data bus interface of the 82C50A. In addition to the current status information, four bits of the MSR indicate whether the modem inputs have changed since the last reading of the MSR. The delta status bits are set high when a control input from the modem changes state, and reset low when the CPU reads the MSR. The modem input lines are CTS (pin 36), DSR (pin 37), RI (pin 39), and DCD (pin 38). MSR(4) - MSR(7) are status indications of these lines. The status indications follow the status of the input lines. If the modem status interrupt in the Interrupt Enable Register is enabled (IER(3)), a change of state in a modem input signals will be reflected by the modem status bits in the lIR register, and an interrupt (lNTRPT) is generated. The MSR is a priority 4 interrupt. The contents of the Modem Status Register are described below: Note that the state (high or low) of the status bits are inverted versions of the actual input pins. MSR BIT MSR (1) MSR (2) MSR (0) MSR (3) MSR (4) MSR (5) MSR (6) MSR (7) MSR BITS 0 THRU 7 MNEMONIC DDSR TERI DCTS DDCD CTS DSR RI DCD DESCRIPTION Delta Data Set Ready Trailing Edge of Ring Indicator Delta Clear To Send Delta Data Carrier Detect Clear To Send Data Set Ready Ring Indicator Data Carrier Detect MSR(0) Delta Clear to Send (DCTS): DCTS indicates that the CTS input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(1) Delta Data Set Ready (DDSR): DDSR indicates that the DSR input (Pin-37) to the 62C50A has changed state since the last time it was read by the CPU. MSR(2) Trailing Edge of Ring Indicator (TERI): TERI indicates that the RI input (Pin-39) to the 82C50A has Changed state from Low to High since the last time it was read by the CPU. High to Low transitions on RI do not activate TERI. 10 FN2958.5 August 24, 2006 82C50A MSR(3) Delta Data Carrier Detect (DDCD): DDCD indicates that the DCD input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(4) Clear to Send (CTS): Clear to Send (CTS) is the status of the CTS input (Pin-36) from the modem indicating to the 82C50A that the modem is ready to receive data from the 62C50A transmitter output (SOUT). If the 82C50A is in the loop mode (MCR(4)=1), MSR(4) is equivalent to RTS in the MCR. MSR(5) Data Set Ready (DSR): Data Set Ready (DSR) is a status of the DSR input (Pin-37) from the modem to the 82C50A which indicates that the modem is ready to provide received data to the 82C50A receiver circuitry. If the 82C50A is in the loop mode (MCR(4) = 1), MSR(5) is equivalent to DTR in the MCR. MSR(6) Ring Indicator MSR(6): Indicates the status of the RI input (Pin-39). If the 82C50A is in the loop mode (MCR(4) = 1), MSR(6) is equivalent to OUT1 in the MCR. MSR(7) Data Carrier Detect (MSR(7)): Data Carrier Detect indicates the status of the Data Carrier Detect (DCD) input (Pin-38). If the 82C50A is in the loop mode (MCR(4) = 1), MSR(4) is equivalent to OUT2 of the MCR. The modem status inputs (RI, DCD, DSR and CTS) reflect the modem input lines with any change of status. Reading the MSR register will clear the delta modem status indications but has no effect on the status bits. The status bits reflect the state of the input pins regardless of the mask control signals. If a DCTS, DDSR, TERI, or DDCD are true and a state change occurs during a read operation (DlSTR, DISTR), the state change is not indicated in the MSR. If DCTS, DDSR, TERI, or DDCD are false and a state change occurs during a read operation, the state change is indicated after the read operation. For LSR and MSR, the setting of status bits is inhibited during status register read (DISTR, DlSTR) operations. If a status condition is generated during a read (DlSTR, DISTR) operation, the status bit is not set until the trailing edge of the read (DISTR, DISTR). If a status bit is set during a read (DlSTR, DISTR) operation, and the same status condition occurs, that status bit will be cleared at the trailing edge of the read (DlSTR, DISTR) instead of being set again. 16-bit Baud counter is immediately loaded. This prevents long counts on initial load. Sample Divisor Number Calculation: Given: Formula: Answer: Check: Desired Baud Rate 1200 Baud Frequency Input 1.8432MHz Divisor # = Frequency Input ÷ (Baud Rate x 16) Divisor # = 1843200 ÷ (1200 x 16) Divisor # = 96 = 60HEX → DLL = 01100000 DLM = 00000000 The Divisor # 96 will divide the input frequency 1.8432MHz down to 19200 which is 16 times the desired baud rate. Divisor Latch Least Significant BYTE DLL (0) Bit 0 DLL (1) Bit 1 DLL (2) Bit 2 DLL (3) Bit 3 DLL (4) Bit 4 DLL (5) Bit 5 DLL (6) Bit 6 DLL (7) Bit 7 Divisor Latch Most Significant BYTE DLM (0) Bit 8 DLM (1) Bit 9 DLM (2) Bit 10 DLM (3) Bit 11 DLM (4) Bit 12 DLM (5) Bit 13 DLM (6) Bit 14 DLM (7) Bit 15 RECEIVER BUFFER REGISTER (RBR) The receiver circuitry in the 82C50A is programmable for 5, 6, 7 or 8 data bits per character. For words of less than 8 bits, the data is right justified to the least significant bit (LSB = Data Bit 0 (RBR(0)). Data Bit 0 of a data word (RBR(0)) is the first data bit received. The unused bits in a character less than 8 bits are output low to the parallel output by the 82C50A. Received data at the SIN input pin is shifted into the Receiver Shift Register by the 16X clock provided at the RCLK input. This clock is synchronized to the incoming data based on the position of the start bit. When a complete character is shifted into the Receiver Shift Register, the assembled data bits are parallel loaded into the Receiver Buffer Register. The DR flag in the LSR register is set. Double buffering of the received data permits continuous reception of data without losing received data. While the Receiver Shift Register is shifting a new character into the 82C50A, the Receiver Buffer Register is holding a previously received character for the CPU to read. Failure to read the FN2958.5 August 24, 2006 BAUD RATE SELECT REGISTER (BRSR) The 82C50A contains a programmable Baud Rate Generator (BRG) that divides the clock (DC to 10MHz) by any divisor from 1 to 216-1 (see also BRG description). The output frequency of the Baud Generator is 16X the data rate [divisor # = frequency input ÷ (baud rate x 16)]. Two 8-bit divisor latch registers store the divisor in a 16-bit binary format. These Divisor Latch registers must be loaded during initialization. Upon loading either of the Divisor Latches, a 11 82C50A data in the RBR before complete reception of the next character result in the loss of the data in the Receiver Register. The OE flag in the LSR register indicates the overrun condition. RBR Bits 0 thru 7 RBR (0) RBR (1) RBR (2) RBR (3) RBR (4) RBR (5) RBR (6) RBR (7) SCR Bits 0 thru 7 SCR (0) SCR (1) SCR (2) SCR (3) SOR (4) SCR (5) SOR (6) SCR (7) Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Interrupt Structure INTERRUPT IDENTIFICATION REGISTER (IIR) The 82C50A has interrupt capability for interfacing to current microprocessors. In order to minimize software overhead during data character transfers, the 82C50A prioritizes interrupts into four levels. The four levels of interrupt conditions are as follows: 1. Receiver Line Status (Priority 1) 2. Received Data Ready (Priority 2) 3. Transmitter Holding Register Empty (Priority 3) 4. Modem Status (Priority 4). Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the Interrupt Identification Register (IIR). When addressed during chip select time, the lIR indicates the highest priority interrupt pending. No other interrupts are acknowledged until the interrupt is serviced by the CPU. The contents of the lIR are indicated in Table 2 and are described below. IIR(0): IIR(0) can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When IIR(0) is low, an interrupt is pending, and the lIR contents may be used as a pointer to the appropriate interrupt service routine. When lIR(0) is high, no interrupt is pending. IlR(1) and IIR(2): llR(1) and IlR(2) are used to identify the highest priority interrupt pending as indicated in Table 2. lIR(3) - IIR(7): These five bits of the lIR are logic 0. TRANSMITTER HOLDING REGISTER (THR) The Transmitter Holding Register (THR) holds parallel data from the data bus (D0-D7) until the Transmitter Shift Register is empty and ready to accept a new character for transmission. The transmitter and receiver word length and number of stop bits are the same. If the character is less than eight bits, unused bits at the microprocessor data bus are ignored by the transmitter. Data Bit 0 (THR(0)) is the first serial data bit transmitted. The THRE flag (LSR(5)) reflect the status of the THR. The TEMT flag (LSR(6)) indicates if both the THR and TSR are empty. THR Bits 0 thru 7 THR (0) THR (1) THR (2) THR (3) THR (4) THR (5) THR (6) THR (7) Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 SCRATCHPAD REGISTER (SCR) This 8-bit Read/Write register has no effect on the 82C50A. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. TABLE 2. INTERRUPT IDENTIFICATION REGISTER INTERRUPT IDENTIFICATION BIT 2 X 1 1 0 0 NOTE: BIT 1 X 1 0 1 0 BIT 0 1 0 0 0 0 First Second Third Fourth PRIORITY LEVEL INTERRUPT SET AND RESET FUNCTIONS INTERRUPT FLAG None Receiver Line Status Received Data Available THRE Modem Status INTERRUPT SOURCE None OE, PE, FE, or BI Receiver Data Available THRE CTS, DSR, RI, DCD LSR Read RBR Read IIR Read if THRE is the Interrupt Source or THR Write MSR Read INTERRUPT RESET CONTROL X = Not Defined, May Be 0 or 1 12 FN2958.5 August 24, 2006 82C50A INTERRUPT ENABLE REGISTER (IER) The Interrupt Enable Register (IER) is a Write register used to independently enable the four 82C50A interrupts which activate the interrupt (lNTRPT) output. All interrupts are disabled by resetting IER(0) - IER(3) of the Interrupt Enable Register. Interrupts are enabled by setting the appropriate bits of the IER high. Disabling the interrupt system inhibits the Interrupt Identification Register and the active (high) INTRPT output. All other system functions operate in their normal manner, including the setting of the Line Status and Modem Status Registers. The contents of the Interrupt Enable Register are indicated in Table 3 and are described below. IER(0): When programmed high (IER(0) = Logic 1), IER(0) enables Received Data Available interrupt. IER(1): When programmed high (IER(1) = Logic 1), IER(1) enables the Transmitter Holding Register Empty interrupt. IER(2): When Programmed high (IER(2) = Logic 1), IER(2) enables the Receiver Line Status interrupt. IER(3): When programmed high (IER(3) = Logic 1), IER(3) enables the Modem Status interrupt. IER(4) - IER(7): These four bits of the IER are logic 0. DR (LSR BIT 0) ERBFI (IER BIT 0) THRE (LSR BIT 5) ETBEI (IER BIT 1) OE (LSR BIT 1) PE (LSR BIT 2) FE (LSR BIT 3) BI (LSR BIT 4) ELSI (IER BIT 2) DCTS (MSR BIT 0) DDSR (MSR BIT 1) TERI (MSR BIT 2) DDCD (MSR BIT 3) EDSSI (IER BIT 3) INTRPT PIN 30 FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY (NOTE: See Table 1 for how to access these registers.) REGISTER MNEMONIC RBR (Read Only) THR (Write Only) DLL DLM IER BIT 7 Data Bit 7 (MSB) Data Bit 7 Bit 7 Bit 15 0 BIT 6 Data Bit 6 Data Bit 6 Bit 6 Bit 14 0 BIT 5 Data Bit 5 Data Bit 5 Bit 5 Bit 13 0 REGISTER BIT NUMBER BIT 4 BIT 3 Data Bit 4 Data Bit 3 Data Bit 4 Bit 4 Bit 12 0 Data Bit 3 Bit 3 Bit 11 (EDSSI) Enable Modem Status Interrupt BIT 2 Data Bit 2 Data Bit 2 Bit 2 Bit 10 (ELSI) Enable Receiver Line Status Interrupt Interrupt ID Bit (1) (STB) Number of Stop Bits Out 1 BIT 1 Data Bit 1 Data Bit 1 Bit 1 Bit 9 (ETBEI) Enable Transmitter Holding Register Empty Interrupt Interrupt ID Bit (0) (WLSB1) Word Length Select Bit 1 (RTS) Request to Send (OE) Overrun Error BIT 0 Data Bit 0 (LSB)† Data Bit 0 Bit 0 Bit 8 (ERBFI) Enable Received Data Available Interrupt “0” 1F Interrupt Pending (WLSB0) Word Length Select Bit 0 (DTR) Data Terminal Ready (DR) Data Ready IIR (Read Only) LCR 0 0 0 0 0 MCR (DLAB) Divisor Latch Access Bit 0 Set Break Stick Parity (EPS) Even Parity Select (PEN) Parity Enable 0 0 Loop Out 2 LSR 0 (TEMT) Transmitter Empty MSR (DCD) Data Carrier Detect (RI) Ring Indicator (THRE) Transmitter Holding Register Empty (DSR) Data Set Ready (BI) Break Interrupt (FE) Framing Error (PE) Parity Error (CTS) Clear to Send Bit 4 SCR Bit 7 Bit 6 Bit 5 †LSB, Data Bit 0 is the first bit transmitted or received. (DDCD) Delta Data Carrier Detect Bit 3 (TERI) Trailing Edge Ring Indicator Bit 2 (DDSR) Delta Data Set Ready Bit 1 (DCTS) Delta Clear to Send Bit 0 13 FN2958.5 August 24, 2006 82C50A Transmitter The serial transmitter section consists of a Transmitter Holding Register (THR), Transmitter Shift Register (TSR), and associated control logic. The Transmitter Holding Register Empty (THRE) and Transmitter Shift Register Empty (TEMT) are two bits in the Line Status Register which indicate the status of THR and TSR. To transmit a 5-8 bit word, the word is written through D0-D7 to the THR. The microprocessor should perform a write operation only if THRE is high. The THRE is set high when the word is automatically transferred from the THR to the TSR during the transmission of the start bit. When the transmitter is idle, both THRE and TEMT are high. The first word written causes THRE to be reset to 0. After completion of the transfer, THRE returns high. TEMT remains low for at least the duration of the transmission of the data word. If a second character is transmitted to the THR, the THRE is reset low. Since the data word cannot be transferred from the THR to the TSR until the TSR is empty, THRE remains low until the TSR has completed transmission of the word. When the last word has been transmitted out of the TSR, TEMT is set high. THRE is set high one THR to TSR transfer time later. Baud Rate Generator (BRG) The BRG generates the clocking for the UART function, providing standard ANSI/CCITT bit rates. The oscillator driving the BRG may be provided either with the addition of an external crystal to the XTAL1 and XTAL2 inputs, or an external clock into XTAL1. In either case, a buffered clock output, BAUDOUT, is provided for other system clocking. If two 82C50As are used on the same board, one can use a crystal, and the buffered clock output can be routed directly into the XTAL1 of the second 82C50A. The data rate is determined by the Divisor Latch registers DLL and DLM and the external frequency or crystal input, with the BAUDOUT providing an output 16X the data rate. The bit rate is selected by programming the two divisor latches, Divisor Latch Most Significant Byte and Divisor Latch Least Significant Byte. Setting DLL = 1 and DLM = 0 selects the divisor to divide by 1 (divide by 1 gives maximum baud rate for a given input frequency at XTAL1). The on-chip oscillator is optimized for a 10MHz crystal. Usually, higher frequency are less expensive than lower frequency crystals. The BRG can use any of three different popular crystals to provide standard baud rates. The frequency of these three common crystals on the market are 1.8432MHz, 2.4576MHz, and 3.072MHz. With these standard crystals, standard bit rates from 50 to 38.5kbps are available. The following tables illustrate the divisors needed to obtain standard rates using these three crystal frequencies. TABLE 4. BAUD RATES USING 1.8432MHz CRYSTAL DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 DIVISOR USED TO GENERATE 16 x CLOCK 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 0.026 0.058 0.69 2.86 Receiver Serial asynchronous data is input into the SIN pin. The idle state of the line providing the input into SIN is high. A start bit detect circuit continually searches for a high to low transition from the idle state. When the transition is detected, a counter is reset, and counts the 16X clock to 7 1/2, which is the center of the start bit. The start bit is valid if the SIN is still low at the mid bit sample of the start bit. Verifying the start bit prevents the receiver from assembling an incorrect data character due to a low going noise spike on the SIN input. The Line Control Register determines the number of data bits in a character (LCR(0), LCR(1)), number of stop bits LCR(2), if parity is used LCR(3), and the polarity of parity LCR(4). Status information for the receiver is provided in the Line Status Register. When a character is transferred from the Receiver Shift Register to the Receiver Buffer Register, the Data Received indication in LSR(0) is set high. The CPU reads the Receiver Buffer Register through D0-D7. This read resets LSR(0). If D0-D7 are not read prior to a new character transfer from the RSR to the RBR, the overrun error status indication is set in LSR(1). The parity check tests for even or odd parity on the parity bit, which precedes the first stop bit. If there is a parity error, the parity error is set in LSR (2). There is circuitry which tests whether the stop bit is high. If it is not, a framing error indication is generated in LSR(3). The center of the start bit is defined as clock count 7 1/2. If the data into SIN is a symmetrical square wave, the center of the data cells will occur within ±3.125% of the actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16X clock cycle prior to being detected. 14 FN2958.5 August 24, 2006 82C50A TABLE 5. BAUD RATES USING 2.4576MHz CRYSTAL DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 DIVISOR USED TO GENERATE 16 x CLOCK 3072 2048 1396 1142 1024 512 256 128 85 77 64 43 32 21 16 8 4 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 0.026 0.0007 0.392 0.260 0.775 1.587 TABLE 6. BAUD RATES USING 3.072MHz CRYSTAL DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 DIVISOR USED TO GENERATE 16 x CLOCK 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 0.026 0.034 0.312 0.628 1.23 - Reset After powerup, the 82C50A Master Reset Schmitt trigger input (MR) should be held high for TMRW ns to reset the 82C50A circuits to an idle mode until initialization. A high on MR causes the following: 1. Initializes the transmitter and receiver internal clock counters. 2. Clears the Line Status Register (LSR), except for Transmitter Shift Register Empty (TE MT) and Transmit Holding Register Empty (THRE), which are set. The Modem Control Register (MCR) is also cleared. All of the discrete lines, memory elements and miscellaneous logic associated with these register bits are also cleared or turned off. Divisor Latches, Receiver Buffer Register, Transmitter Buffer Register are not effected. Following removal of the reset condition (MR low), the 82C50A remains in the idle mode until programmed. A hardware reset of the 82C50A sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently enabled, an interrupt occurs due to THRE. A summary of the effect of a Master Reset on the 82C50A is given in Table 7. TABLE 7. 82C50A RESET OPERATIONS REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Register Line Control Register MODEM Control Register Line Status Register MODEM Status Register SOUT lntrpt (RCVR Errs) lntrpt (RCVR Data Ready) lntrpt (THRE) lntrpt (Modem Status Changes) Out2 RTS DTR Out1 RESET CONTROL Master Reset Master Reset Master Reset Master Reset Master Reset Master Reset Master Reset Read LSR/MR Read RBR/MR Read lIR/Write THR/MR Read MSR/MR Master Reset Master Reset Master Reset Master Reset RESET All Bits Low (0-3 forced and 4-7 permanent) Bit 0 is High, Bits 1 and 2 Low Bits 3-7 are Permanently Low All Bits Low All Bits Low All Bits Low, Except Bits 5 and 6 are High Bit 0-3 Low Bits 4-7 Input Signal High Low Low Low Low High High High High 15 FN2958.5 August 24, 2006 82C50A Programming The 82C50A is programmed by the control registers LCR, lER, DLL and DLM, and MCR. These control words define the character length, number of stop bits, parity, baud rate, and modem interface. While the control registers can be written in any order, the lER should be written to last because it controls the interrupt enables. Once the 82C50A is programmed and operational, these registers can be updated any time the 82C50A is not transmitting or receiving data. The control signals required to access 82C50A internal registers are shown below. The maximum frequency of the 82C50A is 10MHz with an external clock or a crystal attached to XTAL1 and XTAL2. Using the external clock or crystal, and a divide by one divisor, the maximum BAUDOUT is 10MHz, and the maximum data rate is 625Kbps. TABLE 8. TYPICAL CRYSTAL OSCILLATOR CIRCUIT PARAMETER Frequency Type of Operation Load Capacitance (CL) RSERIES (Max) 1.0 to 10MHz Parallel Resonant, Fundamental Mode 20 or 32pF (Typ) 100Ω (f = 10MHz, CL = 32pF) 200Ω (f = 10MHz, CL = 20pF) Software Reset A software reset of the 82C50A is a useful method for returning to a completely known state without a system reset. Such a reset consists of writing to the LCR, Divisor Latches, and MCR registers. The LSR and RBR registers should be read prior to enabling interrupts in order to clear out any residual data or status bits which may be invalid for subsequent operation. XTAL1 CL XTAL PIN 16 TO BAUD RATE GENERATOR LOGIC Crystal Operation The 82C50A crystal oscillator circuitry is designed to operate with a fundamental mode, parallel resonant crystal. Table 8 shows the required crystal parameters and crystal circuit configuration, respectively. When using an external clock source, the XTAL1 input is driven and the XTAL2 output is left open. Power consumption when using an external clock is typically 50% of that required when using a crystal. This is due to the sinusoidal nature of the drive circuitry when using a crystal. XTAL2 CL RS 82C50A PIN 17 FIGURE 2. TYPICAL CRYSTAL OSCILLATOR CIRCUIT 16 FN2958.5 August 24, 2006 82C50A Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) Operating Conditions Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range CX82C50A-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC IX82C50A-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Plastic DIP Package. . . . . . . . . . . . . . . 45 N/A Plastic LCC Package . . . . . . . . . . . . . . 50 N/A Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC Max Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . .+300oC (Lead Tips Only for Surface Mount Packages) Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1788 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications SYMBOL VIH VIL VTH VTL VIH (CLK) VlL (CLK) VOH VCC = 5.0V ±10%, TA = 0oC to +70oC (CX82C50A-5) TA = -40oC to +85oC (lX82C50A-5) MIN 2.0 2.0 VCC-0.8 3.0 VCC-0.4 MAX 0.8 0.8 0.8 0.4 +1.0 +10.0 6 UNITS V V V V V V V V V μA μA mA MR Input MR Input External Clock External Clock IOH = -2.5mA IOH = -100μA lOL = +2.5mA, VIN = GND or VCC, DIP Pins 9,10,12, 13, 14, 18, 19, 21, 22, 25-28, 35-39 VO = GND or VCC, DIP Pins 1-8 External Clock F = 2.4576MHz, VCC = 5.5V, VIN = VCC or GND, Outputs Open VCC = 5.5V, VIN = VCC or GND, Outputs Open TEST CONDITIONS PARAMETER Logical One Input Voltage Logical Zero Input Voltage Schmitt Trigger Logic One Input Voltage Schmitt Trigger Logic Zero Input Voltage Logical One Clock Voltage Logical Zero Clock Voltage Output High Voltage VOL II IO ICCOP Output Low Voltage Input Leakage Current Input/Output Leakage Current Operating Power Supply Current -1.0 -10.0 - ICCSB Standby Supply Current - 100 μA Capacitance TA = 25oC SYMBOL CIN COUT CI/O PARAMETER Input Capacitance Output Capacitance I/O Capacitance TYPICAL 15 15 20 UNITS pF pF pF TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND 17 FN2958.5 August 24, 2006 82C50A AC Electrical Specifications Timing Requirements 82C50A-5 SYMBOL (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) NOTE: 1. “When using the 82C50A in the multiplexed mode (ADS operational), it will operate in 80C86/88 systems with a maximum 3MHz operating frequency.” TAW TAS TAH TCS TCH TDIW TRC RC TDD TDDD THZ TDOW TWC WC TDS TDH PARAMETER Address Strobe Width Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time DISTR DlSTR Strobe Width Read Cycle Delay Read Cycle = TAR + TDIW + TRC DISTR DlSTR to Driver Disable Delay Delay From DISTR DlSTR to Data DlSTR DISTR to Floating Data Delay DOSTR DOSTR Strobe Width Write Cycle Delay Write Cycle = TAW + TDOW + TWC Data Setup Time Data Hold Time MIN 50 60 0 60 0 150 270 500 10 150 270 500 90 60 MAX 75 120 75 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 TEST CONDITIONS VCC = 5.0V ±10%, TA = 0oC to +70oC (CX82C50A-5) TA = -40oC to +85oC (lX82C50A-5) AC Electrical Specifications Timing VCC = 5.0V ±10%, TA = 0oC to +70oC (CX82C50A-5) TA = -40oC to +85oC (lX82C50A-5) 82C50A-5 SYMBOL DEMULTIPLEXED OPERATION (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) TCSC TRA TRCS TAR TCSR TWA TWCS TAW TCSW TMRW TXH TXL Chip Select Output Delay from Select Address Hold Time from DISTR DISTR Chip Select Hold Time from DISTR DISTR DISTR DISTR Delay from Address DISTR DISTR Delay from Chip Select Address Hold Time from DOSTR DOSTR Chip Select Hold Time from DOSTR DOSTR DOSTR DOSTR Delay from Address DOSTR DOSTR Delay from Select Master Reset Pulse Width Duration of Clock High Pulse Duration of Clock Low Pulse 20 20 80 80 20 20 80 80 500 40 40 125 ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER MIN MAX UNITS TEST CONDITIONS 18 FN2958.5 August 24, 2006 82C50A AC Electrical Specifications Timing (Continued) 82C50A-5 SYMBOL BAUD GENERATOR (29) (30) (31) (32) (33) N TBLD TBHD TLW THW Baud Divisor Baud Output Negative Edge Delay Baud Output Positive Edge Delay Baud Output Down Time Baud Output Up Time 1 40 40 216-1 250 250 ns ns ns ns TXL = 50ns TXH = 50ns PARAMETER MIN MAX UNITS TEST CONDITIONS VCC = 5.0V ±10%, TA = 0oC to +70oC (CX82C50A-5) TA = -40oC to +85oC (lX82C50A-5) RECEIVER (34) (35) (36) TSCD TSlNT TRlNT Delay from RCLK to Sample Time Delay from Stop to Set Interrupt Delay from DISTR DISTR (RD RBR) to Reset Interrupt 1 250 1 250 ns BAUDOUT Cycles ns TRANSMITTER (37) (38) (39) (40) (41) THR TlRS TS1 TSTl TIR Delay from DOSTR DOSTR to Reset Interrupt Delay from Initial INTR Reset to Transmit Start Delay from Initial Write to Interrupt Delay from Stop to Interrupt (THRE) Delay from DISTR DISTR (RD lIR) to Reset Interrupt (THRE) 8 16 8 250 24 32 24 250 ns BAUDOUT Cycles BAUDOUT Cycles BAUDOUT Cycles ns MODEM CONTROL (42) (43) (44) TMDO TSIM TRIM Delay from DOSTR DOSTR to Output Delay to Set Interrupt from Modem Input Delay to Reset Interrupt from DISTR DlSTR (RD MSR) 500 500 500 ns ns ns 19 FN2958.5 August 24, 2006 82C50A AC Test Circuit V1 R1 OUTPUT FROM DEVICE UNDER TEST C1 (NOTE) TEST POINT INPUT VIH + 0.4V VIL - 0.4V 1.5V OUTPUT 1.5V VOH VOL AC Testing Input, Output Waveform AC Testing: All input signals must switch between VIL -0.4V and VIH +0.4V. Input rise and fall times are driven at 1ns/V. NOTE: Includes stay and jig capacitance. TEST CONDITION DEFINITION TABLE IOH -2.5mA IOL +2.5mA V1 1.7V R1 520Ω C1 100pF Timing Waveforms tXH (27) 2.0V XTAL1 tXL (28) 0.8V 2.0V 0.8V 2.0V 0.8V FIGURE 3. EXTERNAL CLOCK INPUT FIGURE 4. AC TEST POINTS N (29) XTAL1 (31) tBHD (30) tBLD BAUD OUT (÷1) (31) tBHD (30) tBLD BAUD OUT (÷2) (30) tBLD BAUD OUT (÷3) (30) tBLD BAUD OUT (÷N, N > 3) (32) tLW = 2XTAL1 CYCLES (31) tBHD (33) tHW (31) tBHD tHW (33) tLW (32) tLW (32) tHW (33) tLW (32) tHW = (N - 2) XTAL1 CYCLES (33) NOTE: tBLD (÷1) is the only spec measure from XTL1 falling edge. All other tBLD’s and tBHD’s are measured from XTAL1 rising edge. FIGURE 5. BAUDOUT TIMING 20 FN2958.5 August 24, 2006 82C50A Timing Waveforms (Continued) (1) tAW ADS (2) tAS A2, A1, A0 (4) tCS CS2, CS1, CS0 VALID (17) tCSC† CSOUT (25) tCSW† (24) tAW† DOSTR/DOSTR (14) WC (13) tWC ACTIVE OR DISTR/DISTR (15) tDS DATA D0-D7 VALID DATA (16) tDH ACTIVE (23) tWCS† VALID (5) tCH (22) tWA† (3) tAH (12) tDOW ACTIVE † Applicable only when ADS is tied low. FIGURE 6. WRITE CYCLE (1) tAW ADS (2) tAS A2, A1, A0 (4) tCS CS2, CS1, CS0 VALID (17) tCSC† CSOUT (21) tCSR† (20) tAR† DISTR/DISTR (8) RC (6) tDIW ACTIVE OR DOSTR/DOSTR (9) tDD DD/S (10) tDDD VALID DATA (11) tHZ (9) tDD ACTIVE (7) tRC ACTIVE (19) tRCS† VALID (5) tCH (18) tRA† (3) tAH DATA D0-D7 † Applicable only when ADS is tied low. FIGURE 7. READ CYCLE 21 FN2958.5 August 24, 2006 82C50A Timing Waveforms (Continued) RCLK 8 CLKS SAMPLE CLK PARITY START SIN (RECEIVER INPUT DATA) DATA BITS (5-8) STOP tSCD (34) SAMPLE CLK tSINT (35) INTERRUPT (DATA READY OR RCVR ERR) DISTR/DISTR (READ REC DATA BUFFER OR ROLSR) NOTE 2 ACTIVE tRINT (36) NOTES: 1. See Write Cycle Timing. 2. See Read Cycle Timing. FIGURE 8. RECEIVER TIMING START SERIAL OUT (SOUT) INTERRUPT (THRE) DOSTR/DOSTR (WR THR) NOTE 1 DISTR/DISTR (RD IIR) NOTE 2 DATA (5-8) (38) tIRS (37) tHR (37) tHR PARITY STOP (1-2) START tSTI (40) (39) tSI tIR (41) NOTES: 1. See Write Cycle Timing. 2. See Read Cycle Timing. FIGURE 9. TRANSMITTER TIMING 22 FN2958.5 August 24, 2006 82C50A Timing Waveforms (Continued) ACTIVE DOSTR/DOSTR (WR MCR) NOTE 1 tMDO (42) RTS, DTR OUT1, OUT2 ACTIVE tMDO (42) CTS, DST, DCD tRIM (44) (43) tSIM DISTR/DISTR (RD MSR) NOTE 2 ACTIVE RI tRIM (44) tSIM (43) tSIM (43) INTERRUPT NOTES: 1. See Write Cycle Timing. 2. See Read Cycle Timing. FIGURE 10. MODEM CONTROLS TIMING 23 FN2958.5 August 24, 2006 82C50A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E40.6 (JEDEC MS-011-AC ISSUE B) 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 50.3 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 53.2 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.125 0.014 0.030 0.008 1.980 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 2.095 0.625 0.580 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.600 BSC 0.115 40 0.700 0.200 2.54 BSC 15.24 BSC 2.93 40 17.78 5.08 24 FN2958.5 August 24, 2006 82C50A Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C N44.65 (JEDEC MS-018AC ISSUE A) 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.165 0.090 0.685 0.650 0.291 0.685 0.650 0.291 44 MAX 0.180 0.120 0.695 0.656 0.319 0.695 0.656 0.319 MILLIMETERS MIN 4.20 2.29 17.40 16.51 7.40 17.40 16.51 7.40 44 MAX 4.57 3.04 17.65 16.66 8.10 17.65 16.66 8.10 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97 0.025 (0.64) R 0.045 (1.14) D2/E2 C L E1 E D2/E2 VIEW “A” A1 D D1 D2 E E1 D1 D 0.020 (0.51) MAX 3 PLCS A1 A 0.020 (0.51) MIN E2 N SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) MIN VIEW “A” TYP. 0.025 (0.64) MIN NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 FN2958.5 August 24, 2006