8406901RA

® 82C88 Data Sheet August 25, 2005 FN2979.2 CMOS Bus Controller The Intersil 82C88 is a high performance CMOS Bus Controller manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C88 provides the control and command timing signals for 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188 based systems. The high output drive capability of the 82C88 eliminates the need for additional bus drivers. Static CMOS circuit design insures low operating power. The Intersil advanced SAJI process results in performance equal to or greater than existing equivalent products at a significant power savings. Features • Compatible with Bipolar 8288 • Performance Compatible with: - 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz) - 80186/80188. . . . . . . . . . . . . . . . . . . . . . . . . . (6/8MHz) - 8086/8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz) - 8089 • Provides Advanced Commands for Multi-Master Busses • Three-State Command Outputs • Bipolar Drive Capability • Scaled SAJI IV CMOS Process • Single 5V Power Supply Pinouts 20 LD PDIP, CERDIP TOP VIEW IOB CLK S1 DT/ R ALE AEN MRDC AMWC MWTC 1 2 3 4 5 6 7 8 9 20 VCC 19 S0 18 S2 17 MCE/PDEN 16 DEN 15 CEN 14 INTA 13 IORC 12 AIOWC 11 IOWC • Low Power Operation - ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA (Max) - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max) • Operating Temperature Ranges - C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C - I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C - M82C88 . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER CP82C88 CP82C88Z (Note) PART MARKING CP82C88 CP82C88Z PACKAGE 20 Ld PDIP 20 Ld PDIP (Pb-free) TEMP RANGE (°C) 0 to +70 0 to +70 0 to +70 PKG. DWG. # E20.3 E20.3 E20.3 GND 10 20 LD PLCC, CLCC TOP VIEW CLK VCC IOB S1 S0 CP82C88-10 CP82C88-10 20 Ld PDIP IP82C88 CS82C88 IS82C88 18 S2 17 MCE/PDEN 16 DEN 15 CEN 14 INTA IP82C88 CS82C88 IS82C88 CD82C88 ID82C88 MD82C88/B 8406901RA SMD# 20 Ld CERDIP 20 Ld PLCC -40 to +85 E20.3 0 to +70 N20.35 3 DT/ R ALE AEN MRDC AMWC 4 5 6 7 8 9 MWTC 2 1 20 19 -40 to +85 N20.35 0 to +70 F20.3 CD82C88 ID82C88 MD82C88/B 8406901RA MR82C88/B 84069012A -40 to +85 F20.3 -55 to +125 F20.3 F20.3 MR82C88/B 20 Pad CLCC -55 to +125 J20.A 84069012A SMD# J20.A 10 GND 11 IOWC 12 AIOWC 13 IORC NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 82C88 Functional Diagram S0 S1 S2 MRDC MWTC AMWC IORC IOWC AIOWC INTA CLK CONTROL INPUT AEN CEN IOB CONTROL LOGIC CONTROL SIGNAL GENERATOR DT/R DEN MCE/PDEN ALE ADDRESS LATCH, DATA TRANSCEIVER, AND INTERRUPT CONTROL SIGNALS STATUS DECODER COMMAND SIGNAL GENERATOR MULTIBUSTM COMMAND SIGNALS VCC GND Pin Description PIN SYMBOL VCC GND S0, S1, S2 NUMBER 20 10 19, 3, 18 I TYPE DESCRIPTION VCC: The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling. GROUND. STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The 82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins are not in use (passive), command outputs are held HIGH (See Table1). CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock generator and serves to establish when command/control signals are generated. ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent D type latches, such as the 82C82 and 82C83H. DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This signal is active HIGH. DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory). ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH). COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled. INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections). ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal. AIOWC is active LOW. I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal is active LOW. I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal is active LOW. CLK ALE 2 5 I O DEN DT/R AEN 16 4 6 O O I CEN IOB AIOWC 15 1 12 I I O IOWC IORC 11 13 O O 2 FN2979.2 August 25, 2005 82C88 Pin Description PIN SYMBOL AMWC NUMBER 8 (Continued) TYPE O DESCRIPTION ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine cycle to give memory devices an early indication of a write instruction. Its timing is the same as a read command signal. AMWC is active LOW. MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on the data bus. This signal is active LOW. MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data bus. MRDC is active LOW. INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW. This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt sequence and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto the data bus. The MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables the data bus transceiver for the I/O bus that DEN performs for the system bus. PDEN is active LOW. MWTC MRDC INTA MCE/PDEN 9 7 14 17 O O O O Functional Description The command logic decodes the three 80C86, 8086, 80C88, 8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to determine what command is to be issued (see Table 1). TABLE 1. COMMAND DECODE DEFINITION S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 PROCESSOR STATE Interrupt Acknowledge Read I/O Port Write I/O Port Halt Code Access Read Memory Write Memory Passive 82C88 COMMAND INTA IORC IOWC, AIOWC None IOB mode if I/O or peripherals dedicated to one processor exist in a multi-processor system. System Bus Mode The 82C88 is in the System Bus mode if the IOB pin is strapped LOW. In this mode, no command is issued until a specified time period after the AEN line is activated (LOW). This mode assumes bus arbitration logic will inform the bus controller (on the AEN line) when the bus is free for use. Both memory and I/O commands wait for bus arbitration. This mode is used when only one bus exists. Here, both I/O and memory are shared by more than one processor. Command Outputs MRDC MRDC MWTC, AMWC None The advanced write commands are made available to initiate write procedures early in the machine cycle. This signal can be used to prevent the processor from entering an unnecessary wait state. INTA (Interrupt Acknowledge) acts as an I/O read during an interrupt cycle. Its purpose is to inform an interrupting device that its interrupt is being acknowledged and that it should place vectoring information onto the data bus. The command outputs are: MRDC - Memory Read Command MWTC - Memory Write Command IORC - I/O Read Command IOWC - I/O Write Command AMWC - Advanced Memory Write Command AIOWC - Advanced I/O Write Command INTA - Interrupt Acknowledge I/O Bus Mode The 82C88 is in the I/O Bus mode if the IOB pin is strapped HIGH. In the I/O Bus mode, all I/O command lines IORC, IOWC, AIOWC, INTA) are always enabled (i.e., not dependent on AEN). When an I/O command is initiated by the processor, the 82C88 immediately activates the command lines using PDEN and DT/R to control the I/O bus transceiver. The I/O command lines should not be used to control the system bus in this configuration because no arbitration is present. This mode allows one 82C88 Bus Controller to handle two external busses. No waiting is involved when the CPU wants to gain access to the I/O bus. Normal memory access requires a “Bus Ready” signal (AEN LOW) before it will proceed. It is advantageous to use the 3 FN2979.2 August 25, 2005 82C88 Control Outputs The control outputs of the 82C88 are Data Enable (DEN), Data Transmit/Receive (DT/R) and Master Cascade Enable/ Peripheral Data Enable (MCE/PDEN). The DEN signal determines when the external bus should be enabled onto the local bus and the DT/R determines the direction of data transfer. These two signals usually go to the chip select and direction pins of a transceiver. The MCE/PDEN pin changes function with the two modes of the 82C88. When the 82C88 is in the IOB mode (IOB HIGH), the PDEN signal serves as a dedicated data enable signal for the I/O or Peripheral System bus. Interrupt Acknowledge and MCE The MCE signal is used during an interrupt acknowledge cycle if the 82C88 is in the System Bus mode (IOB LOW). During any interrupt sequence, there are two interrupt acknowledge cycles that occur back to back. During the first interrupt cycle no data or address transfers take place. Logic should be provided to mask off MCE during this cycle. Just before the second cycle begins the MCE signal gates a master Priority Interrupt Controller’s (PIC) cascade address onto the processor’s local bus where ALE (Address Latch Enable) strobes it into the address latches. On the leading edge of the second interrupt cycle, the addressed slave PIC gates an interrupt vector onto the system data bus where it is read by the processor. If the system contains only one PIC, the MCE signal is not used. In this case, the second Interrupt Acknowledge signal gates the interrupt vector onto the processor bus. Address Latch Enable and Halt Address Latch Enable (ALE) occurs during each machine cycle and serves to strobe the current address into the 82C82/82C83H address latches. ALE also serves to strobe the status (S0, S1, S2) into a latch for halt state decoding. Command Enable The Command Enable (CEN) input acts as a command qualifier for the 82C88. If the CEN pin is high, the 82C88 functions normally. If the CEN pin is pulled LOW, all command lines are held in their inactive state (not threestate). This feature can be used to implement memory partitioning and to eliminate address conflicts between system bus devices and resident bus devices. 4 FN2979.2 August 25, 2005 82C88 Absolute Maximum Ratings Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) CERDIP Package. . . . . . . . . . . . . . . . 75 18 CLCC Package . . . . . . . . . . . . . . . . . 85 22 PDIP Package . . . . . . . . . . . . . . . . . . 75 N/A PLCC Package. . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C (PLCC - Lead Tips Only) Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C M82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications VCC = 5.0V ± 10%; TA = 0°C to +70°C (C82C88); TA = -40°C to +85°C (I82C88); TA = -55°C to +125°C (M82C88) MIN 2.0 2.2 VCC -0.8 3.0 VCC -0.4 3.0 VCC -0.4 -1.0 -50 -10.0 MAX 0.8 0.8 0.5 0.4 1.0 -300 10.0 10 1 UNITS V V V V V V V V V V V µA µA µA µA mA/MHz IOH = -8.0mA IOH = -2.5mA IOH = -4.0mA IOH = -2.5mA IOL= +12.0mA IOL = +8.0mA VIN = GND or VCC, except S0, S1, S2, DIP Pins 1-2, 6, 15 VIN = 2.0V, S0, S1, S2 (See Note 1) VO = GND or VCC, IOB = GND, AEN = VCC, DIP Pins 7-9, 11-14 VCC = 5.5V, VIN = VCC or GND, Outputs Open VCC = 5.5V, Outputs Open (See Note 2) TEST CONDITIONS C82C88, I82C88 M82C88 SYMBOL VIH VIL VIHC VILC VOH PARAMETER Logical One Input Voltage Logical Zero Input Voltage CLK Logical One Input Voltage CLK Logical Zero Input Voltage Output High Voltage Command Outputs Output High Voltage Control Outputs VOL Output Low Voltage Command Outputs Output Low Voltage Control Outputs II IBHH IO ICCSB ICCOP NOTES: Input Leakage Current Input Leakage Current-Status Bus Output Leakage Current Standby Power Supply Operating Power Supply Current 1. IBHH should be measured after raising the VIN on S0, S1, S2 to VCC and then lowering to valid input high level of 2.0V. 2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL) Capacitance TA = +25°C SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance TYPICAL 10 17 UNITS pF pF TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND 5 FN2979.2 August 25, 2005 82C88 AC Electrical Specifications VCC = 5.0V ± 10%; TA = 0°C to +70°C (C82C88); TA = -40°C to +85°C (I82C88); TA = -55°C to +125°C (M82C88) 8MHz SYMBOL TIMING REQUIREMENTS (1) TCLCL (2) TCLCH (3) TCHCL (4) TSVCH (5) TCHSV (6) TSHCL (7) TCLSH CLK Cycle Period CLK Low Time CLK High Time Status Active Setup Time Status Inactive Hold Time Status Inactive Setup Time Status Active Hold Time 125 55 40 35 10 35 10 100 50 37 35 10 35 10 83 34 34 35 5 35 5 ns ns ns ns ns ns ns PARAMETER MIN MAX 10MHz MIN MAX 12MHz MIN MAX UNITS TEST CONDITIONS TIMING RESPONSES (8) TCVNV (9) TCVNX (10) TCLLH (11) TCLMCH (12) TSVLH (13) TSVMCH (14) TCHLL (15) TCLML (16) TCLMH (17) TCHDTL (18) TCHDTH (19) TAELCH (20) TAEHCZ (21) TAELCV (22) TAEVNV (23) TCEVNV (24) TCELRH (25) TLHLL NOTES: 1. TAELCH measurement is between 1.5V and 2.5V. 2. TAEHCZ measured at 0.5V change in VOUT. Control Active Delay Control Inactive Delay ALE Active Delay (from CLK) MCE Active Delay (from CLK) ALE Active Delay (from Status) MCE Active Delay (from Status) ALE Inactive Delay Command Active Delay Command Inactive Delay Direction Control Active Delay Direction Control Inactive Delay Command Enable Time (Note 1) Command Disable Time (Note 2) Enable Delay Time AEN to DEN CEN to DEN, PDEN CEN to Command ALE High Time 5 10 4 5 5 110 TCLCH 10 45 45 20 25 20 30 18 35 35 50 30 40 40 250 25 25 TCLML +10 5 10 4 5 5 110 TCLCH 10 45 45 20 23 20 23 18 35 35 50 30 40 40 250 25 25 TCLML 5 10 4 5 5 110 TCLCH 10 45 35 20 23 20 23 18 35 35 50 30 40 40 250 25 25 TCLML n ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 2 2 1 1 3 4 2 1 1 2 1 6 FN2979.2 August 25, 2005 82C88 AC Testing Input, Output Waveform INPUT VIH +0.4V 1.5V VIL -0.4V OUTPUT VOH 1.5V VOL A.C. Testing: All input signals (other than CLK) must switch between VIL -0.4V and VIH +0.4. CLK must switch between 0.4V and VCC -0.4V. Input rise and fall times are driven at 1ns/V. A.C. Test Circuit V1 R1 OUTPUT FROM DEVICE UNDER TEST NOTE: INCLUDES STRAY AND JIG CAPACITANCE TEST POINT C1 (SEE NOTE) TABLE 2. TEST CONDITION DEFINITION TABLE TEST CONDITION 1 2 3 4 V1 2.13V 2.29V 1.5V 1.5V R1 220Ω 91Ω 187Ω 187Ω C1 80pF 300pF 300pF 50pF 7 FN2979.2 August 25, 2005 82C88 Timing Waveforms (Note 3) STATE T4 T1 TCLCL (1) CLK TCHSV (5) S2, S1, S0 TSVCH (4) TCLCH (2) TCHCL (3) TSHCL (6) T2 T3 T4 TCLSH (7) ADDRESS/DATA TCLLH (10) ALE 2 ADDRESS VALID TCHLL (14) TSVLH (12) WRITE 1 DATA VALID TCLMH (16) MRDC, IORC, INTA, AMWC, AIOWC TCLML (15) MWTC, IOWC TCVNV (8) TCLML (15) DEN (READ) (INTA) TCVNX (9) PDEN (READ) (INTA) TCVNV (8) DEN (WRITE) TCVNX (9) PDEN (WRITE) TCHDTH (18) DT/R (READ) (INTA) TCHDTL (17) MCE TCLMCH (11) 2 TCVNX (9) TCHDTH (18) NOTES: TSVMCH (13) 1. Address/Data Bus is shown only for reference purposes. 2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last. 3. All timing measurements are made at 1.5V unless otherwise specified. FIGURE 1. 8 FN2979.2 August 25, 2005 82C88 Timing Waveforms (Note 3) CEN (Continued) AEN TAEVNV (22) DEN TCEVNV (23) PDEN FIGURE 2. DEN, PDEN QUALIFICATION TIMING AEN TAELCV (21) 1.5V TAELCH (19) VOH TAEHCZ (20) 1.5V OUTPUT COMMAND TCELRH (24) CEN TCELRH (24) 0.5V VOH CEN MUST BE LOW OR INVALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED. FIGURE 3. ADDRESS ENABLE (AEN) TIMING (THREE-STATE ENABLE/DISABLE) NOTES: 1. Address/Data Bus is shown only for reference purposes. 2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last. 3. All timing measurements are made at 1.5V unless otherwise specified. 9 FN2979.2 August 25, 2005 82C88 Burn-In Circuits MD82C88 CERDIP R1 F7 R1 F0 R2 F3 A A R1 F5 A A A VCC C1 6 7 8 9 10 15 14 13 12 11 3 4 5 18 17 16 R1 F6 A R3 A A A A R3 VCC 2 19 R2 F2 A A 1 20 R2 F4 VCC MR82C88 CLCC F3 F0 F7 VCC F4 R1 R4 R4 R1 3 R4 VCC/ 2 R4 VCC/ 2 R1 F5 R4 VCC/ 2 R4 VCC/ 2 7 8 9 R4 C1 VCC VCC/ 2 4 5 6 2 1 20 19 R2 18 R4 17 R4 16 R1 15 R4 14 VCC/ 2 F6 VCC/ 2 VCC/ 2 F2 10 11 12 13 R4 R4 R4 VCC/ 2 NOTES: 1. VCC = 5.5V ± 0.5V GND = 0V 2. VIH = 4.5V ± 10% VIL = -0.2V to +0.4V 3. Component Values: R1 = 47kΩ, 1/4W, 5% R2 = 1.5kΩ, 1/4W, 5% R3 = 10kΩ, 1/4W, 5% R4 = 1.2kΩ, 1/4W, 5% C1 = 0.01µF (Min) F0 = 100kHz ± 10% F1 = F0/2 F2 = F1/2 . . . F7 = F6/2 10 FN2979.2 August 25, 2005 82C88 Die Characteristics DIE DIMENSIONS: 103.5 x 116.5 x 19 ± 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 2kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ WORST CASE CURRENT DENSITY: 1.9 x 105 A/cm2 Metallization Mask Layout 82C88 S1 CLK IOB VCC S0 S2 DT/R MCE/ PDEN ALE DEN AEN CEN MRDC INTA AMWC MWTC GND IOWC AIOWC IORC All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN2979.2 August 25, 2005