ACS20DMSR

ACS20MS April 1995 Radiation Hardened Dual 4-Input NAND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C TOP VIEW A1 1 B1 2 NC 3 C1 4 D1 5 Y1 6 GND 7 14 VCC 13 D2 12 C2 11 NC 10 B2 9 A2 8 Y2 Features • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD (Si) • Single Event Upset (SEU) Immunity 80 MEV-cm2/mg • Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min • Input Current ≤1µA at VOL, VOH 14 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C TOP VIEW A1 B1 NC C1 D1 Y1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D2 C2 NC B2 A2 Y2 Description The Intersil ACS20MS is a radiation hardened dual 4-input NAND gate. A low on any input forces the output to a high logic state. The ACS20MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. Ordering Information PART NUMBER ACS20DMSR ACS20KMSR ACS20D/Sample ACS20K/Sample ACS20HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 14 Lead SBDIP 14 Lead Ceramic Flatpack 14 Lead SBDIP 14 Lead Ceramic Flatpack Die Truth Table INPUTS An L X X X H Bn X L X X H Cn X X L X H Dn X X X L H OUTPUT Yn H H H H L Functional Diagram (1, 9) An Bn (2, 10) (6, 8) Yn (4, 12) Cn Dn (5, 13) NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Spec Number 1 518815 File Number 3616 Specifications ACS20MS Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V Input Voltage Range . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA DC Drain Current, Any One Output . . . . . . . . . . . . . . . . . . . . . . .±50mA Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (All Voltages Reference to VSS) Reliability Information Thermal Impedance θJA θJC DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . 116oC/W 30oC/W Maximum Package Power Dissipation at +125oC DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4W Maximum Device Power Dissipation. . . . . . . . . . . . . . . . . . .(TBD)W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Time at 4.5V VCC (TR, TF) . . . . . . .10ns/ V Max Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . VCC to 70% of VCC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . .0V to 30% of VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Source) IOH VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V, (Note 2) VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOH = -50µA VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOH = -50µA Output Voltage Low VOL VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOL = 50µA VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOL = 50µA Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN -12 -8 12 8 VCC -0.1 MAX 5 100 UNITS µA µA mA mA mA mA V PARAMETER Supply Current SYMBOL ICC (NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL Output Voltage High VOH 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V 1 2, 3 +25oC +125oC, -55oC +25oC, +125oC, -55oC - ±0.5 ±1.0 - µA µA V Noise Immunity Functional Test NOTES: FN VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, (Note 3) 7, 8A, 8B 1. All voltages referenced to device GND. 2. Force/Measure functions may be interchanged. 3. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”. Spec Number 2 518815 Specifications ACS20MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTES 1, 2) CONDITIONS VCC = 4.5V, VIH = 4.5V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VIL = 0V GROUP A SUBGROUPS 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC MIN 2 2 MAX 12 15 UNITS ns ns PARAMETER Propagation Delay Input to Output SYMBOL TPHL TPLH NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation Input Capacitance NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0 VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0 VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOH = -50µA VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOH = -50µA Output Voltage Low VOL VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOL = 50µA VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOL = 50µA Input Leakage Current Noise Immunity Functional Test Propagation Delay Input to Output IIN FN TPHL TPLH VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, (Note 2) VCC = 4.5V, VIH = 4.5V, VIL = 0V RAD LIMITS TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25 oC SYMBOL CPD CIN CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz NOTE 1 1 TEMP +25oC +125oC +25 C +125oC o MIN - TYP 18 20 - MAX 10 10 UNITS pF pF pF pF PARAMETER Supply Current Output Current (Source) Output Current (Sink) Output Voltage High SYMBOL ICC IOH IOL VOH MIN -8.0 8.0 VCC -0.1 VCC -0.1 2 MAX 100 0.1 0.1 ±1 15 UNITS µA mA mA V V V V µA V ns +25oC NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”. TABLE 5. DELTA PARAMETERS (+25oC) PARAMETER Supply Current Output Current NOTE: 1. All delta calculations are referenced to 0 hour readings or pre-life readings. ICC IOL/IOH SYMBOL (NOTE 1) DELTA LIMIT ±1.0 ±15 UNITS µA % Spec Number 3 518815 Specifications ACS20MS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test 1 (Postburn-In) Interim Test 2 (Postburn-In) PDA Interim Test 3 (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUP Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. BURN-IN TEST CONNECTIONS (+125oC < TA < 139oC) OSCILLATOR OPEN STATIC 1 BURN-IN (Notes 1, 2) 1, 2, 4, 5, 7, 9, 10, 12, 13 3, 6, 8, 11 14 GROUND 1/2 VCC = 3V ±0.5V VCC = 6V ±0.5V 50kHz 25kHz METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1) METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11 ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H STATIC 2 BURN-IN (Notes 1, 2) DYNAMIC BURN-IN (Notes 1, 2) NOTES: 1. Each lead except VCC and GND will have a series resistor of 500Ω ±5%. 2. No-connect pins 3 and 11 may be connected to any voltage level. TABLE 9. IRRADIATION TEST CONNECTIONS FUNCTION Irradiation Circuit (Note 1) NOTE: 1. Each pin except VCC and GND will have a series resistor of 47kΩ ±5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures. OPEN 3, 6, 8, 11 GROUND 7 VCC = 5V ±0.5V 1, 2, 4, 5, 9, 10, 11, 12, 13, 14 7 3, 6, 8, 11 14 1, 2, 4, 5, 9, 10, 12, 13 7 3, 6, 8, 11 1, 2, 4, 5, 9, 10, 12, 13 - Spec Number 4 518815 Specifications ACS20MS Intersil - Space Products MS Screening Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull Method 2023 100% Internal Visual Inspection Method 2010 100% Temperature Cycling Method 1010 Condition C (-65o to +150oC) 100% Constant Acceleration 100% PIND Testing 100% External Visual Inspection 100% Serialization 100% Initial Electrical Test 100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min 100% Interim Electrical Test 1 (Note 1) NOTES: 1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). 2. These steps are optional, and should be listed on the purchase order if required. 3. Data Package Contents: Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity). Certificate of Conformance (as found on shipper). Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number). Variables Data (All Read, Record, and delta operations). Group A Attributes Data Summary. Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage. X-Ray Report and Film, including penetrometer measurements. GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose, Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil. 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min 100% Interim Electrical Test 2 (Note 1) 100% Dynamic Burn-In Method 1015, 240 Hours at +125oC or 180 Hours at +135oC 100% Interim Electrical Test 3 (Note 1) 100% Final Electrical Test 100% Fine and Gross Seal Method 1014 100% Radiographics Method 2012 (2 Views) 100% External Visual Method 2009 Group A (All Tests) Method 5005 (Class S) Group B (Optional) Method 5005 (Class S) (Note 2) Group D (Optional) Method 5005 (Class S) (Note 2) CSI and/or GSI (Optional) (Note 2) Data Package Generation (Note 3) Propagation Delay Timing Diagram and Load Circuit DUT VIH VS VSS TPLH TPHL VOH VS VOL OUTPUT INPUT CL 50pF TEST POINT RL 500Ω AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND ACS 4.50 4.50 2.25 0 0 UNITS V V V V V Spec Number 5 518815 ACS20MS Die Characteristics DIE DIMENSIONS: 88 mils x 88 mils 2,240mm x 2,240mm METALLIZATION: Type: AlSiCu Metal 1 Thickness: 6.75kÅ (Min), 8.25kÅ (Max) Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max) GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ DIE ATTACH: Material: Silver Glass or JM7000 Polymer after 7/1/95 WORST CASE CURRENT DENSITY: < 2.0 x 105 A/cm2 BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110µm x 110µm Metallization Mask Layout ACS20MS B1 (2) A1 (1) VCC (14) D2 (13) NC (3) (12) C2 C1 (4) (11) NC NC (X) (X) NC D1 (5) (10) B2 (6) Y1 (7) GND (8) Y2 (9) A2 Spec Number 6 518815 ACS20MS Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C) 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94 E M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS c c1 D eA E e eA eA/2 e eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 ccc M C A - B S D S aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. L Q S1 S2 α aaa bbb ccc M N Spec Number 7 518815 ACS20MS Ceramic Metal Seal Flatpack Packages (Flatpack) A e PIN NO. 1 ID AREA A K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B) 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.235 0.125 0.030 MAX 0.115 0.022 0.019 0.009 0.006 0.390 0.260 0.290 MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 5.97 3.18 0.76 1.27 BSC 0.20 6.86 0.66 0.13 14 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 9.91 6.60 7.11 NOTES 3 3 7 2 8 6 Rev. 0 5/18/94 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -A- -B- D A b S1 b E1 b1 c c1 D 0.004 M Q A -C- H A-B S DS E 0.036 M H A-B S C DS E E1 E2 -D-H- L E3 E2 E3 LEAD FINISH L E3 e k L 0.050 BSC 0.008 0.270 0.026 0.005 14 0.015 0.370 0.045 0.0015 SEATING AND BASE PLANE c1 BASE METAL b1 M M (b) SECTION A-A (c) Q S1 M N NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 8 518815