AD7545_01

UCT T PR O D ODUC OLETE STITUTE PR RSIL OBS SU B NTE SIBLE 1-888-I om A POS pplicatio ns DatailSheet .c FO R ters ntral A pp@in call Ce mail: centa or e TM AD7545 May 2001 File Number 3108.3 12-Bit, Buffered, Multiplying CMOS DAC itle D75 ) bjec 2t, ffer , ltip ng OS C) utho ) eyw s tersi rpor on, ico ucto ltip ng, L, OS reato ) OCI O fmar The AD7545 is a low cost monolithic 12-bit, CMOS multiplying DAC with on-board data latches. Data is loaded in a single 12-bit wide word which allows interfacing directly to most 12-bit and 16-bit bus systems. Loading of the input latches is under the control of the CS and WR inputs. A logic low on these control inputs makes the input latches transparent allowing direct unbuffered operation of the DAC. Features • 12-Bit Resolution • Low Gain T.C. 2ppm/oC (Typ) • Fast TTL/CMOS Compatible Data Latches • Single +5V to +15V Supply • Low Power • Low Cost Part Number Information PART NUMBER AD7545JN AD7545KN TEMP. RANGE ( oC) 0 to 70 0 to 70 PACKAGE 20 Ld PDIP 20 Ld PDIP PKG. NO. E20.3 E20.3 Pinout AD7545 (PDIP) TOP VIEW OUT 1 1 2 3 4 5 6 7 8 9 20 RFB 19 VREF 18 VDD 17 WR 16 CS 15 DB0 (LSB) 14 DB1 13 DB2 12 DB3 11 DB4 Functional Diagram RFB 20 AD7545 R VREF 19 12-BIT MULTIPLYING DAC 12 WR 17 INPUT DATA LATCHES CS 16 12 3 DGND 18 VDD 1 2 OUT1 AGND AGND DGND DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 10 DB11 - DB0 (PINS 4 - 15) ge de seO 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001 AD7545 Absolute Maximum Ratings Supply Voltage (VDD to DGND). . . . . . . . . . . . . . . . . . . -0.3V, +17V Digital Input Voltage to DGND . . . . . . . . . . . . . . . . -0.3V, VDD +0.3V VRFB , VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, VDD +0.3V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, VDD +0.3V Thermal Information Thermal Resistance (Typical, Note 1) θJA ( oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature (PDIP Package) . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications TA = See Note 2, VREF = +10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified VDD = +5V (NOTE 7) VDD = +15V (NOTE 7) MIN TYP MAX UNITS PARAMETER STATIC PERFORMANCE Resolution Relative Accuracy J K Differential Nonlinearity J K Gain Error (Using Internal RFB) J K TEST CONDITIONS MIN TYP MAX 12 10-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX DAC Register Loaded with 1111 1111 1111 Gain Error is Adjustable Using the Circuits of Figures 5 and 6 (Note 3) Typical Value is 2ppm/oC for VDD = +5V (Note 4) ∆VDD = ±5% J, K DB0 - DB11 = 0V; WR , CS = 0V (Note 2) - - ±2 ±1 ±4 ±1 ±20 ±10 12 - - ±2 ±1 ±4 ±1 ±25 ±15 Bits LSB LSB LSB LSB LSB LSB Gain Temperature Coefficient ∆Gain/∆Temperature DC Supply Rejection ∆Gain/∆VDD Output Leakage Current at OUT1 0.015 - - ±5 0.03 50 0.01 - - ±10 0.02 50 ppm/oC % nA DYNAMIC CHARACTERISTICS Current Settling Time To 1/2 LSB, OUT1 LOAD = 100Ω, DAC Output Measured from Falling Edge of WR, CS = 0V (Note 4) 2 2 µs Propagation Delay from Digital Input OUT1 LOAD = 100Ω , Change to 90% of Final Analog Output CEXT = 13pF (Notes 4 and 5) Digital to Analog Glitch Impulse AC Feedthrough at OUT1 ANALOG OUTPUTS Output Capacitance COUT1 DB0 - DB11 = 0V, WR, CS = 0V (Note 4) DB0 - DB11 = VDD , WR , CS = 0V (Note 4) VREF = AGND VREF = ±10V, 10kHz Sinewave - 400 5 300 - - 250 5 250 - ns nV/s mVP-P - - 70 200 - - 70 200 pF pF 2 AD7545 Electrical Specifications TA = See Note 2, VREF = +10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified (Continued) V DD = +5V (NOTE 7) PARAMETER REFERENCE INPUT Input Resistance (Pin 19 to GND) Input Resistance TC = -300ppm/oC (Typ) Typical Input Resistance = 11kΩ DIGITAL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN Input Capacitance DB0 DB11 VIN = 0 or VDD (Note 6) VIN = 0 (Note 4) 2.4 ±1 0.8 ±10 7 20 ±1 13.5 1.5 ±10 7 20 V V µA pF pF 7 25 7 25 kΩ kΩ TEST CONDITIONS MIN TYP MAX VDD = +15V (NOTE 7) MIN TYP MAX UNITS WR, CS VIN = 0 (Note 4) SWITCHING CHARACTERISTICS (Note 4) Chip Select to Write Setup Time, tCS Chip Select to Write Hold Time, tCH Write Pulse Width, tWR Data Setup Time, tDS Data Hold Time, tDH See Figure 1 See Figure 1 tCS ≥ tWR , tCH ≥ 0, See Figure 1 See Figure 1 See Figure 1 380 0 400 210 10 200 175 100 - - 200 0 240 120 10 120 100 60 - - ns ns ns - ns ns POWER SUPPLY CHARACTERISTICS IDD All Digital Inputs VIL or VIH All Digital Inputs 0V or VDD All Digital Inputs 0V or VDD NOTES: 2. Temperature Ranges as follows: J, K versions: 0oC to 70oC TA = 25oC for TYP Specifications. MIN and MAX are measured over the specified operating range. 3. This includes the effect of 5ppm maximum gain TC. 4. Parameter not tested. Parameter guaranteed by design, simulation, or characterization. 5. DB0 - DB11 = 0V to VDD or VDD to 0V. 6. Logic inputs are MOS gates. Typical input current (25oC) is less than 1nA. 7. Typical values are not guaranteed but reflect mean performance specification. Specifications subject to change without notice. 100 10 2 500 100 10 2 500 mA µA µA Timing Diagrams tCH CHIP SELECT tCS VDD 0 WRITE tWR tDH tDS DATA IN (DB0 - DB11) DATA VALID VDD 0 VDD 0 tDS DATA IN (DB0 - DB11) DATA VALID WRITE tWR tDH CHIP SELECT tCS tCH VDD 0 VDD 0 VDD 0 FIGURE 1A. TYPICAL WRITE CYCLE FIGURE 1B. PREFERRED WRITE CYCLE FIGURE 1. WRITE CYCLE TIMING DIAGRAM 3 AD7545 MODE SELECTION HOLD MODE: WRITE MODE: CS and WR low, DAC responds Either CS or WR high, data bus to data bus (DB0 - DB11) inputs (DB0 - DB11) is locked out; DAC holds last data present when WR or CS assumed high state. NOTES: 8. VDD = +5V; tr = tf = 20ns. 9. VDD = +15V; tr = tf = 40ns. 10. All input signal rise and fall times measured from 10% to 90% of VDD . 11. Timing measurement reference level is (VIH + VIL)/2. 12. Since input data latches are transparent for CS and WR both low, it is preferred to have data valid before CS and WR both go low. This prevents undesirable changes at the analog output while the data inputs settle. INPUTS BUFFERS TO OUT1 SWITCH Circuit Information - Digital Section Figure 4 shows the digital structure for one bit. The digital signals CONTROL and CONTROL are generated from CS and WR. TO AGND SWITCH CONTROL CONTROL FIGURE 4. DIGITAL INPUT STRUCTURE Circuit Information - D/A Converter Section Figure 2 shows a simplified circuit of the D/A converter section of the AD7545. Note that the ladder termination resistor is connected to AGND. R is typically 11kΩ. The binary weighted currents are switched between the OUT1 bus line and AGND by N-Channel switches, thus maintaining a constant current in each ladder leg independent of the switch state. One of the current switches is shown in Figure 3. VREF R R R R The input buffers are simple CMOS inverters designed such that when the AD7545 is operated with VDD = 5V, the buffers convert TTL input levels (2.4V and 0.8V) into CMOS logic levels. When VIN is in the region of 2.0V to 3.5V the input buffers operate in their linear region and draw current from the power supply. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (V DD and DGND) as is practically possible. The AD7545 may be operated with any supply voltage in the range 5V ≤ VDD ≤ 15V. With V DD = +15V the input logic levels are CMOS compatible only, i.e., 1.5V and 13.5V. Application 2R 2R 2R 2R 2R 2R Output Offset RFB OUT1 AGND DB11 (MSB) DB10 DB9 DB1 DB0 (LSB) FIGURE 2. SIMPLIFIED D/A CIRCUIT OF AD7545 TO LADDER FROM INTERFACE LOGIC CMOS current-steering D/A converters exhibit a code dependent output resistance which in turn causes a code dependent amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output which depends on VOS where VOS is the amplifier input offset voltage. To maintain monotonic operation it is recommended that V OS be no greater than (25 x 10-6) (VREF) over the temperature range of operation. General Ground Management AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7545. In more complex systems where the AGND and DGND connection is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7545 AGND and DGND pins (1N914 or equivalent). AGND OUT1 FIGURE 3. N-CHANNEL CURRENT STEERING SWITCH The capacitance at the OUT1 bus line, COUT1, is code dependent and varies from 70pF (all switches to AGND) to 200pF (all switches to OUT1). The input resistance at VREF (Figure 2) is always equal to RLDR (RLDR is the R/2R ladder characteristic resistance and is equal to the value “R”). Since RIN at the VREF pin is constant, the reference terminal can be driven by a reference voltage or a reference current, AC or DC, of positive or negative polarity. (If a current source is used, a low temperature coefficient external RFB is recommended to define scale factor). 4 Digital Glitches When WR and CS are both low the latched are transparent and the D/A converter inputs follow the data inputs. In some bus systems, data on the data bus is not always valid for the whole period during which WR is low and as a result invalid data can briefly occur at the D/A converter inputs during a write cycle. Such invalid data can cause unwanted glitches at the output of the D/A converter. The solution to this AD7545 problem, if it occurs, is to retime the write pulse (WR) so that it only occurs when data is valid. Another cause of digital glitches is capacitive coupling from the digital lines to the OUT1 and AGND terminals. This should be minimized by isolating the analog pins of the AD7545 (pins 1, 2, 19, 20) from the digital pins by a ground track run between pins 2 and 3 and between pins 18 and 19 of the AD7545. Note how the analog pins are at one end of the package and separated from the digital pins by VDD and DGND to aid isolation at the board level. On-chip capacitive coupling can also give rise to crosstalk from the digital to analog sections of the AD7545, particularly in circuits with high currents and fast rise and fall times. This type of crosstalk is minimized by using VDD = +5V. However, great care should be taken to ensure that the +5V used to power the AD7545 is free from digitally induced noise. operational amplifiers which are good candidates for many applications. The main selection criteria for these operational amplifiers is to have low V OS , low VOS drift, low bias current and low settling time. These amplifiers need to maintain the low nonlinearity and monotonic operation of the D/A while providing enough speed for maximum converter performance. Operational Amplifiers HA-5127 HA-5137 HA-5147 HA-5170 Ultra Low Noise, Precision Ultra Low Noise, Precision, Wide Band Ultra Low Noise, Precision, High Slew Rate Precision, JFET Input TABLE 1. RECOMMENDED TRIM RESISTOR VALUES vs GRADES FOR VDD = +5V TRIM RESISTOR R1 R2 J 500Ω 150Ω K 200Ω 68Ω Temperature Coefficients The gain temperature coefficient of the AD7545 has a maximum value of 5ppm/oC and a typical value of 2ppm/oC. This corresponds to worst case gain shifts of 2 LSBs and 0.8 LSBs respectively over a 100oC temperature range. When trim resistors R1 and R2 are used to adjust full scale range, the temperature coefficient of R1 and R2 should also be taken into account. TABLE 2. UNIPOLAR BINARY CODE TABLE FOR CIRCUIT OF FIGURE 5 BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT  4095  -----------IN  4096    Basic Applications Figures 5 and 6 show simple unipolar and bipolar circuits using the AD7545. Resistor R1 is used to trim for full scale. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when using high speed op amps. Note that the circuits of Figures 5 and 6 have constant input impedance at the VREF terminal. The circuit of Figure 5 can either be used as a fixed reference D/A converter so that it provides an analog output voltage in the range 0V to -VIN (note the inversion introduced by the op amp) or VIN can be an AC signal in which case the circuit behaves as an attenuator (2-Quadrant Multiplier). VIN can be any voltage in the range -20V ≤ VIN ≤ +20V (provided the op amp can handle such voltages) since VREF is permitted to exceed VDD . Table 2 shows the code relationship for the circuit of Figure 5. Figure 6 and Table 3 illustrate the recommended circuit and code relationship for bipolar operation. The D/A function itself uses offset binary code and inverter U1 on the MSB line converts 2’s complement input code to offset binary code. If appropriate, inversion of the MSB may be done in software using an exclusive -OR instruction and the inverter omitted. R3, R4 and R5 must be selected to match within 0.01% and they should be the same type of resistor (preferably wire-wound or metal foil), so that their temperature coefficients match. Mismatch of R3 value to R4 causes both offset and full scale error. Mismatch of R5 to R4 and R3 causes full scale error. The choice of the operational amplifiers in Figure 5 and Figure 6 depends on the application and the trade off between required precision and speed. Below is a list of 1111 1111 1111 –V  2048  1 – V IN  ------------  = – -- VIN 2 4096   1 – V IN  ------------   4096  0V 1000 0000 0000 0000 0000 0001 0000 0000 0000 TABLE 3. 2’S COMPLEMENT CODE TABLE FOR CIRCUIT OF FIGURE 6 DATA INPUT ANALOG OUTPUT  2047  • -----------IN  2048    0111 1111 1111 +V 0000 0000 0001 1 +V IN •  ------------   2048  0V 1 • -----------IN  2048    0000 0000 0000 1111 1111 1111 –V 1000 0000 0000  2048  – V IN •  ------------   2048  5 AD7545 VDD R2 (NOTE) 18 VIN 19 VREF R1 (NOTE) WR 17 16 CS VDD 20 RFB AD7545 OUT 1 AGND DGND 3 2 1 C1 33pF + VOUT ANALOG COMMON DB11 - DB0 (PINS 4 - 15) NOTE: REFER TO TABLE 1 FIGURE 5. UNIPOLAR BINARY OPERATION VDD R2 (NOTE) R4 20K C1 33pF 18 VIN 19 VREF R1 (NOTE) WR 17 16 CS U1 (SEE TEXT) DB11 4 VDD 20 RFB AD7545 DB10 - DB0 3 DGND 11 12 OUT 1 AGND 2 1 R3 10K A1 R6 5K R5 20K A2 + VOUT ANALOG COMMON NOTE: FOR VALUES OF R1 AND R2 SEE TABLE 1 DATA INPUT FIGURE 6. BIPOLAR OPERATION (2’S COMPLEMENT CODE) 6 AD7545 Die Characteristics DIE DIMENSIONS 121 mils x 123 mils (3073 µm x 3124µm) METALLIZATION Type: Pure Aluminum Thickness: 10 ±1kÅ PASSIVATION Type: PSG/Nitride PSG: 7 ±1.4kÅ Nitride: 8 ±1.2kÅ PROCESS CMOS Metal Gate Metallization Mask Layout AD7545 PIN 4 DB11 (MSB) PIN 7 DB8 PIN 6 DB9 PIN 5 DB10 PIN 3 DGND PIN 2 AGND PIN 1 OUT1 PIN 8 DB7 PIN 9 DB6 PIN 10 DB5 PIN 11 DB4 PIN 20 RFEEDBACK PIN 19 VREF PIN 12 DB3 PIN 13 DB2 PIN 18 VDD PIN 14 DB1 PIN 15 DB0 (LSB) PIN 16 CS PIN 17 WR 7 AD7545 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E20.3 (JEDEC MS-001-AD ISSUE D) 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL MIN 0.015 0.115 0.014 0.045 0.008 0.980 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 1.060 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.55 0.204 24.89 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 26.9 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 -B-AD BASE PLANE -CSEATING PLANE D1 B1 B D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E E1 eA eC C e 0.010 (0.25) M C A B S eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e eA eB L N 0.100 BSC 0.300 BSC 0.115 20 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 20 2.93 All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 8