CA3054_05

CA3054 Data Sheet September 22, 2005 FN388.6 Dual Independent Differential Amp for Low Power Applications from DC to 120MHz The CA3054 consists of two independent differential amplifiers with associated constant current transistors on a common monolithic substrate. The six NPN transistors which comprise the amplifiers are general purpose devices which exhibit low 1/f noise and a value of fT in excess of 300MHz. These feature make the CA3054 useful from DC to 120MHz. Bias and load resistors have been omitted to provide maximum application flexibility. The monolithic construction of the CA3054 provides close electrical and thermal matching of the amplifiers. This feature makes these devices particularly useful in dual channel applications where matched performance of the two channels is required. Features • Two Differential Amplifiers on a Common Substrate • Independently Accessible Inputs and Outputs • Maximum Input Offset Voltage . . . . . . . . . . . . . . . . . ±5mV • Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Dual Sense Amplifiers • Dual Schmitt Triggers • Multifunction Combinations - RF/Mixer/Oscillator; Converter/IF • IF Amplifiers (Differential and/or Cascode) • Product Detectors • Doubly Balanced Modulators and Demodulators Ordering Information PART NUMBER (BRAND) CA3054M96 (3054) CA3054MZ (CA3054MZ) CA3054MZ96 (CA3054MZ) TEMP. RANGE (°C) 0 to 85 0 to 85 0 to 85 PACKAGE 14 Ld SOIC Tape and Reel 14 Ld SOIC (Pb-free) PKG. DWG. # M14.15 M14.15 • Balanced Quadrature Detectors • Cascade Limiters • Synchronous Detectors • Pairs of Balanced Mixers • Synthesizer Mixers • Balanced (Push-Pull) Cascode Amplifiers 14 Ld SOIC Tape M14.15 and Reel (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout CA3054 (SOIC) TOP VIEW 1 2 3 4 SUBSTRATE 5 6 7 Q3 Q4 Q5 Q6 Q2 Q1 14 13 12 11 10 NC 9 8 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Harri Corporation 1998. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA3054 Absolute Maximum Ratings TA = 25°C Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . 20V Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . . . 20V Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Maximum Voltage Ratings The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the terminals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V. (NOTE 4) TERM NO. 13 13 14 1 2 3 4 6 7 8 9 11 12 5 Maximum Current Ratings (NOTE 4) TERM IIN NO. mA 13 14 1 2 3 4 6 7 8 9 11 12 5 50 50 5 5 0.1 5 50 50 5 5 0.1 IOUT mA 0.1 0.1 0.1 0.1 0.1 50 0.1 0.1 0.1 0.1 0.1 50 14 0, -20 1 Note 3 2 +5, -5 3 4 6 7 8 9 11 12 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 -1, -5 5 Note 3 +20, 0 +20, 0 Note 3 Note 3 Note 3 +20, 0 +20, 0 Note 3 Note 3 Ref. Substrate Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3 +20, 0 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3 +1, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 0, -20 Note 3 +5, -5 Note 3 Note 3 Note 3 +20, 0 Note 3 Note 3 +15, -5 Note 3 Note 3 +15, -5 Note 3 NOTES: 3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe if the specified limits between all other terminals are not exceeded. 4. Terminal No. 10 of CA3054 is not used. Electrical Specifications TA = 25°C PARAMETER DC CHARACTERISTICS SYMBOL TEST CONDITIONS MIN TYP MAX UNIT For Each Differential Amplifier VIO IIO II I C(Q1) I C(Q5) ----------------- or ----------------I C(Q2) I C(Q6) ∆ V IO ---------------∆T VCB = 3V, IE(Q3) = IE(Q4) = 2mA VCB = 3V, IE(Q3) = IE(Q4) = 2mA VCB = 3V, IE(Q3) = IE(Q4) = 2mA VCB = 3V, IE(Q3) = IE(Q4) = 2mA 0.45 0.3 10 0.98 to 1.02 1.1 5 2 24 mV µA µA - Input Offset Voltage (Figure 8) Input Offset Current (Figure 9) Input Bias Current (Figure 5) Quiescent Operating Current Ratio (Figure 5) Temperature Coefficient Magnitude of Input Offset Voltage (Figure 7) VCB = 3V, IE(Q3) = IE(Q4) = 2mA - - µV/°C 2 CA3054 Electrical Specifications TA = 25°C (Continued) PARAMETER FOR EACH TRANSISTOR DC Forward Base-to-Emitter Voltage (Figure 8) VBE VCB = 3V IC = 5 0 µ A IC = 1mA IC = 3mA IC = 10mA Temperature Coefficient of Base-to-Emitter Voltage (Figure 6) Collector Cutoff Current (Figure 4) Collector-to-Emitter Breakdown Voltage Collector-to-Base Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage DYNAMIC CHARACTERISTICS Common Mode Rejection Ratio for each Amplifier (Figures 1, 10) AGC Range, One Stage (Figures 2, 11) Voltage Gain, Single Stage Double-Ended Output (Figures 2, 11) AGC Range, Two Stage (Figures 3, 12) Voltage Gain, Two Stage Double-Ended Output (Figures 3, 12) Low Frequency, Small Signal Equivalent Circuit Characteristics (For Single Transistor) Forward Current Transfer Ratio (Figure 13) Short Circuit Input Impedance (Figure 13) Open Circuit Output Impedance (Figure 13) Open Circuit Reverse Voltage Transfer Ratio (Figure 13) 1/f Noise Figure for Single Transistor Gain Bandwidth Product for Single Transistor (Figure 14) Admittance Characteristics; Differential Circuit Configuration (For Each Amplifier) Forward Transfer Admittance (Figure 15) Input Admittance (Figure 16) Output Admittance (Figure 17) Reverse Transfer Admittance (Figure 18) Y21 Y11 Y22 Y12 VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA -20 + j0 0.22 + j0.1 0.01 + j0 -0.003 + j0 mS mS mS mS hFE hIE hOE hRE NF fT f = 1kHz, VCE = 3V, IC = 1mA f = 1kHz, VCE = 3V, IC = 1mA f = 1kHz, VCE = 3V, IC = 1mA f = 1kHz, VCE = 3V, IC = 1mA f = 1kHz, VCE = 3V VCE = 3V, IC = 3mA 110 3.5 15.6 1.8 x 10-4 3.25 550 kΩ µS dB MHz CMRR AGC A AGC A VCC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz VCC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz VCC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz VCC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz VCC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz 100 75 32 105 60 dB dB dB dB dB ∆ V BE --------------∆T ICBO V(BR)CEO V(BR)CBO V(BR)CIO V(BR)EBO VCB = 3V, IC = 1mA 0.630 0.715 0.750 0.800 -1.9 0.700 0.800 0.850 0.900 V V V V µV/°C SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCB = 10V, IE = 0 IC = 1mA, IB = 0 IC = 10µA, IE = 0 IC = 10µA, ICI = 0 IE = 10µA, IC = 0 15 20 20 5 0.002 24 60 60 7 100 - nA V V V V 3 CA3054 Electrical Specifications TA = 25°C (Continued) PARAMETER Admittance Characteristics; Cascode Circuit Configuration (For Each Amplifier) Forward Transfer Admittance (Figure 19) Input Admittance (Figure 20) Output Admittance (Figure 21) Reverse Transfer Admittance (Figure 22) Noise Figure Y21 Y11 Y22 Y12 NF VCB = 3V, f = 1MHz Total Stage IC ≈ 2.5 mA VCB = 3V, f = 1MHz Total Stage IC ≈ 2.5 mA VCB = 3V, f = 1MHz Total Stage IC ≈ 2.5 mA VCB = 3V, f = 1MHz Total Stage IC ≈ 2.5 mA f = 100MHz 68 - j0 0.55 + j0 0+ j0.02 0.004 j0.005 8 mS mS mS µS dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Test Circuits VX VCC = +12V VX VCC = +12V 1kΩ VIN = 0.3VRMS 10µF 9 ICUT SIGNAL SOURCE 6 0.5kΩ 0.5kΩ 8 12 1kΩ 11 7 0.1µF VIN = 10mVRMS 10µF 9 VOUT SIGNAL SOURCE 1kΩ 11 1kΩ 7 ICUT 6 1kΩ 0.5kΩ 8 12 1kΩ 0.1µF VOUT 0.1µF VEE = -6V VCC = +12V 0.1µF VEE = -6V VCC = +12V FIGURE 1. COMMON MODE REJECTION RATIO TEST SETUP FIGURE 2. SINGLE STAGE VOLTAGE GAIN TEST SETUP 1 µF 1kΩ VIN = 1mVRMS 10µF 9 SIGNAL SOURCE 1kΩ 1kΩ 6 3 11 8 VX 1kΩ 1 µF 13 ICUT 2 7 1 VCC = +12V 1kΩ 1kΩ 0.5kΩ 0.1µF 4 VOUT 12 14 1kΩ 1kΩ VCC = +12V 0.5kΩ 0.1µF VEE = -6V FIGURE 3. TWO STAGE VOLTAGE GAIN TEST SETUP 4 CA3054 Typical Performance Curves 102 COLLECTOR CUTOFF CURRENT (nA) IE = 0 10 1 10-1 10-2 10-3 10-4 0 25 50 75 100 TEMPERATURE (°C) (NOTE) 125 VCB = 15V VCB = 10V VCB = 5V INPUT BIAS CURRENT (µA) 100 VCB = 3V TA = 25°C 10.0 1.0 0.1 1.0 COLLECTOR CURRENT (mA) 10 NOTE: For CA3054 use data from 0°C to 85°C only. FIGURE 4. COLLECTOR-TO-BASE CUTOFF CURRENT vs TEMPERATURE FOR EACH TRANSISTOR FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT FOR EACH TRANSISTOR BASE-TO-EMITTER VOLTAGE (V) VCB = 3V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -75 IE = 3mA IE = 1mA IE = 0.5mA OFFSET VOLTAGE (mV) 5 VCB = 3V 4 3 2 0.75 0.50 0.25 0 -75 IE = 0.1mA IE = 1mA IE = 10mA -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) (NOTE) TEMPERATURE (°C) (NOTE) NOTE: For CA3054 use data from 0°C to 85°C only. FIGURE 6. BASE-TO-EMITTER VOLTAGE FOR EACH TRANSISTOR vs TEMPERATURE NOTE: For CA3054 use data from 0°C to 85°C only. FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR DIFFERENTIAL PAIRS 0.8 BASE-TO-EMITTER VOLTAGE (V) INPUT OFFSET VOLTAGE Q1 AND Q2 (mV) VCB = 3V TA = 25°C 4 INPUT OFFSET CURRENT (µA) 10 VCB = 3V TA = 25°C 0.7 VBE 0.6 3 1.0 2 0.1 0.5 VIO = |VBE1 - VBE2| 0.4 0.01 1 0 0.1 1.0 EMITTER CURRENT (mA) 10 0.01 0.01 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs EMITTER CURRENT FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED DIFFERENTIAL PAIRS vs COLLECTOR CURRENT 5 CA3054 Typical Performance Curves COMMON MODE REJECTION RATIO (dB) VCC = 12V 110 VEE = -6V f = 1kHz SINGLE STAGE VOLTAGE GAIN (dB) 75 50 25 0 -25 -50 0 -1 -2 -3 BIAS VOLTAGE ON TERMINAL 11 (V) -4 0 -1 -2 -3 -4 -5 -6 -7 BIAS VOLTAGE ON TERMINAL 11 (V) (Continued) 100 VCC = 12V VEE = -6V f = 1kHz SIGNAL INPUT = 10mVRMS 100 90 80 FIGURE 10. COMMON MODE REJECTION RATIO CHARACTERISTIC 100 TWO STAGE VOLTAGE GAIN (dB) VCC = 12V VEE = -6V f = 1kHz SIGNAL INPUT = 1mVRMS FIGURE 11. SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC 100 NORMALIZED h PARAMETERS VCB = 3V f = 1kHz TA = 25°C hIE 10 hRE hFE = 110 hIE = 3.5kΩ hRE = 1.88 x 10-4 hOE = 15.6µS hOE 75 AT 1mA 50 25 0 1.0 hFE -25 hRE 0.1 0.01 hIE 0.1 1.0 COLLECTOR CURRENT (mA) 10 -50 0 -1 -2 -3 -4 -5 -6 BIAS VOLTAGE ON TERMINALS 3 AND 11 (V) -7 FIGURE 12. TWO STAGE VOLTAGE GAIN CHARACTERISTIC FIGURE 13. FORWARD CURRENT TRANSFER RATIO (hFE), SHORT CIRCUIT INPUT IMPEDANCE (hIE), OPEN CIRCUIT OUTPUT IMPEDANCE (hOE), AND OPEN CIRCUIT REVERSE VOLTAGE TRANSFER RATIO (hRE) vs COLLECTOR CURRENT FOR EACH TRANSISTOR 30 FORWARD TRANSFER SUSCEPTANCE OR CONDUCTANCE (mS) DIFFERENTIAL CONFIGURATION IC (EACH TRANSISTOR) ≅ 1.25mA VCB = 3V TA = 25°C GAIN BANDWIDTH PRODUCT (MHz) 1000 900 800 700 600 500 400 300 200 100 0 VCB = 3V TA = 25°C 20 10 b21 0 -10 g21 -20 0.1 1.0 10 FREQUENCY (MHz) 100 1 2 3 4 5 6 7 8 9 10 11 COLLECTOR CURRENT (mA) 12 13 14 FIGURE 14. GAIN BANDWIDTH PRODUCT (fT) vs COLLECTOR CURRENT FIGURE 15. FORWARD TRANSFER ADMITTANCE (Y21) vs FREQUENCY 6 CA3054 Typical Performance Curves 5 INPUT SUSCEPTANCE OR CONDUCTANCE (mS) DIFFERENTIAL CONFIGURATION IC (EACH TRANSISTOR) ≅ 1.25mA OUTPUT CONDUCTANCE (mS) VCB = 3V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0.1 1 10 FREQUENCY (MHz) 100 0.1 1 10 FREQUENCY (MHz) 1 (Continued) 3 DIFFERENTIAL CONFIGURATION IC (EACH TRANSISTOR) ≅ 1.25mA VCB = 3V TA = 25°C 2 OUTPUT SUSCEPTANCE (mS) OUTPUT SUSCEPTANCE (mS) 4 3 2 b11 g11 b22 g22 1 0 0 100 FIGURE 16. INPUT ADMITTANCE (Y11) FIGURE 17. OUTPUT ADMITTANCE (Y22) vs FREQUENCY REVERSE TRANSFER CONDUCTANCE (mS) 1 DIFFERENTIAL CONFIGURATION VCB = 3V IC (EACH TRANSISTOR) ≅ 1.25mA TA = 25°C b12 REVERSE TRANSFER SUSCEPTANCE (µS) 10 FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (mS) 1000 80 60 40 20 0 -20 -40 0.1 1 10 FREQUENCY (MHz) 100 200 b21 CASCODE CONFIGURATION IC (STAGE) ≅ 2.5mA VCB = 3V TA = 25°C g21 100 0.1 g12 -g12 10 0.01 1 0.001 0.1 0.0001 0.1 1 10 FREQUENCY (MHz) 100 0.01 1000 FIGURE 18. REVERSE TRANSFER ADMITTANCE (Y12) vs FREQUENCY FIGURE 19. FORWARD TRANSFER ADMITTANCE (Y21) vs FREQUENCY OUTPUT CONDUCTANCE (mS x 10-4) 6 INPUT CONDUCTANCE OR SUSCEPTANCE (mS) 5 4 3 2 1 0 0.1 CASCODE CONFIGURATION IC (STAGE) ≅ 2.5mA VCB = 3V TA = 25°C g22 0 2 -2 -4 -6 -8 -10 -12 0.1 1 10 FREQUENCY (MHz) 100 b22 0 CASCODE CONFIGURATION IC (STAGE) ≅ 2.5mA VCB = 3V TA = 25°C 1 g11 b11 1 10 FREQUENCY (MHz) 100 200 FIGURE 20. INPUT ADMITTANCE (Y11) vs FREQUENCY FIGURE 21. OUTPUT ADMITTANCE (Y22) vs FREQUENCY 7 CA3054 Typical Performance Curves REVERSE TRANSFER CONDUCTANCE OR SUSCEPTANCE (µS) 100 CASCODE CONFIGURATION IC (STAGE) ≅ 2.5mA 10 VCB = 3V TA = 25°C g12 (Continued) 1 0.1 -b12 0.01 0.001 0.1 1 10 FREQUENCY (MHz) 100 200 FIGURE 22. REVERSE TRANSFER ADMITTANCE (Y12) vs FREQUENCY All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8