CA3078AM

® IC DUCT UCT E P RO SOLET ITUTE PROD , CA3160 OB SUBST 0A, CA3140 Sheet SIBLE POSData 612, CA542 ICL7 L7611, CA3078, CA3078A May 2001 FN535.6 2MHz, Micropower Operational Amplifier The CA3078 and CA3078A are high gain monolithic operational amplifiers which can deliver milliamperes of current yet only consume microwatts of standby power. Their operating points are externally adjustable and frequency compensation may be accomplished with one external capacitor. The CA3078 and CA3078A provide the designer with the opportunity to tailor the frequency response and improve the slew rate without sacrificing power. Operation with a single 1.5V battery is a practical reality with these devices. The CA3078A is a premium device having a supply voltage range of V± = 0.75V to V± = 15V. The CA3078 has the same lower supply voltage limit but the upper limit is V+ = +6V and V- = -6V. Features • Low Standby Power . . . . . . . . . . . . . . . As Low As 700nW • Wide Supply Voltage Range . . . . . . . . . . ±0.75V to ±15V • High Peak Output Current . . . . . . . . . . . . . . . 6.5mA (Min) • Adjustable Quiescent Current • Output Short Circuit Protection Applications • Portable Electronics • Telemetry • Medical Electronics • Intrusion Alarms • Instrumentation Pinouts CA3078 (PDIP, SOIC) TOP VIEW Part Number Information PART NUMBER TEMP. (BRAND) RANGE (oC) CA3078AE CA3078AM (3078A) CA3078AM96 (3078A) CA3078AT CA3078E CA3078M (3078) CA3078T -55 to 125 -55 to 125 -55 to 125 -55 to 125 0 to 70 0 to 70 0 to 70 PACKAGE 8 Ld PDIP 8 Ld SOIC PKG. NO. E8.3 M8.15 COMP 1 INV. INPUT 2 NON-INV. 3 INPUT V- 4 + 8 COMP - 7 V+ 6 OUTPUT 5 BIAS 8 Ld SOIC Tape and Reel M8.15 8 Pin Metal Can 8 Ld PDIP 8 Ld SOIC 8 Pin Metal Can T8.C E8.3 M8.15 T8.C CA3078 (METAL CAN) TOP VIEW COMP TAB 8 1 INV. 2 INPUT NON-INV. 3 INPUT + 5 4 V7 V+ 6 OUTPUT RSET V+ BIAS NOTE: Case Voltage = Floating Schematic Diagram 7 D2 D3 D5 Q10 Q6 Q4 NONINVERTING 3 Q1 Q3 INVERTING 2 BIAS 5 Q2 D1 D4 1 D9 D8 Q8 D6 Q5 D7 Q9 Q14 50Ω V4 Q7 Q11 Q13 Q15 Q17 Q16 OUTPUT 6 Q12 50Ω V+ Q18 COMPENSATION 8 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA3078, CA3078A Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminal) CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . No Limitation Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A Metal Can Package . . . . . . . . . . . . . . . 175 100 Maximum Junction Temperature (Metal Can Package) . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications For Equipment Design CA3078 LIMITS CA3078A LIMITS RSET = 5.1MΩ TA = 0oC to 70oC MAX 4.5 32 170 130 1560 MIN 86 ±5 -5 to +5 6.5 MAX 5 40 200 150 1800 30 MIN 92 ±5.1 80 76 76 TA = 25oC TYP 0.70 0.50 7 100 20 240 ±5.3 -5.5 to +5.8 115 12 105 105 MAX 3.5 2.5 12 25 300 TA = -55oC to 125oC MIN 90 ±5 -5 to +5 6.5 MAX 4.5 5.0 50 45 540 30 UNITS mV nA nA dB µA µW V V dB mA µV/V µV/V TEST CONDITIONS RSET = 1MΩ TA = 25oC MIN 88 ±5.1 80 76 76 TYP 1.3 6 60 92 100 1200 ±5.3 -5.5 to +5.8 110 12 93 93 PARAMETER VIO IIO IIB AOL IQ PD VOM VICR CMRR IOM+ or IOM∆VIO/∆V+ ∆VIO/∆V- V+ and V±6V RS (kΩ) ≤10 ≤10 ≤10 ≤10 ≤10 RL (kΩ) ≥10 ≥10 - RSET = 13MΩ VIO AOL IQ PD VOM CMRR IIB IIO ±15V ≤10 ≤10 ≥10 ≥10 92 ±13.7 80 1.4 100 20 600 ±14.1 106 7 0.50 3.5 30 750 14 2.7 88 ±13.5 4.5 50 1350 55 5.5 mV dB µA µW V dB nA nA 2 CA3078, CA3078A Electrical Specifications TA = 25oC, Typical Values Intended Only for Design Guidance CA3078 V+ = +1.3V, V- = -1.3V RSET = 2MΩ 1.3 1.7 9 80 10 26 1.4 -0.8 to +1.1 100 12 20 V+ = +0.75V, V- = -0.75V RSET = 10MΩ 1.5 0.5 1.3 60 1 1.5 0.3 -0.2 to +0.5 90 0.5 50 V+ = +1.3V, V- = -1.3V RSET = 2MΩ 0.7 0.3 3.7 84 10 26 1.4 -0.8 to +1.1 100 12 20 CA3078A V+ = +0.75V, V- = -0.75V RSET = 10MΩ 0.9 0.054 0.45 65 1 1.5 0.3 -0.2 to +0.5 90 0.5 50 PARAMETER VIO IIO IIB AOL IQ PD VOP-P VICR CMRR IOM± ∆VIO/∆V± UNITS mV nA nA dB µA µW V V dB mA µV/V Electrical Specifications PARAMETER ∆VIO/∆TA ∆IIO/∆TA GBWP SR TA = 25oC and VSUPPLY = ±6V, Typical Values Intended Only for Design Guidance CA3078 CA3078A RSET = 5.1MΩ 5 6.3 0.3 0.027 0.5 3 7.4 1 40 0.25 RSET = 1MΩ 6 70 2 0.04 1.5 2.5 1.7 0.8 UNITS µV/oC pA/oC MHz V/µs V/µs µs MΩ kΩ nV/√Hz pA/√Hz TEST CONDITIONS RS ≤10kΩ RS ≤10kΩ AV = 100, C1 = 10pF See Figures 23, 24 RSET = 1MΩ 6 70 2 0.04 1.5 tR RI RO eN(10Hz) iN(10Hz) 10% to 90% Rise Time RS = 0 RS = 1MΩ 2.5 0.87 0.8 25 1 3 CA3078, CA3078A Test Circuits V+ 100kΩ V+ 0V 100kΩ VIN R2 C2 3 51kΩ 2 7 V+ 100kΩ V+ 7 0V 6 8 1 4 VR1 OPTIONAL R2 - C2 COMP. R1 C1 R1 OPTIONAL R2 - C2 COMP. 10kΩ CL R2 VOUT 0V VIN C2 3 100kΩ 4 VR1 C1 2 RSET RSET CA3078 CA3078A + 5 CA3078 CA3078A + 1 5 0V 6 8 CL 10kΩ VOUT FIGURE 1. TRANSIENT RESPONSE AND SLEW RATE, UNITY GAIN (INVERTING) TEST CIRCUIT NON-INVERTING V+ INPUT RI 3 7 + CA3078 CA3078A FIGURE 2. SLEW RATE, UNITY GAIN (NON-INVERTING) TEST CIRCUIT INVERTING RF INPUT V+ 7 OUTPUT 6 V+ RI 2 V+ RB 1M V2 CA3078 CA3078A OUTPUT 6 RF 4 1M VV- RB 3 + 4 V- RI Value of RB required to have a null adjustment range of ±7.5mV RI RF V+ RB ≈ (RI + RF) 7.5 x 10-3 assuming RB > > RI RF RI + RF Value of RB required to have a null adjustment range of ±7.5mV RI V+ RB ≈ 7.5 x 10-3 assuming RB > > RI FIGURE 3. OFFSET VOLTAGE NULL CIRCUITS 5.1MΩ 5.1MΩ 10MΩ 7 VP-P 1µF 510kΩ 2 RSET = 30MΩ 5 6 + VP-P 1µF 8 5µF RL 1.5V “AA” CELL + 10MΩ 7 2 510kΩ 1µF 3 10MΩ RSET = 30MΩ 5 6 + 8 5µF RL 1.5V “AA” CELL + CA3078 CA3078A - CA3078 CA3078A + 1 4 7pF - 3 10MΩ + 1 4 7pF FIGURE 4. INVERTING 20dB AMPLIFIER CIRCUIT FIGURE 5. NON-INVERTING 20dB AMPLIFIER CIRCUIT 4 CA3078, CA3078A TABLE 1. UNITY GAIN SLEW RATE vs COMPENSATION - CA3078 AND CA3078A VSUPPLY = ±6V, Output Voltage (VO) = ±5V, Load Resistance (RL) = 10kΩ, Transient Response: 10% overshoot for an output voltage of 100mV, Ambient Temperature (TA) = 25oC UNITY GAIN (INVERTING) FIGURE 1 COMPENSATION TECHNIQUE CA3078 - IQ = 100µA Single Capacitor Resistor and Capacitor Input CA3078A - IQ = 20µA Single Capacitor Resistor and Capacitor Input 0 14 300 100 0 0 3.5 750 350 0 R1 kΩ C1 pF R2 kΩ C2 µF SLEW RATE V/µs R1 kΩ UNITY GAIN (NON-INVERTING) FIGURE 2 C1 pF R2 kΩ C2 µF SLEW RATE V/µs ∞ ∞ 0.25 0 0 0.306 0.0085 0.04 0.67 0 5.3 1500 500 0 ∞ ∞ 0.311 0 0 0.45 0.0095 0.024 0.67 ∞ ∞ ∞ ∞ 0.644 0 0 0.156 0.0095 0.027 0.29 0 34 800 125 0 ∞ ∞ 0.77 0 0 0.4 0.003 0.02 0.4 ∞ ∞ Application Information Compensation Techniques The CA3078A and CA3078 can be phase compensated with one or two external components depending upon the closed loop gain, power consumption, and speed desired. The recommended compensation is a resistor in series with a capacitor connected from Terminal 1 to Terminal 8. Values of the resistor and capacitor required for compensation as a function of closed loop gain are shown in Figures 25 and 26. These curves represent the compensation necessary at quiescent currents of 100µA and 20µA, respectively, for a transient response with 10% overshoot. Figures 23 and 24 show the slew rates that can be obtained with the two different compensation techniques. Higher speeds can be achieved with input compensation, but this increases noise output. Compensation can also be accomplished with a single capacitor connected from Terminal 1 to Terminal 8, with speed being sacrificed for simplicity. Table 1 gives an indication of slew rates that can be obtained with various compensation techniques at quiescent currents of 100µA and 20µA. Single Supply Operation The CA3078A and CA3078 can operate from a single supply with a minimum total supply voltage of 1.5V. Figures 4 and 5 show the CA3078A or CA3078 in inverting and non-inverting 20dB amplifier configurations utilizing a 1.5V type “AA” cell for a supply. The total consumption for either circuit is approximately 675nW. The output voltage swing in this configuration is 300mVP-P with a 20kΩ load. Typical Performance Curves V S = ±6 TA = 25oC RS ≤ 10kΩ INPUT OFFSET VOLTAGE (mV) V S = ±6 TA = 25oC INPUT OFFSET CURRENT (nA) 10 CA3078 1 CA3078A 0.1 3.0 2.4 1.8 1.2 0.6 0 1 10 100 1000 TOTAL QUIESCENT CURRENT (µA) CA3078 CA3078A 0.01 1 100 10 1000 TOTAL QUIESCENT CURRENT (µA) 10000 FIGURE 6. INPUT OFFSET VOLTAGE vs TOTAL QUIESCENT CURRENT FIGURE 7. INPUT OFFSET CURRENT vs TOTAL QUIESCENT CURRENT 5 CA3078, CA3078A Typical Performance Curves V S = ±6 TA = 25oC OPEN LOOP VOLTAGE GAIN (dB) 100 INPUT BIAS CURRENT (nA) (Continued) TA = 25oC CA3078A CA3078 126 RL = 1MΩ 10kΩ 2kΩ 108 90 72 54 36 18 0 1 10 100 TOTAL QUIESCENT CURRENT (µA) 1000 VS = ±6 TO VS = ±15 TA = 25oC 1 1 10 100 1000 TOTAL QUIESCENT CURRENT (µA) V S = ±6 IQ = 100µA C1 = 10pF C1 = 30pF 100 300 1000 0 100 200 300 400 PHASE ANGLE (DEGREES) C1 = 0pF 10 CA3078 CA3078A 126 108 90 72 54 36 18 0 1 0.1 1 10 100 1000 10000 TOTAL QUIESCENT CURRENT (µA) FIGURE 8. INPUT BIAS CURRENT vs TOTAL QUIESCENT CURRENT FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TOTAL QUIESCENT CURRENT 1000 MAXIMUM OUTPUT CURRENT (mA) BIAS SETTING RESISTANCE (MΩ) VS = ±15 100 +6 -6 +3 -3 1 +1 -1 TA = 25oC RSET CONNECTED BETWEEN TERMINAL 5 AND V+ 0.01 1000 100 10 1 0.1 0.01 TOTAL QUIESCENT CURRENT (µA) 0.001 100 10 10 0.1 0.1 FIGURE 10. BIAS SETTING RESISTANCE vs TOTAL QUIESCENT CURRENT VS = ±1.3V 1.5 OUTPUT VOLTAGE SWING (V) TA = 25oC RL = 50kΩ FIGURE 11. MAXIMUM OUTPUT CURRENT vs TOTAL QUIESCENT CURRENT 120 OPEN LOOP VOLTAGE GAIN (dB) 100 80 60 40 20 1.0 10kΩ 5kΩ 2kΩ 1kΩ 500Ω φ 0.5 0 0 0.5 1.0 1.5 2.0 TOTAL QUIESCENT CURRENT (µA) 0 RL = 10kΩ, TA = 25oC C1- BETWEEN TERMINALS 1 AND 8 -20 0.1 1 101 102 103 FREQUENCY (Hz) 104 105 106 FIGURE 12. OUTPUT VOLTAGE SWING vs TOTAL QUIESCENT CURRENT FIGURE 13. OPEN LOOP VOLTAGE GAIN vs FREQUENCY 6 CA3078, CA3078A Typical Performance Curves 100 IQ = 20µA TA = 25oC (Continued) OPEN LOOP VOLTAGE GAIN (dB) 120 100 80 60 V S = ±6 IQ = 20µA C1 = 0pF 0 PHASE ANGLE (DEGREES) INPUT BIAS CURRENT (nA) - CA3078T 10 VICR PEAK OUTPUT VOLTAGE (V), COMMON MODE VOLTAGE RANGE (V) VOM 1 C1 = 10pF C1 = 30pF 100 φ 200 300 400 100 40 300 1000 20 0 RL = 10kΩ TA = 25oC -20 C1- BETWEEN TERMINALS 1 AND 8 0.1 1 101 102 103 104 105 106 0.1 +1 +0.1 -0.1 -0.1 -1 +10 -10 SUPPLY VOLTS (V+, V-) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 V S = ±6 +100 -100 FREQUENCY (Hz) FIGURE 15. OPEN LOOP VOLTAGE GAIN vs FREQUENCY INPUT OFFSET VOLTAGE (mV) CA3078 IQ = 100µA -1 -VICR -VOM CA3078A IQ = 20µA -10 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 14. OUTPUT AND COMMON MODE VOLTAGE vs SUPPLY VOLTAGE FIGURE 16. INPUT OFFSET VOLTAGE vs TEMPERATURE INPUT OFFSET CURRENT (nA) - CA3078AT INPUT OFFSET CURRENT (nA) - CA3078T V S = ±6 V S = ±6 INPUT BIAS CURRENT (nA) - CA3078AT 15.0 12.5 10.0 7.5 5.0 2.5 0 -75 CA3078 IQ = 100µA CA3078A IQ = 20µA 100 75 50 25 0 125 2.5 2.0 1.5 1.0 0.5 0 -75 CA3078A IQ = 20µA CA3078 IQ = 100µA 10 8 6 4 2 0 125 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 FIGURE 17. INPUT OFFSET CURRENT vs TEMPERATURE FIGURE 18. INPUT BIAS CURRENT vs TEMPERATURE 7 CA3078, CA3078A Typical Performance Curves V S = ±6 110 OPEN LOOP VOLTAGE GAIN (dB) 105 100 95 90 85 80 -75 CA3078A IQ = 20µA CA3078 IQ = 100µA (Continued) TOTAL QUIESCENT CURRENT (µA) - CA3078AT TOTAL QUIESCENT CURRENT (µA) - CA3078T 105 V S = ±6 50 40 30 CA3078 20 10 0 -75 CA3078A 200 150 100 50 0 125 -50 -25 0 25 50 75 100 125 -50 -25 TEMPERATURE (oC) 0 25 50 TEMPERATURE (oC) 75 100 FIGURE 19. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE FIGURE 20. TOTAL QUIESCENT CURRENT vs TEMPERATURE EQUIVALENT INPUT NOISE CURRENT (pA/√Hz) EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) 100 V S = ±6 TA = 25oC CA3078AT 1 IQ = 20µA V S = ±6 TA = 25oC CA3078AT IQ = 100µA 0.1 IQ = 20µA IQ = 100µA 10 0 101 102 103 FREQUENCY (Hz) 104 105 0.01 101 102 103 FREQUENCY (Hz) 104 FIGURE 21. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY FIGURE 22. EQUIVALENT INPUT NOISE CURRENT vs FREQUENCY 8 CA3078, CA3078A Typical Performance Curves 1.5 RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN 1.25 TERMINALS 1 AND 8) 1 0.75 0.5 0.25 0 CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) (Continued) 0.6 SLEW RATE (V/µs) 0.5 0.4 0.3 0.2 0.1 0 SLEW RATE (V/µs) RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 90 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 90 Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 100µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 10V R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2.5 x 10-6) FIGURE 23. SLEW RATE vs CLOSED LOOP GAIN FOR IQ = 100mA - CA3078 Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 20µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 10V R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2 x 10-6) FIGURE 24. SLEW RATE vs CLOSED LOOP GAIN FOR IQ = 20mA - CA3078A PHASE COMPENSATION CAPACITOR (pF) 1000 CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) PHASE COMPENSATION CAPACITOR (pF) 1000 CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) 100 100 10 10 1 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 90 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 1 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 90 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 100µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 100mV R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2.5 x 10-6) FIGURE 25. PHASE COMPENSATION CAPACITANCE vs CLOSED LOOP GAIN - CA3078 Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 20µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 100mV R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2 x 10-6) FIGURE 26. PHASE COMPENSATION CAPACITANCE vs CLOSED LOOP GAIN - CA3078A 9 CA3078, CA3078A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 10 CA3078, CA3078A Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L SEATING PLANE -AD -CA h x 45o MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 A1 B C D E α µ A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 11. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 12. Dimensioning and tolerancing per ANSI Y14.5M-1982. 13. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 14. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 15. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 16. “L” is the length of terminal for soldering to a substrate. 17. “N” is the number of terminal positions. 18. Terminal numbers are shown for reference only. 19. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 20. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 11 CA3078, CA3078A Metal Can Packages (Can) REFERENCE PLANE A L L2 L1 A A ØD ØD1 Øe 2 1 Øb1 F Q Øb BASE AND SEATING PLANE BASE METAL LEAD FINISH β N k1 ØD2 T8.C MIL-STD-1835 MACY1-X8 (A1) e1 8 LEAD METAL CAN PACKAGE INCHES SYMBOL A Øb Øb1 Øb2 ØD MIN 0.165 0.016 0.016 0.016 0.335 0.305 0.110 MAX 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS MIN 4.19 0.41 0.41 0.41 8.51 7.75 2.79 MAX 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES 1 1 2 1 1 1 3 3 4 Rev. 0 5/18/94 α k ØD1 C L ØD2 e e1 F k k1 0.200 BSC 0.100 BSC 0.027 0.027 0.500 0.250 0.010 45o BSC 45o BSC 8 0.040 0.034 0.045 0.750 0.050 0.045 - 5.08 BSC 2.54 BSC 1.02 0.86 1.14 19.05 1.27 1.14 0.69 0.69 12.70 6.35 0.25 Øb1 Øb2 L L1 SECTION A-A L2 Q NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. α β N 45o BSC 45o BSC 8 12