CA3081

CT RODU DUCT LETE P TITUTE PRO at B SO O BS en ter L E SU port C POSSIB chnical Sup rsil.com/tsc Data Sheet FO R A ou r Te ww.inte t contac TERSIL or w N 1-888-I ® CA3081, CA3082 May 2001 File Number 480.6 General Purpose High Current NPN Transistor Arrays CA3081 and CA3082 consist of seven high current (to 100mA) silicon NPN transistors on a common monolithic substrate. The CA3081 is connected in a common emitter configuration and the CA3082 is connected in a common collector configuration. The CA3081 and CA3082 are capable of directly driving seven segment displays, and light emitting diode (LED) displays. These types are also well suited for a variety of other drive applications, including relay control and thyristor firing. Features • CA3081 - Common Emitter Array • CA3082 - Common Collector Array • Directly Drive Seven Segment Incandescent Displays and Light Emitting Diode (LED) Display • 7 Transistors Permit a Wide Range of Applications in Either a Common Emitter (CA3081) or Common Collector (CA3082) Configuration • High IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Max) • Low VCESAT (at 50mA) . . . . . . . . . . . . . . . . . . 0.4V (Typ) Part Number Information PART NUMBER (BRAND) CA3081 CA3081F CA3081M (3081) CA3082 CA3082M (3082) CA3082M96 (3082) TEMP. RANGE ( oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld CERDIP 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel PKG. NO. E16.3 F16.3 M16.15 E16.3 M16.15 M16.15 Applications • Drivers for - Incandescent Display Devices - LED Displays • Relay Control • Thyristor Firing Pinouts CA3081 COMMON EMITTER CONFIGURATION (PDIP, CERDIP, SOIC) TOP VIEW 1 2 3 4 SUBSTRATE 5 6 7 8 16 15 14 13 12 11 10 9 CA3082 COMMON COLLECTOR CONFIGURATION (PDIP, SOIC) TOP VIEW 1 2 3 4 SUBSTRATE 5 6 7 8 16 15 14 13 12 11 10 9 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved CA3081, CA3082 Absolute Maximum Ratings TA = 25oC Collector-to-Emitter Voltage (V CEO) . . . . . . . . . . . . . . . . . . . . . .16V Collector-to-Base Voltage (VCBO) . . . . . . . . . . . . . . . . . . . . . . . 20V Collector-to-Substrate Voltage (V CIO , Note 1) . . . . . . . . . . . . . 20V Emitter-to-Base Voltage (VEBO) . . . . . . . . . . . . . . . . . . . . . . . . . 5V Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Base Current (IB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Information Thermal Resistance (Typical, Note 2) θJA ( oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 115 45 PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 190 N/A Maximum Power Dissipation (Any One Transistor) . . . . . . . 500mW Maximum Junction Temperature (Ceramic Package). . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3081 and CA3082 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors, the substrate terminal (5) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER For Equipment Design at TA = 25oC SYMBOL V(BR)CBO V(BR)CIO V(BR)CEO V(BR)EBO hFE TEST CONDITIONS IC = 500µA, IE = 0 IC = 500µA, IB = 0 IC = 1mA, IB = 0 IC = 500µA VCE = 0.5V, IC = 30mA VCE = 0.8V, IC = 50mA MIN 20 20 16 5.0 30 40 TYP 60 60 24 6.9 68 70 0.87 0.27 0.4 0.4 MAX 1.2 0.5 0.7 0.8 10 1.0 UNITS V V V V V V V V µA µA Collector-to-Base Breakdown Voltage Collector-to-Substrate Breakdown Voltage Collector-to-Emitter Breakdown Voltage Emitter-to-Base Breakdown Voltage DC Forward Current Transfer Ratio Base-to-Emitter Saturation Voltage (Figure 4) Collector-to-Emitter Saturation Voltage CA3081, CA3082 CA3081 (Figure 5) CA3082 (Figure 5) Collector Cutoff Current Collector Cutoff Current VBESAT V CESAT IC = 30mA, IB = 1mA IC = 30mA, IB = 1mA IC = 50mA, IB = 5mA IC = 50mA, IB = 5mA ICEO ICBO VCE = 10V, IB = 0 VCB = 10V, IE = 0 Typical Read - Out Driver Applications VP 0V V+ 1/7 CA3082 (COMMON COLLECTOR) R (NOTE) LIGHT EMITTING DIODE (LED) 40736R V+ 1 SEGMENT OF INCANDESCENT DISPLAY (DR2000 SERIES OR EQUIVALENT) FROM DECODER 1/7 CA3081 (COMMON EMITTER) NOTE: The Resistance for R is determined by the relationship: V P – V BE – VF ( LED ) R = -----------------------------------------------------I ( LED ) R = 0 for V P = V BE + V F ( LED ) Where: VP = Input Pulse Voltage VF = Forward Voltage Drop Across the Diode FIGURE 1. SCHEMATIC DIAGRAM SHOWING ONE TRANSISTOR OF THE CA3081 DRIVING ONE SEGMENT OF AN INCANDESCENT DISPLAY FIGURE 2. SCHEMATIC DIAGRAM SHOWING ONE TRANSISTOR OF THE CA3082 DRIVING A LIGHT EMITTING DIODE (LED) 2 CA3081, CA3082 Typical Performance Curves 100 VCE = 3V BASE-TO-EMITTER SATURATION VOLTAGE (V) 90 DC FORWARD CURRENT TRANSFER RATIO (hFE) 80 70 TA = 0 oC 60 50 40 0.1 TA = 25oC 1.0 TA = 25 oC hFE = 10 0.9 TA = 7 0oC 0.8 0.7 0.6 1 10 COLLECTOR CURRENT (mA) 100 1 10 COLLECTOR CURRENT (mA) 100 FIGURE 3. DC FORWARD CURRENT TRANSFER RATIO vs COLLECTOR CURRENT 1 hFE = 1 0 TA = 25oC COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) 0.8 FIGURE 4. BASE-TO-EMITTER SATURATION VOLTAGE vs COLLECTOR CURRENT 1.2 hFE = 1 0 TA = 70oC COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) 1 0.8 0.6 0.4 0.2 0 0.6 MAXIMUM 0.4 MAXIMUM 0.2 TYPICAL TYPICAL 0 1 10 COLLECTOR CURRENT (mA) 100 1 10 COLLECTOR CURRENT (mA) 100 FIGURE 5. COLLECTOR-TO-EMITTER SATURATION VOLTAGE vs COLLECTOR CURRENT FIGURE 6. COLLECTOR-TO-EMITTER SATURATION VOLTAGE vs COLLECTOR CURRENT 3 CA3081, CA3082 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e 0.010 (0.25) M C A B S eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 4 CA3081, CA3082 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D α µ A1 0.10(0.004) C E e H h L N e B 0.25(0.010) M C AM BS 0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 5 CA3081, CA3082 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 6