CA3094AE

UCT M E NT RO D E TE P EPLAC nter at E S O L DE D R t Ce m/tsc or OB Supp ME N il.co COM chnical w.inters RE e Sheet NO r TData r ww ct ou IL o onta INTERS c 81-88 ® CA3094, CA3094A, CA3094B October 2000 File Number 598.8 30MHz, High Output Current Operational Transconductance Amplifier (OTA) The CA3094 is a differential input power control switch/amplifier with auxiliary circuit features for ease of programmability. For example, an error or unbalance signal can be amplified by the CA3094 to provide an on-off signal or proportional control output signal up to 100mA. This signal is sufficient to directly drive high current thyristors, relays, DC loads, or power transistors. The CA3094 has the generic characteristics of the CA3080 operational amplifier directly coupled to an integral Darlington power transistor capable of sinking or driving currents up to 100mA. The gain of the differential input stage is proportional to the amplifier bias current (IABC), permitting programmable variation of the integrated circuit sensitivity with either digital and/or analog programming signals. For example, at an IABC of 100µA, a 1mV change at the input will change the output from 0 to 100µA (typical). The CA3094 is intended for operation up to 24V and is especially useful for timing circuits, in automotive equipment, and in other applications where operation up to 24V is a primary design requirement (see Figures 28, 29 and 30 in Typical Applications text). The CA3094A and CA3094B are like the CA3094 but are intended for operation up to 36V and 44V, respectively (single or dual supply). Features • CA3094E, M for Operation Up to 24V • CA3094AT, E, M for Operation Up to 36V • CA3094BT, M for Operation Up to 44V • Designed for Single or Dual Power Supply • Programmable: Strobing, Gating, Squelching, AGC Capabilities • Can Deliver 3W (Average) or 10W (Peak) to External Load (in Switching Mode) • High Power, Single Ended Class A Amplifier will Deliver Power Output of 0.6W (1.6W Device Dissipation) • Total Harmonic Distortion (THD) at 0.6W in Class A Operation 1.4% (Typ) Applications • Error Signal Detector: Temperature Control with Thermistor Sensor; Speed Control for Shunt Wound DC Motor • Over Current, Over Voltage, Over Temperature Protectors • Dual Tracking Power Supply with CA3085 • Wide Frequency Range Oscillator • Analog Timer • Level Detector Ordering Information PART NUMBER (BRAND) CA3094AT, BT CA3094E, AE CA3094M, BM TEMP. RANGE ( oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 8 Pin Metal Can 8 Ld PDIP 8 Ld SOIC PKG. NO. T8.C E8.3 M8.15 • Alarm Systems • Voltage Follower • Ramp Voltage Generator • High Power Comparator • Ground Fault Interrupter (GFI) Circuits Pinouts CA3094 (PDIP, SOIC) TOP VIEW EXT. FREQUENCY COMPENSATION OR INHIBIT INPUT DIFFERENTIAL VOLTAGE INPUTS GND (V- IN DUAL SUPPLY OPERATION) 1 2 3 4 8 7 6 5 SINK OUTPUT (COLLECTOR) V+ DRIVE OUTPUT (EMITTER) 2 IABC CURRENT PROGRAMMABLE INPUT (STROBE OR AGC) DIFFERENTIAL VOLTAGE INPUTS 6 CA3094 (METAL CAN) TOP VIEW SINK OUTPUT (COLLECTOR) EXT. FREQUENCY COMPENSATION OR INHIBIT INPUT 8 1 TAB 7 V+ DRIVE OUTPUT (EMITTER) 3 4 5 GND (V- IN DUAL SUPPLY OPERATION) IABC CURRENT PROGRAMMABLE INPUT (STROBE OR AGC) NOTE: Pin 4 is connected to case. 3-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved CA3094, CA3094A, CA3094B Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) CA3094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V CA3094A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V CA3094B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V Differential Input Voltage (Terminals 2 and 3, Note 1). . . . . . . . . 5V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current (Terminals 2 and 3) . . . . . . . . . . . . . . . . . . . . . . ±1mA Amplifier Bias Current (Terminal 5) . . . . . . . . . . . . . . . . . . . . . . 2mA Average Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA Thermal Information Thermal Resistance (Typical, Note 2) θJA ( oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 170 N/A Metal Can Package . . . . . . . . . . . . . . . 175 100 Maximum Junction Temperature (Metal Can Package). . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Exceeding this voltage rating will not damage the device unless the peak input signal current (1mA) is also exceeded. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER INPUT PARAMETERS Input Offset Voltage TA = 25oC for Equipment Design. Single Supply V+ = 30V, Dual Supply VSUPPLY = ±15V, IABC = 100µA Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VIO |∆VIO| IIO TA = 25oC TA = 0oC to 70oC Change in VIO between IABC = 100µA and IABC = 5µA TA = 25oC TA = 0oC to 70oC TA = 25oC TA = 0oC to 70oC 8 70 0.4 1 0.02 0.2 10 110 28.8 0.5 13.8 -14.5 30 4 0.4 1.4 0.68 4 15 18 1.8 1.0 2.6 5.0 7.0 8.0 0.2 0.3 0.50 0.70 12 150 - mV mV mV µA µA µA µA mW dB V V V V MHz kHz % % V µV/oC µ V/V nV/ H z pA/ Hz MΩ pF Input Offset Voltage Change Input Offset Current Input Bias Current II Device Dissipation Common Mode Rejection Ratio Common Mode Input Voltage Range PD CMRR VICR IOUT = 0mA V+ = 30V (High) V- = 0V (Low) V+ = 15V V- = -15V 27 1.0 12 -14 - Unity Gain Bandwidth Open Loop Bandwidth at -3dB Point Total Harmonic Distortion (Class A Operation) Amplifier Bias Voltage (Terminal 5 to Terminal 4) Input Offset Voltage Temperature Coefficient Power Supply Rejection 1/F Noise Voltage 1/F Noise Current Differential Input Resistance Differential Input Capacitance fT BWOL THD IC = 7.5mA, VCE = 15V, IABC = 500µ A IC = 7.5mA, VCE = 15V, IABC = 500µ A PD = 220mW PD = 600mW VABC ∆VIO/∆T ∆VIO/∆V EN IN RI CI f = 10Hz, IABC = 50µA f = 10Hz, IABC = 50µA IABC = 20µA f = 1MHz, V+ = 30V 0.50 - 3-2 CA3094, CA3094A, CA3094B Electrical Specifications PARAMETER TA = 25oC for Equipment Design. Single Supply V+ = 30V, Dual Supply VSUPPLY = ±15V, IABC = 100µA Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OUTPUT PARAMETERS (Differential Input Voltage = 1V) Peak Output Voltage (Terminal 6) Peak Output Voltage (Terminal 6) Peak Output Voltage (Terminal 8) Peak Output Voltage (Terminal 8) With Q13 “ON” With Q13 “OFF” Positive Negative With Q13 “OFF” With Q13 “ON” Positive Negative VOM+ VOMV OM+ VOMVOM+ VOMV OM+ VOMVCE( SAT) V+ = 15V, V- = -15V, RL = 2kΩ to 15V V+ = 30V, IC = 50mA, Terminal 6 Grounded V+ = 30V hFE CO V+ = 30V, V CE = 5V, IC = 50mA f = 1MHz, All Remaining Terminals Tied to Terminal 4 V+ = 30V, RL = 2kΩ to 30V V+ = 15V, V- = -15V, R L = 2kΩ to -15V V+ = 30V, RL = 2kΩ to GND 26 11 29.95 14.95 16,000 27 0.01 12 -14.99 29.99 0.040 14.99 -14.96 0.17 2 100,000 5.5 17 0.05 -14.95 0.80 10 pF pF V V V V V V V V V µA Collector-to-Emitter Saturation Voltage (Terminal 8) Output Leakage Current (Terminal 6 to Terminal 4) Composite Small Signal Current Transfer Ratio (Beta) (Q12 and Q13) Output Capacitance Terminal 6 Terminal 8 TRANSFER PARAMETERS Voltage Gain A V+ = 30V, IABC = 100µA, ∆VOUT = 20V, RL = 2kΩ 20,000 86 1650 100,000 100 2200 500 50 0.70 2750 - V/V dB µS V/µs V/µs V/µs Forward Transconductance to Terminal 1 Slew Rate (Open Loop) Positive Slope Negative Slope gM SR IABC = 500µA, RL = 2kΩ IABC = 500µA, RL = 2kΩ - Unity Gain (Non-Inverting Compensated) Schematic Diagram EXTERNAL FREQUENCY COMPENSATION OR INHIBIT INPUT D3 Q4 Q6 D2 Q5 Q9 DIFFERENTIAL VOLTAGE 2 INPUT DIFFERENTIAL VOLTAGE INPUT AMPLIFIER BIAS INPUT 5 IABC 8 Q1 Q2 Q12 3 Q11 Q10 R2 47kΩ D6 6 “SOURCE” (DRIVE) OUTPUT “SINK” OUTPUT Q13 Q7 D4 Q8 D5 R1 2kΩ 1 7 V+ INPUTS OUTPUT MODE “Source” “Sink” OUTPUT TERM 6 8 INV 2 3 NONINV 3 2 Q3 D1 4 V- 3-3 CA3094, CA3094A, CA3094B Operating Considerations The “Sink” Output (Terminal 8) and the “Drive” Output (Terminal 6) of the CA3094 are not inherently current (or power) limited. Therefore, if a load is connected between Terminal 6 and Terminal 4 (V- or Ground), it is important to connect a current limiting resistor between Terminal 8 and Terminal 7 (V+) to protect transistor Q13 under shorted load conditions. Similarly, if a load is connected between Terminal 8 and Terminal 7 (V+), the current limiting resistor should be connected between Terminal 6 and Terminal 4 or ground. In circuit applications where the emitter of the output transistor is not connected to the most negative potential in the system, it is recommended that a 100Ω current limiting resistor be inserted between Terminal 7 and the V+ supply. 1/F Noise Measurement Circuit When using the CA3094, A, or B audio amplifier circuits, it is frequently necessary to consider the noise performance of the device. Noise measurements are made in the circuit shown in Figure 20. This circuit is a 30dB, non-inverting amplifier with emitter follower output and phase compensation from Terminal 2 to ground. Source resistors (RS) are set to 0Ω or 1MΩ for E noise and I noise measurements, respectively. These measurements are made at frequencies of 10Hz, 100Hz and 1kHz with a 1Hz measurement bandwidth. Typical values for 1/f noise at 10Hz and 50µA IABC are: EN = 18nV ⁄ Hz and IN = 1.8pA ⁄ Hz . Test Circuits 30V NOTES: 7 5 2 CA3094 3 100Ω 100Ω 4 8 300k Ω 9.9kΩ E OUT 3. Input Offset Voltage: VIO = ---------------- . 100 4. For Power Supply Rejection Test: (1) vary V+ by -2V; then (2) vary V- by +2V. 5. Equations: E O UT – E OUT 0 1 (1) V+ Rejection = -----------------------------------------------200 E OUT – E O UT 0 2 (2) V- Rejection = -----------------------------------------------200 6 1 10kΩ 1kΩ 100pF EOUT 1 6. Power Supply Rejection: ( d B ) = 20 log -------------------------------------------- . V REJECTIO N † † Maximum Reading of Step 1 or Step 2 15V 30V FIGURE 1. INPUT OFFSET VOLTAGE AND POWER SUPPLY REJECTION TEST CIRCUIT 30V 7 5 RABC 1MΩ 8 7 30V 2 CA3094 3 1 4 220Ω 0.001µF 15V 150kΩ EOUT 15V 3 6 300kΩ 5 2 CA3094A + 4 1MΩ NOTES: 7. PDISSIPATION = (V+)(I) E OUT 8. I O S = ------------------------------VOLTS 10 6 -------------------AMPS I NOTE: I = -I 2 FIGURE 2. INPUT OFFSET CURRENT TEST CIRCUIT FIGURE 3. INPUT BIAS CURRENT TEST CIRCUIT 3-4 CA3094, CA3094A, CA3094B Test Circuits (Continued) 30V 7 100 Ω 2 100 Ω 3 VCMR 0.8V TO 27.2V 9.9kΩ 1 1kΩ 200Ω 15V 100pF 8 4.7kΩ 10k Ω CA3094 + 4 6 10kΩ EOUT NOTES: 9. 100 × 26V CMRR = -------------------------------------------- . E 2OUT – E 1OUT 10. Input Voltage Range for CMRR = 1V to 27V. 100 × 26V CMRR (dB) = 20 log -------------------------------------------- . E 2OUT – E 1OUT 11. FIGURE 4. COMMON MODE RANGE AND REJECTION RATIO TEST CIRCUIT +15V IABC 500Ω 10kΩ 3.6kΩ RS (NOTE) 2 5 7 2 8 91Ω 10 Ω 3 6 4 RS (NOTE) 1 CC -15V -15V 3k Ω OUTPUT (RMS) 100Ω 10 Ω 4 OUTPUT RL = 2k Ω IABC 5 7 10k Ω +15V +15V RS -15V CA3094A + 8 CA3094A + 3 120Ω 6 IABC (µA) 5 50 500 CCOMP (pF) 0 50 500 NOTE: RS = 1MΩ (1/F Noise Current Test). RS = 0Ω (1/F Noise Voltage Test). RS (Ω ) 56K 560K 56M IABC (µ A) 500 50 5 FIGURE 5. 1/F NOISE TEST CIRCUIT +15V IABC 5 7 2V 0V 8 2 13kΩ 3 15kΩ FIGURE 6. OPEN LOOP GAIN vs FREQUENCY TEST CIRCUIT +15V 56k Ω 5 7 2 6 ±10V 10kΩ 3 4 2k Ω EOUT 220 Ω 0.001µF CA3094A + CA3094A + 1 4 8 6 10kΩ 2kΩ EOUT -15V -15V FIGURE 7. OPEN LOOP SLEW RATE vs IABC TEST CIRCUIT FIGURE 8. SLEW RATE vs NON-INVERTING UNITY GAIN TEST CIRCUIT 3-5 CA3094, CA3094A, CA3094B Test Circuits (Continued) 120VAC V+ = 30V +15V RLOAD R5 56k Ω 5 7 R2 2 R1 3 8 R3 R6 (NOTE 12) D1 S1 2 3 7 8 5 + CA3094A S2 R1 R2 R3 R4 EOUT MT2 6 CA3094A + 4 6 OUTPUT 2k Ω 4 R8 MT1 R7 C1 51Ω RC 1 COMMON CC NOTES: -15V CLOSED LOOP GAIN (dB) 0 20 40 R1 (kΩ) 10 10 1 R2 (kΩ) R3 (kΩ) 10 10 10 ∞ 1 0.1 12. C1 = 0.5µ F D1 = 1N914 R1 = 0.51MΩ = 3 min. R2 = 5.1MΩ = 30 min. R3 = 22MΩ = 2 hrs. R4 = 44MΩ = 4 hrs. R5 = 1.5kΩ R6 = 50kΩ R7 = 5.1kΩ R8 = 1.5kΩ S1 3 6 29V 0 27V 0 3V Time = 1 hr. S2 Set to R 4 13. Potentiometer required for initial time set to permit device interconnecting. Time variation with temperature