CA3102E

® CA3102 Data Sheet October 12, 2005 FN611.7 Dual High Frequency Differential Amplifier For Low Power Applications Up to 500MHz The CA3102 consists of two independent differential amplifiers with associated constant current transistors on a common monolithic substrate. The six transistors which comprise the amplifiers are general purpose devices which exhibit low 1/f noise and a value of fT in excess of 1GHz. These features make the CA3102 useful from DC to 500MHz. Bias and load resistors have been omitted to provide maximum application flexibility. The monolithic construction of the CA3102 provides close electrical and thermal matching of the amplifiers. This feature makes this device particularly useful in dual channel applications where matched performance of the two channels is required. The CA3102 has a separate substrate connection for greater design flexibility. Features • Power Gain 23dB (Typ) . . . . . . . . . . . . . . . . . . . . 200MHz • Noise Figure 4.6dB (Typ) . . . . . . . . . . . . . . . . . . . 200MHz • Two Differential Amplifiers on a Common Substrate • Independently Accessible Inputs and Outputs • Full Military Temperature Range . . . . . . . -55oC to 125oC • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • VHF Amplifiers • VHF Mixers • Multifunction Combinations - RF/Mixer/Oscillator; Converter/IF • IF Amplifiers (Differential and/or Cascode) • Product Detectors • Doubly Balanced Modulators and Demodulators Ordering Information PART NUMBER (BRAND) CA3102E (CA3102E) CA3102M (3102) CA3102MZ (CA3102MZ) (Note) TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC (Pb-free) PKG. DWG. # E14.3 M14.15 M14.15 • Balanced Quadrature Detectors • Cascade Limiters • Synchronous Detectors • Balanced Mixers • Synthesizers • Balanced (Push-Pull) Cascode Amplifiers • Sense Amplifiers NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout CA3102 (PDIP, SOIC) TOP VIEW 1 2 3 4 SUBSTRATE 5 6 7 14 13 12 SUBSTRATE 11 10 9 8 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA3102 Absolute Maximum Ratings Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . 20V Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . . . 20V Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3102 is isolated from the substrate by an integral diode. The substrate (Terminal 9) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TA = 25oC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER Input Offset Voltage (Figures 1, 4) Input Offset Current (Figure 1) Input Bias Current (Figures 1, 5) Temperature Coefficient Magnitude of Input Offset Voltage VIO IIO IB I3 = I9 = 2mA 0.25 0.3 13.5 1.1 5.0 3.0 33 mV µA µA µV/oC ∆ V IO ---------------∆T DC CHARACTERISTICS FOR EACH TRANSISTOR DC Forward Base-to-Emitter Voltage (Figure 6) VBE ∆ V BE -------------∆T ICBO V(BR)CEO V(BR)CBO V(BR)CIO V(BR)EBO VCE = 6V, IC = 1mA VCE = 6V, IC = 1mA 674 - 774 -0.9 874 - mV mV/oC Temperature Coefficient of Base-to-Emitter Voltage (Figure 6) Collector Cutoff Current (Figure 7) Collector-to-Emitter Breakdown Voltage Collector-to-Base Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage VCB = 10V, IE = 0 IC = 1mA, IB = 0 IC = 10µA, IE = 0 IC = 10µA, IB = IE = 0 IE = 10µA, IC = 0 f = 100kHz, RS = 500Ω, IC = 1mA VCE = 6V, IC = 5mA IC = 0 , VCB = 5V IC = 0, VCI = 5V I3 = I9 = 2mA Bias Voltage = -6V Bias Voltage = -4.2V, f = 10MHz Note 3 Note 4 15 20 20 5 0.0013 24 60 60 7 100 - nA V V V V DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER 1/f Noise Figure (For Single Transistor) (Figure 12) Gain Bandwidth Product (For Single Transistor) (Figure 11) Collector-Base Capacitance (Figure 8) NF fT CCB 18 1.5 1.35 0.28 0.15 1.65 100 75 22 dB GHz pF pF pF dB dB dB Collector-Substrate Capacitance (Figure 8) Common Mode Rejection Ratio AGC Range, One Stage (Figure 2) Voltage Gain, Single-Ended Output (Figures 2, 9, 10) CCI CMRR AGC A 2 CA3102 Electrical Specifications PARAMETER Insertion Power Gain (Figure 3) Noise Figure (Figure 3) Input Admittance TA = 25oC (Continued) SYMBOL GP NF Y11 TEST CONDITIONS VCC = 12V, for Cascode Configuration I3 = I9 = 2mA. For Diff. Amp. Configuration I3 = I9 = 4mA (Each Collector IC ≅ 2mA) f = 200MHz Cascode Cascode Cascode (Figures 14, 16, 18) Diff. Amp. (Figures 15, 17, 19) Cascode Diff. Amp. Forward Transfer Admittance Y21 Cascode (Figures 26, 28, 30) Diff. Amp. (Figures 27, 29, 31) Output Admittance Y22 Cascode (Figures 20, 22, 24) Diff. Amp. (Figures 21, 23, 25) NOTES: 3. Terminals 1 and 14 or 7 and 8. 4. Terminals 13 and 4 or 6 and 11. MIN TYP 23 4.6 1.5 + j2.45 0.878 + j1.3 0.0 - j0.008 0.0 - j0.013 17.9 - j30.7 -10.5 + j13 -0.503 - j15 0.071 + j0.62 MAX UNITS dB dB mS mS mS mS mS mS mS mS Reverse Transfer Admittance Y12 Schematic Diagram CA3102E, CA3102M 1 14 13 4 12 8 7 6 11 Q2 2 Q3 Q1 10 Q6 Q4 Q5 3 5 SUBSTRATE 9 3 CA3102 Test Circuits +6V V+ (+6V) 1kΩ VOUT +1V 1kΩ VO S1 -1V BIAS VOLTAGE 5 VX M I3 or I9 12 1kΩ 10µF S2 M S1 VIN (8) 1 100Ω (10) 2 Q3 (Q4) 3 (9) 500Ω (7) 14 S2 M Q2 (Q6) 13 (6) Q1 (Q5) 100Ω 1kΩ 4 (11) V- (-6V) -6V FIGURE 1. DC CHARACTERISTICS TEST CIRCUIT FOR CA3102 FIGURE 2. AGC RANGE AND VOLTAGE GAIN TEST CIRCUIT FOR CA3102 1/2 CA3102 14(7) Q2 (Q6) Q1 (Q5) 0.005µF 5(12) 1(8) SUBSTRATE Q3 (Q4) 2 (10) 5.6pF 3 (9) 4 (11) 13 (6) 2.7pF 5 µF 6V 2+ 0.001 µF 5pF C2 0.001µF 0.001µF L2 OUTPUT RL = 50Ω INPUT RG = 50Ω L1 C1 100Ω 0.001µF 2kΩ 1kΩ MA 13kΩ 0.001µF FERRITE BEADS 5kΩ 100pF NOTES: 5. Numbers in parentheses refer to the other half of the CA3102. 6. L1, L2 - Approximately 1/2 Turn #18 Tinned Copper Wire, 5/8” Diameter. 100pF 100pF 470pF 10kΩ +12V 0.001µF 7. C1, C2 - 15pF Variable Capacitors (Hammarlund, MAC-15; or Equivalent). FIGURE 3. 200MHz CASCODE POWER GAIN AND NOISE FIGURE TEST CIRCUIT 4 CA3102 Typical Performance Curves 0.5 TA = 25oC INPUT OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (µA) 100 0.4 10 TA = -40oC TA = 25oC TA = 85oC 1.0 0.3 0.2 0.1 1 EMITTER CURRENT (mA) 10 0.1 0.1 1.0 EMITTER CURRENT (mA) 10 FIGURE 4. INPUT OFFSET VOLTAGE vs EMITTER CURRENT FIGURE 5. INPUT BIAS CURRENT vs EMITTER CURRENT 1000 COLLECTOR CUTOFF CURRENT (pA) BASE-TO-EMITTER VOLTAGE (V) VCB = 15V 100 VCB = 10V VCB = 5V 10 1.0 TA = 85oC 0.9 TA = 25oC TA = -40oC 0.8 1.0 0.7 0.6 0.1 0.5 0.1 1.0 COLLECTOR CURRENT (mA) 10 0.01 -100 -75 -50 -25 0 25 TEMPERATURE (οC) 50 75 100 FIGURE 6. BASE-TO-EMITTER VOLTAGE vs COLLECTOR CURRENT FIGURE 7. COLLECTOR CUTOFF CURRENT vs TEMPERATURE 3 TA = 25oC 70 60 50 VOLTAGE GAIN (dB) 40 30 20 10 0 -10 -20 -30 -40 -50 12 13 14 0 TA = 25oC V+ = 6V, V- = -6V f = 1kHz CAPACITANCE (pF) 2 CCI 1 TERMINALS 14 AND 1; 7 AND 8 TERMINALS 13 AND 4; 6 AND 11 CCB 0 0 1 2 3 4 5 67 89 BIAS VOLTAGE (V) 10 11 -1 -2 -3 -4 -5 -6 -7 BIAS VOLTAGE ON TERMINALS 2 AND 10 (V) FIGURE 8. CAPACITANCE vs DC BIAS VOLTAGE FIGURE 9. VOLTAGE GAIN vs DC BIAS VOLTAGE 5 CA3102 Typical Performance Curves 40 35 VOLTAGE GAIN (dB) 30 25 20 15 10 5 0 0.01 GAIN BANDWIDTH PRODUCT (GHz) TA = 25oC (Continued) 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0 1 2 3 45 6 78 9 10 11 12 13 COLLECTOR CURRENT (mA) 14 TA = 25oC 0.1 1.0 FREQUENCY (MHz) 10 100 FIGURE 10. VOLTAGE GAIN vs FREQUENCY FIGURE 11. GAIN BANDWIDTH PRODUCT vs COLLECTOR CURRENT 30 TA = 25oC RSOURCE = 500Ω f = 10Hz 30 NOISE FIGURE (dB) TA = 25oC RSOURCE = 1kΩ f = 10Hz f = 100Hz NOISE FIGURE (dB) f = 100Hz 20 20 f = 10kHz 10 f = 1kHz f = 1kHz 10 f = 10kHz f = 100kHz f = 100kHz 0 0.01 0.1 1.0 COLLECTOR CURRENT (mA) 0 0.01 0.1 1.0 COLLECTOR CURRENT (mA) FIGURE 12. 1/f NOISE FIGURE vs COLLECTOR CURRENT FIGURE 13. 1/f NOISE FIGURE vs COLLECTOR CURRENT 2.5 INPUT CONDUCTANCE (g11) (mS) CASCODE AMPLIFIER VCC = 12V I3 = I9 = 2mA TA = 25oC 25 INPUT SUSCEPTANCE (b11) (mS) 6 DIFFERENTIAL AMPLIFIER VCC = 12V I3 = I9 = 4mA TA = 25oC 2.0 20 OR SUSCEPTANCE (b11) (mS) INPUT CONDUCTANCE (g11) 5 4 b11 1.5 15 3 1.0 g11 10 2 g11 1 0.5 b11 0 10 102 FREQUENCY (MHz) 5 0 103 0 10 102 FREQUENCY (MHz) 103 FIGURE 14. INPUT ADMITTANCE (Y11) vs FREQUENCY FIGURE 15. INPUT ADMITTANCE (Y11) vs FREQUENCY 6 CA3102 Typical Performance Curves (Continued) 3 INPUT CONDUCTANCE OR SUSCEPTANCE (mS) b11 2 INPUT CONDUCTANCE OR SUSCEPTANCE (mS) CASCODE AMPLIFIER I3 = I9 = 2mA f = 200MHz TA = 25oC 3 DIFFERENTIAL AMPLIFIER I3 = I9 = 4mA f = 200MHz TA = 25oC 2 g11 1 1 b11 g11 0 0 10 20 30 40 COLLECTOR SUPPLY VOLTAGE (V) 0 0 10 20 30 40 COLLECTOR SUPPLY VOLTAGE (V) FIGURE 16. INPUT ADMITTANCE (Y11) vs COLLECTOR SUPPLY VOLTAGE FIGURE 17. INPUT ADMITTANCE (Y11) vs COLLECTOR SUPPLY VOLTAGE 7 6 INPUT CONDUCTANCE OR SUSCEPTANCE (mS) 5 4 3 b11 2 1 0 0 2 4 6 8 EMITTER CURRENT (I3 OR I9) (mA) g11 CASCODE AMPLIFIER VCC = 12V f = 200MHz TA = 25oC 3 INPUT CONDUCTANCE OR SUSCEPTANCE (mS) DIFFERENTIAL AMPLIFIER VCC = 12V f = 200MHz TA = 25oC g11 b11 2 1 0 0 5 10 15 20 EMITTER CURRENT (I3 OR I9) (mA) FIGURE 18. INPUT ADMITTANCE (Y11) vs EMITTER CURRENT FIGURE 19. INPUT ADMITTANCE (Y11) vs EMITTER CURRENT 3 2 OUTPUT CONDUCTANCE OR SUSCEPTANCE (mS) 1 0 g22 -1 -2 -3 -4 -5 -6 10 102 FREQUENCY (MHz) 103 b22 CASCODE AMPLIFIER VCC = 12V I3 = I9 = 2mA TA = 25oC 4 DIFFERENTIAL AMPLIFIER VCC = 12V I3 = I9 = 4mA TA = 25oC 2 b22 OUTPUT CONDUCTANCE OR SUSCEPTANCE (mS) 3 1 0 -1 g22 -2 10 102 FREQUENCY (MHz) 103 FIGURE 20. OUTPUT ADMITTANCE (Y22) vs FREQUENCY FIGURE 21. OUTPUT ADMITTANCE (Y22) vs FREQUENCY 7 CA3102 Typical Performance Curves (Continued) 0 OUTPUT CONDUCTANCE OR SUSCEPTANCE (mS) g22 -1 b22 -2 OUTPUT CONDUCTANCE OR SUSCEPTANCE (mS) CASCODE AMPLIFIER I3 = I9 = 2mA f = 200MHz TA = 25oC 0.6 b22 DIFFERENTIAL AMPLIFIER I3 = I9 = 4mA f = 200MHz TA = 25oC 0.4 0.2 g22 -3 0 10 20 30 40 COLLECTOR SUPPLY VOLTAGE (V) 0 0 10 20 30 40 COLLECTOR SUPPLY VOLTAGE (V) FIGURE 22. OUTPUT ADMITTANCE (Y22) vs COLLECTOR SUPPLY VOLTAGE FIGURE 23. OUTPUT ADMITTANCE (Y22) vs COLLECTOR SUPPLY VOLTAGE OUTPUT CONDUCTANCE OR SUSCEPTANCE (mS) 0 -1 -2 -3 g22 OUTPUT CONDUCTANCE OR SUSCEPTANCE (mS) CASCODE AMPLIFIER VCC = 12V f = 200MHz TA = 25oC DIFFERENTIAL AMPLIFIER VCC = 12V f = 200MHz TA = 25oC 1 b22 0 g22 b22 -1 0 2 4 6 8 0 5 10 15 20 EMITTER CURRENT (I3 OR I9) (mA) EMITTER CURRENT (I3 OR I9) (mA) FIGURE 24. OUTPUT ADMITTANCE (Y22) vs EMITTER CURRENT FIGURE 25. OUTPUT ADMITTANCE (Y22) vs EMITTER CURRENT FORWARD TRANSFER CONDUCTANCE (mS) FORWARD TRANSFER SUSCEPTANCE (mS) 60 50 40 30 20 10 0 -10 -20 10 b21 g21 CASCODE AMPLIFIER VCC = 12V I3 = I9 = 2mA TA = 25oC FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (mS) 70 50 40 30 20 10 0 -10 -20 -30 -40 10 102 FREQUENCY (MHz) 103 b21 g21 DIFFERENTIAL AMPLIFIER VCC = 12V I3 = I9 = 4mA TA = 25oC 0 -20 102 FREQUENCY (MHz) -40 103 FIGURE 26. FORWARD TRANSFER ADMITTANCE (Y21) vs FREQUENCY FIGURE 27. FORWARD TRANSFER ADMITTANCE (Y21) vs FREQUENCY 8 CA3102 Typical Performance Curves FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (mS) 20 g21 10 CASCODE AMPLIFIER I3 = I9 = 2mA f = 200MHz TA = 25oC (Continued) 20 FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (mS) 15 b21 10 5 0 -5 -10 -15 g21 DIFFERENTIAL AMPLIFIER I3 = I9 = 4mA f = 200MHz TA = 25oC 0 -10 -20 -30 0 5 b21 10 15 20 25 COLLECTOR SUPPLY VOLTAGE (V) 30 35 0 10 20 30 40 COLLECTOR SUPPLY VOLTAGE (V) FIGURE 28. FORWARD TRANSFER ADMITTANCE (Y21) vs COLLECTOR SUPPLY VOLTAGE FIGURE 29. FORWARD TRANSFER ADMITTANCE (Y21) vs COLLECTOR SUPPLY VOLTAGE 40 FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (mS) FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (mS) 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 2 4 6 8 10 EMITTER CURRENT (I3 OR I9) (mA) 12 14 b21 CASCODE AMPLIFIER VCC = 12V f = 200MHz TA = 25oC g21 50 40 30 20 10 0 -10 -20 0 4 8 12 16 EMITTER CURRENT (I3 OR I9) (mA) g21 DIFFERENTIAL AMPLIFIER VCC = 12V f = 200MHz TA = 25oC b21 FIGURE 30. FORWARD TRANSFER ADMITTANCE (Y21) vs EMITTER CURRENT FIGURE 31. FORWARD TRANSFER ADMITTANCE (Y21) vs EMITTER CURRENT 9 CA3102 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 10 CA3102 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 A1 B C D E α µ A1 0.10(0.004) C e B 0.25(0.010) M C AM BS e H h L N 0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11