CA3127

® CA3127 Data Sheet June 5, 2006 FN662.5 High Frequency NPN Transistor Array The CA3127 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Each of the completely isolated transistors exhibits low 1/f noise and a value of fT in excess of 1GHz, making the CA3127 useful from DC to 500MHz. Access is provided to each of the terminals for the individual transistors and a separate substrate connection has been provided for maximum application flexibility. The monolithic construction of the CA3127 provides close electrical and thermal matching of the five transistors. Features • Gain Bandwidth Product (fT) . . . . . . . . . . . . . . . . . >1GHz • Power Gain . . . . . . . . . . . . . . . . . . 30dB (Typ) at 100MHz • Noise Figure. . . . . . . . . . . . . . . . . 3.5dB (Typ) at 100MHz • Five Independent Transistors on a Common Substrate • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • VHF Amplifiers • Multifunction Combinations - RF/Mixer/Oscillator • Sense Amplifiers Ordering Information PART NUMBER CA3127M CA3127MZ (Note) PART MARKING CA3127 CA3127MZ TEMP. RANGE (°C) -55 to 125 -55 to 125 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. DWG. # M16.15 M16.15 • Synchronous Detectors • VHF Mixers • IF Converter • IF Amplifiers • Synthesizers • Cascade Amplifiers NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout CA3127 (SOIC) TOP VIEW 1 2 Q2 3 4 Q1 16 15 14 13 Q5 12 11 SUBSTRATE 5 6 Q3 7 8 Q4 10 9 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. CA3127 Absolute Maximum Ratings The following ratings apply for each transistor in the device Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . 15V Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . 20V Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . .20V Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Power Dissipation, PD (Any One Transistor). . . . . .85mW Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Packages) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3127 is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TA = 25°C TEST CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS (For Each Transistor) Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Substrate Breakdown-Voltage Emitter-to-Base Breakdown Voltage (Note 3) Collector-Cutoff-Current Collector-Cutoff-Current DC Forward-Current Transfer Ratio IC = 10µA, IE = 0 IC = 1mA, IB = 0 IC1 = 10µA, IB = 0, IE = 0 IE = 10µA, IC = 0 VCE = 10V IB = 0 VCB = 10V, IE = 0 VCE = 6V IC = 5mA IC = 1mA IC = 0.1mA Base-to-Emitter Voltage VCE = 6V IC = 5mA IC = 1mA IC = 0.1mA Collector-to-Emitter Saturation Voltage Magnitude of Difference in VBE Magnitude of Difference in IB DYNAMIC CHARACTERISTICS Noise Figure Gain-Bandwidth Product Collector-to-Base Capacitance Collector-to-Substrate Capacitance Emitter-to-Base Capacitance Voltage Gain Power Gain Noise Figure f = 100kHz, RS = 500Ω, IC = 1mA VCE = 6V, IC = 5mA VCB = 6V, f = 1MHz VCI = 6V, f = 1MHz VBE = 4V, f = 1MHz VCE = 6V, f = 10MHz, RL = 1kΩ, IC = 1mA Cascode Configuration f = 100MHz, V+ = 12V, IC = 1mA 27 28 30 3.5 2.2 1.15 See Fig. 5 dB GHz pF pF pF dB dB dB IC = 10mA, IB = 1mA Q1 and Q2 Matched VCE = 6V, IC = 1mA 20 15 20 4 35 40 35 0.71 0.66 0.60 32 24 60 5.7 88 90 85 0.81 0.76 0.70 0.26 0.5 0.2 0.5 40 0.91 0.86 0.80 0.50 5 3 V V V V mV µA V V V V µA nA 2 FN662.5 June 5, 2006 CA3127 Electrical Specifications PARAMETER Input Resistance Output Resistance Input Capacitance Output Capacitance Magnitude of Forward Transadmittance NOTE: 3. When used as a zener for reference voltage, the device must not be subjected to more than 0.1mJ of energy from any possible capacitance or electrostatic discharge in order to prevent degradation of the junction. Maximum operating zener current should be less than 10mA. TA = 25°C TEST CONDITIONS Common-Emitter Configuration VCE = 6V, IC = 1mA, f = 200 MHz MIN TYP 400 4.6 3.7 2 24 MAX UNITS Ω kΩ pF pF mS Test Circuits V+ 10kΩ BIAS-CURRENT ADJ 470 pF RL 0.01 µF 1µF 51Ω 6 0.01µF 8 1 µF 0.01 µF 470pF 7 VI GEN Q3 470pF 4 2 Q2 3 VO FIGURE 1. VOLTAGE-GAIN TEST CIRCUIT USING CURRENT-MIRROR BIASING FOR Q2 1.5 - 8pF VO 12 SHIELD Q5 2 VI 1000pF 0.3µH 4 1.8pF C1 (NOTE 5) 3 Q2 560Ω 750Ω 1% 1000 pF 6 8 1000 pF 7 25kΩ Q3 5 +12V 13 620Ω 14 1000 pF 1000 pF TEST POINT C2 (NOTE 5) 8.2 kΩ 0.47µH NOTES: 4. This circuit was chosen because it conveniently represents a close approximation in performance to a properly unilateralized single transistor of this type. The use of Q3 in a current-mirror configuration facilitates simplified biasing. The use of the cascode circuit in no way implies that the transistors cannot be used individually. 5. E.F. Johnson number 160-104-1 or equivalent. OHMITE Z144 FIGURE 2. 100MHz POWER-GAIN AND NOISE-FIGURE TEST CIRCUIT 3 FN662.5 June 5, 2006 CA3127 GENERAL RADIO 1021-P1 100MHz GENERATOR ATTN 100MHz TEST SET BOONTON 91C RF VOLTMETER 12VDC POWER SUPPLY FIGURE 3A. POWER GAIN SET-UP VHF NOISE SOURCE HEWLETT PACKARD HP343A 100MHz TEST SET 100MHz POST AMPLIFIER NOISE FIGURE METER HEWLETT PACKARD HP342A 12VDC POWER SUPPLY 15VDC POWER SUPPLY FIGURE 3B. NOISE FIGURE SET-UP FIGURE 3. BLOCK DIAGRAMS OF POWER-GAIN AND NOISE-FIGURE TEST SET-UPS Typical Performance Curves TA = 25°C VCE = 6V RSOURCE = 500Ω f = 10Hz 30 TA = 25°C VCE = 6V RSOURCE = 1kΩ f = 10Hz f = 100Hz 30 NOISE FIGURE (dB) 20 NOISE FIGURE (dB) f = 100Hz 20 f = 10kHz 10 f = 1kHz f = 1kHz 10 f = 10kHz f = 100kHz f = 100kHz 0 0.01 0.1 1.0 COLLECTOR CURRENT (mA) 0 0.01 0.1 1.0 COLLECTOR CURRENT (mA) FIGURE 4. NOISE FIGURE vs COLLECTOR CURRENT FIGURE 5. NOISE FIGURE vs COLLECTOR CURRENT 4 FN662.5 June 5, 2006 CA3127 Typical Performance Curves (Continued) BASE-TO-EMITTER VOLTAGE (V) TA = 25°C VCE = 6V GAIN-BANDWIDTH PRODUCT (GHz) 1.0 TA = -55°C 0.9 0.8 0.7 TA = 125°C 0.6 TA = 25°C 1.2 1.1 1.0 0.9 0.8 0 1 2 3 4 5 6 7 8 9 10 COLLECTOR CURRENT (mA) 0.5 0.4 0.1 1 COLLECTOR CURRENT (mA) 10 FIGURE 6. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CURRENT FIGURE 7. BASE-TO-EMITTER VOLTAGE vs COLLECTOR CURRENT TA = 25°C f = 1MHz 2.25 2.00 CAPACITANCE (pF) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 1 2 3 4 5 CEB CCB 6 7 8 9 10 CCI CAPACITANCE (pF) CCB TRANSISTOR CCE CEB CCI PKG TOTAL PKG TOTAL PKG TOTAL PKG TOTAL 6V 6V 4V 6V BIAS (V) Q1 Q2 Q3 Q4 Q5 BIAS VOLTAGE (V) 0.025 0.190 0.090 0.125 0.365 0.610 0.475 1.65 0.015 0.170 0.225 0.265 0.130 0.360 0.085 1.35 0.040 0.200 0.215 0.240 0.360 0.625 0.210 1.40 0.040 0.190 0.225 0.270 0.365 0.610 0.085 1.25 0.010 0.165 0.095 0.115 0.140 0.365 0.090 1.35 FIGURE 8A. CAPACITANCE vs BIAS VOLTAGE FOR Q2 FIGURE 8B. TYPICAL CAPACITANCE VALUES AT f = 1MHz. THREE TERMINAL MEASUREMENT. GUARD ALL TERMINALS EXCEPT THOSE UNDER TEST. 5 FN662.5 June 5, 2006 CA3127 Typical Performance Curves 40 35 30 VOLTAGE GAIN (dB) 25 20 15 10 5 0 -5 -10 1M 10M 100M FREQUENCY (Hz) 1G IC = 0.2mA IC = 1mA IC = 0.5mA VOLTAGE GAIN (dB) IC = 5mA TA = 25°C, VCE = 6V, RL = 100Ω FOR TEST CIRCUIT SEE FIGURE 19 (Continued) 40 35 30 25 20 15 10 5 0 -5 -10 1M TA = 25°C, VCE = 6V, RL = 1kΩ FOR TEST CIRCUIT SEE FIGURE 19 10M 100M FREQUENCY (Hz) 1G IC = 1mA IC = 0.5mA IC = 0.2mA IC = 5mA FIGURE 10. VOLTAGE GAIN vs FREQUENCY FIGURE 9. VOLTAGE GAIN vs FREQUENCY DC FORWARD CURRENT TRANSFER RATIO 100 TA = 25°C 90 VCE = 6V INPUT CONDUCTANCE (g11) OR SUSCEPTANCE (b11) (mS) 8 7 6 5 4 3 2 1 0 100M FREQUENCY (Hz) g11 b11 TA = 25°C, VCE = 6V, IC = 1mA 80 70 60 50 40 0.1 1.0 COLLECTOR CURRENT (mA) 10 1G FIGURE 11. DC FORWARD-CURRENT TRANSFER RATIO (hFE) vs COLLECTOR CURRENT FIGURE 12. INPUT ADMITTANCE (Y11) vs FREQUENCY 6 FN662.5 June 5, 2006 CA3127 Typical Performance Curves (Continued) OUTPUT CONDUCTANCE (g22) (mS) TA = 25°C VCE = 6V f = 200MHz INPUT CONDUCTANCE (g11) OR 9 SUSCEPTANCE (b11) (mS) 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 COLLECTOR CURRENT (mA) 9 10 b11 g11 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 100M b22 8 7 6 5 4 3 g22 2 1 0 1G FREQUENCY (Hz) FIGURE 13. INPUT ADMITTANCE (Y11) vs COLLECTOR CURRENT FIGURE 14. OUTPUT ADMITTANCE (Y22) vs FREQUENCY MAGNITUDE OF FORWARD TRANSADMITTANCE (|Y21|) (mS) OUTPUT CONDUCTANCE (g22) (mS) TA = 25°C VCE = 6V f = 200MHz 0.400 0.375 0.350 0.325 0.300 0.275 0.250 0.225 0.200 0.175 0 1 2 TA = 25°C OUTPUT SUSCEPTANCE (b22) (mS) b22 100 80 |Y21| VCE = 6V f = 200MHz 0 PHASE-ANGLE OF FORWARD TRANSADMITTANCE (|θ21|) (°) 2.8 2.7 -20 g22 2.6 2.5 2.4 2.3 2.2 2.1 2.0 60 -40 40 θ21 -60 20 -80 3 4 5 6 7 8 9 10 11 COLLECTOR CURRENT (mA) 1.9 12 0 1 2 -100 3 4 5 6 7 8 9 10 11 12 COLLECTOR CURRENT (mA) FIGURE 15. OUTPUT ADMITTANCE (Y22) vs COLLECTOR CURRENT FIGURE 16. FORWARD TRANSADMITTANCE (Y21) vs COLLECTOR CURRENT 7 FN662.5 June 5, 2006 OUTPUT SUSCEPTANCE (b22) (mS) TA = 25°C VCE = 6V IC = 1mA CA3127 Typical Performance Curves (Continued) TA = 25°C VCE = 6V IC = 1mA MAGNITUDE OF FORWARD TRANSADMITTANCE (|Y21|) (mS) -10 MAGNITUDE OF REVERSE TRANSADMITTANCE (|Y12|) (mS) PHASE-ANGLE OF FORWARD TRANSADMITTANCE (|θ21|) (°) -20 -30 -40 θ21 -50 -60 f = 200MHz θ12 -80 -90 -100 -110 -120 -130 -140 30 20 10 0 100M |Y21| -70 -80 -90 -100 |Y12| 0.21 150M 200M FREQUENCY (Hz) 1G 0 1 2 -150 3 4 5 6 7 8 9 10 11 12 COLLECTOR CURRENT (mA) FIGURE 17. FORWARD TRANSADMITTANCE (Y21) vs FREQUENCY FIGURE 18. REVERSE TRANSADMITTANCE (Y12) vs COLLECTOR CURRENT TA = 25°C VCE = 6V IC = 1mA MAGNITUDE OF REVERSE TRANSADMITTANCE (|Y12|) (mS) 0.6 0.5 0.4 0.3 0.2 0.1 0 100M |Y12| θ12 -90 -95 -100 -105 -110 -115 -120 FREQUENCY (Hz) 1G PHASE-ANGLE OF REVERSE TRANSADMITTANCE (|θ12|) (°) FIGURE 19. REVERSE TRANSADMITTANCE (Y12) vs FREQUENCY 8 FN662.5 June 5, 2006 PHASE-ANGLE OF REVERSE TRANSADMITTANCE (|θ12|) (°) TA = 25°C VCE = 6V CA3127 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8° Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 16 0° 8° 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0° 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN662.5 June 5, 2006