CA3130AT

CA3130, CA3130A Data Sheet September 1998 File Number 817.4 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output CA3130A and CA3130 are op amps that combine the advantage of both CMOS and bipolar transistors. Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. The use of PMOS transistors in the input stage results in common-mode input-voltage capability down to 0.5V below the negative-supply terminal, an important attribute in single-supply applications. A CMOS transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA3130 Series circuits operate at supply voltages ranging from 5V to 16V, (±2.5V to ±8V). They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage. The CA3130A offers superior input characteristics over those of the CA3130. Features • MOSFET Input Stage Provides: - Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ) - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation . . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation • Ideal for Single-Supply Applications • Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.5V Below Negative Supply Rail • CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails Applications • Ground-Referenced Single Supply Amplifiers • Fast Sample-Hold Amplifiers • Long-Duration Timers/Monostables • High-Input-Impedance Comparators (Ideal Interface with Digital CMOS) • High-Input-Impedance Wideband Amplifiers • Voltage Followers (e.g. Follower for Single-Supply D/A Converter) • Voltage Regulators (Permits Control of Output Voltage Down to 0V) • Peak Detectors • Single-Supply Full-Wave Precision Rectifiers • Photo-Diode Sensor Amplifiers Pinouts CA3130, CA3130A (PDIP, SOIC) TOP VIEW OFFSET NULL INV. INPUT NON-INV. INPUT V- 1 2 3 4 8 STROBE V+ OUTPUT OFFSET NULL Ordering Information PART NO. (BRAND) CA3130AE CA3130AM + 7 6 5 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC Tape and Reel 8 Pin Metal Can 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC Tape and Reel 8 Pin Metal Can PKG. NO. E8.3 M8.15 M8.15 T8.C E8.3 M8.15 M8.15 T8.C CA3130, CA3130A (METAL CAN) TOP VIEW PHASE COMPENSATION TAB 8 OFFSET NULL INV. INPUT 2 1 7 V+ STROBE (3130A) CA3130AM96 (3130A) CA3130AT CA3130E CA3130M + 3 4 5 (3130) 6 OUTPUT CA3130M96 (3130) OFFSET NULL NON-INV. INPUT CA3130T V- AND CASE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CA3130, CA3130A Absolute Maximum Ratings DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A Metal Can Package . . . . . . . . . . . . . . . 170 85 Maximum Junction Temperature (Metal Can Package) . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Offset Voltage Input Offset Voltage Temperature Drift Input Offset Current Input Current Large-Signal Voltage Gain TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VS = ±7.5V CA3130 MIN VS = ±7.5V VS = ±7.5V VO = 10VP-P RL = 2kΩ 50 94 70 0 VS = ±7.5V RL = 2kΩ RL = 2kΩ RL = ∞ RL = ∞ 12 14.99 12 12 TYP 8 10 0.5 5 320 110 90 -0.5 to 12 32 13.3 0.002 15 0 22 20 10 2 MAX 15 30 50 10 320 0.01 0.01 45 45 15 3 MIN 50 94 80 0 12 14.99 12 12 CA3130A TYP 2 10 0.5 5 320 110 90 -0.5 to 12 32 13.3 0.002 15 0 22 20 10 2 MAX 5 20 30 10 150 0.01 0.01 45 45 15 3 UNITS mV µV/oC pA pA kV/V dB dB V µV/V V V V V mA mA mA mA SYMBOL |VIO| ∆VIO/∆T |IIO| II AOL Common-Mode Rejection Ratio Common-Mode Input Voltage Range Power-Supply Rejection Ratio Maximum Output Voltage CMRR VICR ∆VIO/∆VS VOM+ VOMVOM+ VOM- Maximum Output Current IOM+ (Source) at VO = 0V IOM- (Sink) at VO = 15V Supply Current I+ I+ VO = 7.5V, RL = ∞ VO = 0V, RL = ∞ 2 CA3130, CA3130A Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC Unless Otherwise Specified SYMBOL TEST CONDITIONS 10kΩ Across Terminals 4 and 5 or 4 and 1 RI CI eN f = 1MHz BW = 0.2MHz, RS = 1MΩ (Note 3) CC = 0 CC = 47pF CA3130, CA3130A ±22 1.5 4.3 23 15 4 UNITS mV TΩ pF µV MHz MHz PARAMETER Input Offset Voltage Adjustment Range Input Resistance Input Capacitance Equivalent Input Noise Voltage Open Loop Unity Gain Crossover Frequency (For Unity Gain Stability ≥47pF Required.) Slew Rate: Open Loop Closed Loop Transient Response: Rise Time Overshoot Settling Time (To