CA3140T

CA3140, CA3140A Data Sheet September 1998 File Number 957.4 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output The CA3140A and CA3140 are integrated circuit operational amplifiers that combine the advantages of high voltage PMOS transistors with high voltage bipolar transistors on a single monolithic chip. The CA3140A and CA3140 BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. The CA3140A and CA3140 operate at supply voltage from 4V to 36V (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute for single supply applications. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. The CA3140 Series has the same 8-lead pinout used for the “741” and other industry standard op amps. The CA3140A and CA3140 are intended for operation at supply voltages up to 36V (±18V). Features • MOSFET Input Stage - Very High Input Impedance (ZIN) -1.5TΩ (Typ) - Very Low Input Current (Il) -10pA (Typ) at ±15V - Wide Common Mode Input Voltage Range (VlCR) - Can be Swung 0.5V Below Negative Supply Voltage Rail - Output Swing Complements Input Common Mode Range • Directly Replaces Industry Type 741 in Most Applications Applications • Ground-Referenced Single Supply Amplifiers in Automobile and Portable Instrumentation • Sample and Hold Amplifiers • Long Duration Timers/Multivibrators (µseconds-Minutes-Hours) • Photocurrent Instrumentation • Peak Detectors • Active Filters • Comparators • Interface in 5V TTL Systems and Other Low Supply Voltage Systems • All Standard Operational Amplifier Applications • Function Generators • Tone Controls • Power Supplies • Portable Instruments • Intrusion Alarm Systems Ordering Information PART NUMBER (BRAND) CA3140AE CA3140AM (3140A) CA3140AS CA3140AT CA3140E CA3140M (3140) CA3140M96 (3140) CA3140T TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld SOIC 8 Pin Metal Can 8 Pin Metal Can 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC Tape and Reel 8 Pin Metal Can T8.C PKG. NO. E8.3 M8.15 T8.C T8.C E8.3 M8.15 Pinouts CA3140 (METAL CAN) TOP VIEW TAB 8 OFFSET NULL INV. 2 INPUT NON-INV. INPUT 3 1 7 V+ 6 OUTPUT STROBE + 5 OFFSET NULL 4 V- AND CASE CA3140 (PDIP, SOIC) TOP VIEW OFFSET NULL INV. INPUT NON-INV. INPUT V1 2 3 4 8 STROBE V+ OUTPUT OFFSET NULL + 7 6 5 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CA3140, CA3140A Absolute Maximum Ratings DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0.5V) Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . Indefinite . Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A Metal Can Package . . . . . . . . . . . . . . . 170 85 Maximum Junction Temperature (Metal Can Package). . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Short circuit may be applied to ground or to either supply. Electrical Specifications PARAMETER VSUPPLY = ±15V, TA = 25oC TYPICAL VALUES SYMBOL TEST CONDITIONS Typical Value of Resistor Between Terminals 4 and 5 or 4 and 1 to Adjust Max VIO RI CI RO eN eN BW = 140kHz, RS = 1MΩ RS = 100Ω f = 1kHz f = 10kHz CA3140 4.7 CA3140A 18 UNITS kΩ Input Offset Voltage Adjustment Resistor Input Resistance Input Capacitance Output Resistance Equivalent Wideband Input Noise Voltage (See Figure 27) Equivalent Input Noise Voltage (See Figure 35) 1.5 4 60 48 40 12 40 18 4.5 9 220 1.5 4 60 48 40 12 40 18 4.5 9 220 0.08 10 4.5 1.4 TΩ pF Ω µV nV/√Hz nV/√Hz mA mA MHz V/µs µA µs % µs µs Short Circuit Current to Opposite Supply IOM+ IOM- Source Sink Gain-Bandwidth Product, (See Figures 6, 30) Slew Rate, (See Figure 31) Sink Current From Terminal 8 To Terminal 4 to Swing Output Low Transient Response (See Figure 28) fT SR tr OS RL = 2kΩ CL = 100pF RL = 2kΩ CL = 100pF Voltage Follower Rise Time Overshoot To 1mV To 10mV 0.08 10 4.5 1.4 Settling Time at 10VP-P, (See Figure 5) tS Electrical Specifications PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain (Note 3) (See Figures 6, 29) For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified CA3140 SYMBOL |VIO| |IIO| II AOL MIN 20 86 TYP 5 0.5 10 100 100 MAX 15 30 50 MIN 20 86 CA3140A TYP 2 0.5 10 100 100 MAX 5 20 40 UNITS mV pA pA kV/V dB 2 CA3140, CA3140A Electrical Specifications PARAMETER Common Mode Rejection Ratio (See Figure 34) Common Mode Input Voltage Range (See Figure 8) Power-Supply Rejection Ratio, ∆VIO/∆VS (See Figure 36) Max Output Voltage (Note 4) (See Figures 2, 8) Supply Current (See Figure 32) Device Dissipation Input Offset Voltage Temperature Drift NOTES: 3. At VO = 26VP-P , +12V, -14V and RL = 2kΩ. 4. At RL = 2kΩ. For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued) CA3140 SYMBOL CMRR MIN 70 VICR PSRR -15 76 VOM+ VOMI+ PD ∆VIO/∆T +12 -14 TYP 32 90 -15.5 to +12.5 100 80 13 -14.4 4 120 8 MAX 320 11 150 6 180 MIN 70 -15 76 +12 -14 CA3140A TYP 32 90 -15.5 to +12.5 100 80 13 -14.4 4 120 6 MAX 320 12 150 6 180 UNITS µV/V dB V µV/V dB V V mA mW µV/oC Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC TYPICAL VALUES PARAMETER Input Offset Voltage Input Offset Current Input Current Input Resistance Large Signal Voltage Gain (See Figures 6, 29) SYMBOL |VIO| |IIO| II RI AOL CA3140 5 0.1 2 1 100 100 CA3140A 2 0.1 2 1 100 100 32 90 -0.5 2.6 100 80 3 0.13 10 1 7 3.7 1.6 8 200 UNITS mV pA pA TΩ kV/V dB µV/V dB V V µV/V dB V V mA mA V/µs MHz mA mW µA Common Mode Rejection Ratio CMRR 32 90 Common Mode Input Voltage Range (See Figure 8) VICR -0.5 2.6 Power Supply Rejection Ratio PSRR ∆VIO/∆VS VOM+ VOM- 100 80 3 0.13 10 1 7 3.7 1.6 8 200 Maximum Output Voltage (See Figures 2, 8) Maximum Output Current: Source Sink IOM+ I OM- Slew Rate (See Figure 31) Gain-Bandwidth Product (See Figure 30) Supply Current (See Figure 32) Device Dissipation Sink Current from Terminal 8 to Terminal 4 to Swing Output Low SR fT I+ PD 3 CA3140, CA3140A Block Diagram 2mA BIAS CIRCUIT CURRENT SOURCES AND REGULATOR + 3 INPUT 200µA 1.6mA 200µA A≈ 10,000 C1 12pF STROBE 4 V8 2µA 2mA 4mA 7 V+ - A ≈ 10 A≈1 6 OUTPUT 2 5 1 OFFSET NULL Schematic Diagram BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK 7 V+ D1 Q3 D7 Q2 R9 50Ω R10 1K Q19 R11 20Ω R12 12K Q20 R13 5K Q1 D8 R14 20K Q6 Q7 Q5 Q4 Q17 R1 8K Q8 R8 1K Q 18 Q21 6 OUTPUT D2 D3 D4 D5 INVERTING INPUT NON-INVERTING INPUT 2 + 3 R2 500Ω R3 500Ω - Q9 Q10 C1 12pF Q14 Q15 Q16 D6 R6 50Ω R7 30Ω Q13 Q11 Q12 R4 500Ω R5 500Ω 5 OFFSET NULL 1 8 STROBE 4 V- NOTE: All resistance values are in ohms. 4 CA3140, CA3140A Application Information Circuit Description As shown in the block diagram, the input terminals may be operated down to 0.5V below the negative supply rail. Two class A amplifier stages provide the voltage gain, and a unique class AB amplifier stage provides the current gain necessary to drive low-impedance loads. A biasing circuit provides control of cascoded constant current flow circuits in the first and second stages. The CA3140 includes an on chip phase compensating capacitor that is sufficient for the unity gain voltage follower configuration. When the CA3140 is operating such that output Terminal 6 is sinking current to the V- bus, transistor Q16 is the current sinking element. Transistor Q16 is mirror connected to D6, R7, with current fed by way of Q21, R12, and Q20. Transistor Q20, in turn, is biased by current flow through R13, zener D8, and R14. The dynamic current sink is controlled by voltage level sensing. For purposes of explanation, it is assumed that output Terminal 6 is quiescently established at the potential midpoint between the V+ and V- supply rails. When output current sinking mode operation is required, the collector potential of transistor Q13 is driven below its quiescent level, thereby causing Q17, Q18 to decrease the output voltage at Terminal 6. Thus, the gate terminal of PMOS transistor Q21 is displaced toward the V- bus, thereby reducing the channel resistance of Q21. As a consequence, there is an incremental increase in current flow through Q20, R12, Q21, D6, R7, and the base of Q16. As a result, Q16 sinks current from Terminal 6 in direct response to the incremental change in output voltage caused by Q18. This sink current flows regardless of load; any excess current is internally supplied by the emitter-follower Q18. Short circuit protection of the output circuit is provided by Q19, which is driven into conduction by the high voltage drop developed across R11 under output short circuit conditions. Under these conditions, the collector of Q19 diverts current from Q4 so as to reduce the base current drive from Q17, thereby limiting current flow in Q18 to the short circuited load terminal. Input Stage The schematic diagram consists of a differential input stage using PMOS field-effect transistors (Q9, Q10) working into a mirror pair of bipolar transistors (Q11, Q12) functioning as load resistors together with resistors R2 through R5. The mirror pair transistors also function as a differential-to-single-ended converter to provide base current drive to the second stage bipolar transistor (Q13). Offset nulling, when desired, can be effected with a 10kΩ potentiometer connected across Terminals 1 and 5 and with its slider arm connected to Terminal 4. Cascode-connected bipolar transistors Q2, Q5 are the constant current source for the input stage. The base biasing circuit for the constant current source is described subsequently. The small diodes D3, D4, D5 provide gate oxide protection against high voltage transients, e.g., static electricity. Bias Circuit Quiescent current in all stages (except the dynamic current sink) of the CA3140 is dependent upon bias current flow in R1. The function of the bias circuit is to establish and maintain constant current flow through D1, Q6, Q8 and D2. D1 is a diode connected transistor mirror connected in parallel with the base emitter junctions of Q1, Q2, and Q3. D1 may be considered as a current sampling diode that senses the emitter current of Q6 and automatically adjusts the base current of Q6 (via Q1) to maintain a constant current through Q6, Q8, D2. The base currents in Q2, Q3 are also determined by constant current flow D1. Furthermore, current in diode connected transistor Q2 establishes the currents in transistors Q14 and Q15. Second Stage Most of the voltage gain in the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor Q13 and its cascode connected load resistance provided by bipolar transistors Q3, Q4. On-chip phase compensation, sufficient for a majority of the applications is provided by C1. Additional Miller-Effect compensation (roll off) can be accomplished, when desired, by simply connecting a small capacitor between Terminals 1 and 8. Terminal 8 is also used to strobe the output stage into quiescence. When terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output Terminal 6 swings low, i.e., approximately to Terminal 4 potential. Typical Applications Wide dynamic range of input and output characteristics with the most desirable high input impedance characteristics is achieved in the CA3140 by the use of an unique design based upon the PMOS Bipolar process. Input common mode voltage range and output swing capabilities are complementary, allowing operation with the single supply down to 4V. The wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example, where one input is driven below the potential of Terminal 4 and the phase sense of the output signal must be maintained – a most important consideration in comparator applications. Output Stage The CA3140 Series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the PMOS input stage when operating near the negative rail. Quiescent current in the emitter-follower cascade circuit (Q17, Q18) is established by transistors (Q14, Q15) whose base currents are “mirrored” to current flowing through diode D2 in the bias circuit section. When the CA3140 is operating such that output Terminal 6 is sourcing current, transistor Q18 functions as an emitter-follower to source current from the V+ bus (Terminal 7), via D7, R9, and R11. Under these conditions, the collector potential of Q13 is sufficiently high to permit the necessary flow of base current to emitter follower Q17 which, in turn, drives Q18. 5 CA3140, CA3140A Output Circuit Considerations Excellent interfacing with TTL circuitry is easily achieved with a single 6.2V zener diode connected to Terminal 8 as shown in Figure 1. This connection assures that the maximum output signal swing will not go more positive than the zener voltage minus two base-to-emitter voltage drops within the CA3140. These voltages are independent of the operating supply voltage. V+ 5V TO 36V 7 2 8 CA3140 3 4 6.2V 6 LOGIC SUPPLY 5V TYPICAL TTL GATE level shifting circuitry usually associated with the 741 series of operational amplifiers. Figure 4 shows some typical configurations. Note that a series resistor, RL, is used in both cases to limit the drive available to the driven device. Moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. Offset Voltage Nulling The input offset voltage can be nulled by connecting a 10kΩ potentiometer between Terminals 1 and 5 and returning its wiper arm to terminal 4, see Figure 3A. This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors (R) that may be placed at either end of the potentiometer, see Figure 3B, to optimize its utilization range are given in the Electrical Specifications table. An alternate system is shown in Figure 3C. This circuit uses only one additional resistor of approximately the value shown in the table. For potentiometers, in which the resistance does not drop to 0Ω at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used. ≈ 5V FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING TO TTL LEVELS OUTPUT STAGE TRANSISTOR (Q15, Q16) SATURATION VOLTAGE (mV) 1000 SUPPLY VOLTAGE (V-) = 0V TA = 25oC 100 SUPPLY VOLTAGE (V+) = +5V +15V +30V Low Voltage Operation Operation at total supply voltages as low as 4V is possible with the CA3140. A current regulator based upon the PMOS threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages. 10 1 0.01 0.1 1.0 LOAD (SINKING) CURRENT (mA) 10 FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15 AND Q16) vs LOAD CURRENT Figure 2 shows output current sinking capabilities of the CA3140 at various supply voltages. Output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for V+ V+ 2 7 CA3140 CA3140 3 5 1 10kΩ R 4 1 R 10kΩ 6 3 5 4 6 2 7 The low voltage limitation occurs when the upper extreme of the input common mode voltage range extends down to the voltage at Terminal 4. This limit is reached at a total supply voltage just below 4V. The output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the input. Figure 8 shows these characteristics and shows that with 2V dual supplies, the lower extreme of the input common mode voltage range is below ground potential. V+ 2 7 CA3140 3 5 1 10kΩ R 4 6 V- V- V- FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS 6 CA3140, CA3140A RS LOAD 30V NO LOAD 120VAC 7 2 CA3140 3 4 6 RL MT1 MT2 3 4 2 7 V+ +HV LOAD 6 RL CA3140 FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES FOLLOWER +15V 7 3 10kΩ CA3140 2 4 -15V 2kΩ 6 100pF 0.1µF 2kΩ 0.1µF SIMULATED LOAD LOAD RESISTANCE (RL) = 2kΩ LOAD CAPACITANCE (CL) = 100pF SUPPLY VOLTAGE: VS = ±15V TA = 25oC 10 8 6 INPUT VOLTAGE (V) 4 2 0 -2 -4 -6 -8 -10 0.1 10mV 1mV 10mV 10 D1 1N914 D2 1mV 4.99kΩ FOLLOWER INVERTING 5kΩ 200Ω 3 10mV 10mV 2 1mV 1mV 0.05µF INVERTING 5kΩ +15V 7 0.1µF 6 100pF 4 -15V SETTLING POINT 0.1µF 5.11kΩ 2kΩ SIMULATED LOAD CA3140 1.0 SETTLING TIME (µs) 1N914 FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS FIGURE 5. SETTLING TIME vs INPUT VOLTAGE Bandwidth and Slew Rate For those cases where bandwidth reduction is desired, for example, broadband noise reduction, an external capacitor connected between Terminals 1 and 8 can reduce the open loop -3dB bandwidth. The slew rate will, however, also be proportionally reduced by using this additional capacitor. Thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%. Figure 5 shows the typical settling time required to reach 1mV or 10mV of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers. The exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the CA3140; as shown in Figure 6. Input Circuit Considerations As mentioned previously, the amplifier inputs can be driven below the Terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry. Moreover, some current limiting resistance should be provided between the inverting input and the output when the CA3140 is used as a unity gain voltage follower. This resistance prevents the possibility of extremely large input 7 CA3140, CA3140A signal transients from forcing a signal through the input protection network and directly driving the internal constant current source which could result in positive feedback via the output terminal. A 3.9kΩ resistor is sufficient. The typical input current is on the order of 10pA when the inputs are centered at nominal device dissipation. As the output supplies load current, device dissipation will increase, raising the chip temperature and resulting in increased input current. Figure 7 shows typical input terminal current versus ambient temperature for the CA3140. It is well known that MOSFET devices can exhibit slight changes in characteristics (for example, small changes in input offset voltage) due to the application of large OPEN LOOP PHASE (DEGREES) SUPPLY VOLTAGE: VS = ±15V TA = 25oC 100 80 60 40 20 0 101 RL = 2kΩ, CL = 100pF φOL -75 RL = 2kΩ, CL = 0pF -90 -105 -120 -135 -150 differential input voltages that are sustained over long periods at elevated temperatures. Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite polarity reverse the offset. Figure 9 shows the typical offset voltage change as a function of various stress voltages at the maximum rating of 125oC (for metal can); at lower temperatures (metal can and plastic), for example, at 85oC, this change in voltage is considerably less. In typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. 10K SUPPLY VOLTAGE: VS = ±15V OPEN LOOP VOLTAGE GAIN (dB) INPUT CURRENT (pA) 1K 100 10 102 103 104 105 106 FREQUENCY (Hz) 107 108 1 -60 -40 -20 0 20 40 60 80 TEMPERATURE (oC) 100 120 140 FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs FREQUENCY FIGURE 7. INPUT CURRENT vs TEMPERATURE INPUT AND OUTPUT VOLTAGE EXCURSIONS FROM TERMINAL 7 (V+) RL = ∞ 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 +VICR AT TA = 125oC +VICR AT TA = 25oC +VICR AT TA = -55oC +VOUT AT TA = 125oC +VOUT AT TA = 25oC +VOUT AT TA = -55oC INPUT AND OUTPUT VOLTAGE EXCURSIONS FROM TERMINAL 4 (V-) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -VOUT FOR TA = -55oC to 125oC -VICR AT TA = 125oC -VICR AT TA = 25oC -VICR AT TA = -55oC 0 5 10 15 SUPPLY VOLTAGE (V+, V-) 20 25 0 5 10 15 SUPPLY VOLTAGE (V+, V-) 20 25 FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 8 CA3140, CA3140A 7 OFFSET VOLTAGE SHIFT (mV) 6 5 4 3 2 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 TIME (HOURS) DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2 TA = 125oC FOR METAL CAN PACKAGES DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 2V OUTPUT STAGE TOGGLED placed across the input to the CA3080A to give a logarithmic analog indication of the function generator’s frequency. Analog frequency readout is readily accomplished by the means described above because the output current of the CA3080A varies approximately one decade for each 60mV change in the applied voltage, VABC (voltage between Terminals 5 and 4 of the CA3080A of the function generator). Therefore, six decades represent 360mV change in VABC. Now, only the reference voltage must be established to set the lower limit on the meter. The three remaining transistors from the CA3086 Array used in the sweep generator are used for this reference voltage. In addition, this reference generator arrangement tends to track ambient temperature variations, and thus compensates for the effects of the normal negative temperature coefficient of the CA3080A VABC terminal voltage. Another output voltage from the reference generator is used to insure temperature tracking of the lower end of the Frequency Adjustment Potentiometer. A large series resistance simulates a current source, assuring similar temperature coefficients at both ends of the Frequency Adjustment Control. To calibrate this circuit, set the Frequency Adjustment Potentiometer at its low end. Then adjust the Minimum Frequency Calibration Control for the lowest frequency. To establish the upper frequency limit, set the Frequency Adjustment Potentiometer to its upper end and then adjust the Maximum Frequency Calibration Control for the maximum frequency. Because there is interaction among these controls, repetition of the adjustment procedure may be necessary. Two adjustments are used for the meter. The meter sensitivity control sets the meter scale width of each decade, while the meter position control adjusts the pointer on the scale with negligible effect on the sensitivity adjustment. Thus, the meter sensitivity adjustment control calibrates the meter so that it deflects 1/6 of full scale for each decade change in frequency. FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE Super Sweep Function Generator A function generator having a wide tuning range is shown in Figure 10. The 1,000,000/1 adjustment range is accomplished by a single variable potentiometer or by an auxiliary sweeping signal. The CA3140 functions as a noninverting readout amplifier of the triangular signal developed across the integrating capacitor network connected to the output of the CA3080A current source. Buffered triangular output signals are then applied to a second CA3080 functioning as a high speed hysteresis switch. Output from the switch is returned directly back to the input of the CA3080A current source, thereby, completing the positive feedback loop The triangular output level is determined by the four 1N914 level limiting diodes of the second CA3080 and the resistor divider network connected to Terminal No. 2 (input) of the CA3080. These diodes establish the input trip level to this switching stage and, therefore, indirectly determine the amplitude of the output triangle. Compensation for propagation delays around the entire loop is provided by one adjustment on the input of the CA3080. This adjustment, which provides for a constant generator amplitude output, is most easily made while the generator is sweeping. High frequency ramp linearity is adjusted by the single 7pF to 60pF capacitor in the output of the CA3080A. It must be emphasized that only the CA3080A is characterized for maximum output linearity in the current generator function. Sine Wave Shaper The circuit shown in Figure 12 uses a CA3140 as a voltage follower in combination with diodes from the CA3019 Array to convert the triangular signal from the function generator to a sine-wave output signal having typically less than 2% THD. The basic zero crossing slope is established by the 10kΩ potentiometer connected between Terminals 2 and 6 of the CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer from Terminal 2 to ground. Two break points are established by diodes D1 through D4. Positive feedback via D5 and D6 establishes the zero slope at the maximum and minimum levels of the sine wave. This technique is necessary because the voltage follower configuration approaches unity gain rather than the zero gain required to shape the sine wave at the two extremes. Meter Driver and Buffer Amplifier Figure 11 shows the CA3140 connected as a meter driver and buffer amplifier. Low driving impedance is required of the CA3080A current source to assure smooth operation of the Frequency Adjustment Control. This low-driving impedance requirement is easily met by using a CA3140 connected as a voltage follower. Moreover, a meter may be 9 CA3140, CA3140A CENTERING -15V 10kΩ 62kΩ 5 11kΩ 11kΩ 10kΩ EXTERNAL OUTPUT 2 3 +15V 7.5kΩ 360Ω 3 360Ω 2 2MΩ SYMMETRY -15V +15V 100kΩ FROM BUFFER METER DRIVER (OPTIONAL) -15V + +15V 7 6 7-60 pF HIGH FREQ. SHAPE +15V 0.1 µF 6 15kΩ 51 pF 3 2 7 + CA3140 HIGH FREQUENCY LEVEL 910kΩ 7-60pF 10kΩ EXTERNAL OUTPUT 6 2.7kΩ -15V TO OUTPUT AMPLIFIER CA3080A 5 - 7 4 -15V 4 -15V 2kΩ 0.1 µF CA3080 + 4 13kΩ 39kΩ 120Ω 10kΩ +15V FREQUENCY ADJUSTMENT 5.1kΩ TO SINE WAVE SHAPER THIS NETWORK IS USED WHEN THE OPTIONAL BUFFER CIRCUIT IS NOT USED OUTPUT AMPLIFIER 1N914 FIGURE 10A. CIRCUIT FREQUENCY ADJUSTMENT Top Trace: Output at junction of 2.7Ω and 51Ω resistors; 5V/Div., 500ms/Div. Center Trace: External output of triangular function generator; 2V/Div., 500ms/Div. Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div. FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING METER DRIVER AND BUFFER AMPLIFIER FUNCTION GENERATOR +15V M POWER SUPPLY ±15V -15V SINE WAVE SHAPER WIDEBAND LINE DRIVER 51Ω GATE DC LEVEL SWEEP ADJUST OFF INT. COARSE RATE VEXT. EXTERNAL INPUT FINE RATE SWEEP GENERATOR 1V/Div., 1s/Div. Three tone test signals, highest frequency ≥0.5MHz. Note the slight asymmetry at the three second/cycle signal. This asymmetry is due to slightly different positive and negative integration from the CA3080A and from the PC board and component leakages at the 100pA level. FIGURE 10C. FUNCTION GENERATOR WITH FIXED FREQUENCIES SWEEP LENGTH V- FIGURE 10D. INTERCONNECTIONS FIGURE 10. FUNCTION GENERATOR 10 CA3140, CA3140A FREQUENCY CALIBRATION MAXIMUM 620kΩ 7 51kΩ 3 + CA3140 3MΩ 2 2kΩ 6 4.7kΩ 4 0.1µF +15V 500kΩ FREQUENCY ADJUSTMENT 10kΩ SWEEP IN - TO CA3080A OF FUNCTION CA3080A GENERATOR (FIGURE 10) 4 5 METER SENSITIVITY ADJUSTMENT 620Ω 1kΩ 200µA M METER 11 9 510Ω 8 6 7 METER POSITION ADJUSTMENT 2kΩ 10 12 3.6kΩ 13 14 +15V -15V 0.1µF 5.6kΩ 7.5kΩ TO WIDEBAND OUTPUT AMPLIFIER 10kΩ EXTERNAL OUTPUT D4 5.1kΩ 3 2 + 7 6 CA3140 - 4 SUBSTRATE OF CA3019 12kΩ FREQUENCY 2.4kΩ CALIBRATION MINIMUM 2.5 kΩ 510Ω 0.1µF +15V 100 kΩ -15V 1MΩ 9.1kΩ 6 D3 D1 7 -15V R3 10kΩ R1 10kΩ 5 D6 9 8 D2 1 2 430Ω R2 1kΩ 3/ OF CA3086 5 -15V 3 4 D CA3019 5 DIODE ARRAY FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER 750kΩ “LOG” SAWTOOTH 18MΩ 1N914 1MΩ 22MΩ SAWTOOTH SYMMETRY 100kΩ 100kΩ FINE RATE 8.2kΩ 1N914 0.47µF 0.047µF 4700pF 470pF +15V SAWTOOTH AND RAMP LOW LEVEL SET (-14.5V) 50kΩ 75kΩ COARSE RATE 2 3 - 7 +15V 0.1 µF 6 0.1 µF SAWTOOTH “LOG”+15V TRIANGLE 30kΩ 50kΩ LOG RATE ADJUST 10kΩ -15V 10kΩ 36kΩ 3 51kΩ +15V CA3140 + 4 - 7 6 100kΩ TO OUTPUT 2 AMPLIFIER CA3140 + 4 10kΩ GATE PULSE OUTPUT -15V 43kΩ -15V EXTERNAL OUTPUT TO FUNCTION GENERATOR “SWEEP IN” SWEEP WIDTH +15V 3 2 LOGVIO + CA3140 7 6 4 51kΩ 6.8kΩ 91kΩ 1 25kΩ 3.9Ω 5 10kΩ TRIANGLE 5 4 3 2 1 TRANSISTORS FROM CA3086 ARRAY SAWTOOTH “LOG” 100Ω -15V 390Ω FIGURE 13. SWEEPING GENERATOR 11 CA3140, CA3140A This circuit can be adjusted most easily with a distortion analyzer, but a good first approximation can be made by comparing the output signal with that of a sine wave generator. The initial slope is adjusted with the potentiometer R1, followed by an adjustment of R2. The final slope is established by adjusting R3, thereby adding additional segments that are contributed by these diodes. Because there is some interaction among these controls, repetition of the adjustment procedure may be necessary. Sweeping Generator Figure 13 shows a sweeping generator. Three CA3140s are used in this circuit. One CA3140 is used as an integrator, a second device is used as a hysteresis switch that determines the starting and stopping points of the sweep. A third CA3140 is used as a logarithmic shaping network for the log function. Rates and slopes, as well as sawtooth, triangle, and logarithmic sweeps are generated by this circuit. Wideband Output Amplifier Figure 14 shows a high slew rate, wideband amplifier suitable for use as a 50Ω transmission line driver. This circuit, when used in conjunction with the function generator and sine wave shaper circuits shown in Figures 10 and 12 provides 18VP-P output open circuited, or 9VP-P output when terminated in 50Ω. The slew rate required of this amplifier is 28V/µs (18VP-P x π x 0.5MHz). +15V SIGNAL LEVEL ADJUSTMENT 2.5kΩ 200Ω 3 2 REFERENCE VOLTAGE INPUT VOLTAGE ADJUSTMENT 3 + 7 6 REGULATED OUTPUT CA3140 2 - 4 FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR SHOWING VOLTAGE FOLLOWER CONFIGURATION Essentially, the regulators, shown in Figures 16 and 17, are connected as non inverting power operational amplifiers with a gain of 3.2. An 8V reference input yields a maximum output voltage slightly greater than 25V. As a voltage follower, when the reference input goes to 0V the output will be 0V. Because the offset voltage is also multiplied by the 3.2 gain factor, a potentiometer is needed to null the offset voltage. Series pass transistors with high ICBO levels will also prevent the output voltage from reaching zero because there is a finite voltage drop (VCESAT) across the output of the CA3140 (see Figure 2). This saturation voltage level may indeed set the lowest voltage obtainable. The high impedance presented by Terminal 8 is advantageous in effecting current limiting. Thus, only a small signal transistor is required for the current-limit sensing amplifier. Resistive decoupling is provided for this transistor to minimize damage to it or the CA3140 in the event of unusual input or output transients on the supply rail. Figures 16 and 17, show circuits in which a D2201 high speed diode is used for the current sensor. This diode was chosen for its slightly higher forward voltage drop characteristic, thus giving greater sensitivity. It must be emphasized that heat sinking of this diode is essential to minimize variation of the current trip point due to internal heating of the diode. That is, 1A at 1V forward drop represents one watt which can result in significant regenerative changes in the current trip point as the diode temperature rises. Placing the small signal reference amplifier in the proximity of the current sensing diode also helps minimize the variability in the trip level due to the negative temperature coefficient of the diode. In spite of those limitations, the current limiting point can easily be adjusted over the range from 10mA to 1A with a single adjustment potentiometer. If the temperature stability of the current limiting system is a serious consideration, the more usual current sampling resistor type of circuitry should be employed. A power Darlington transistor (in a metal can with heatsink), is used as the series pass element for the conventional current limiting system, Figure 16, because high power Darlington dissipation will be encountered at low output voltage and high currents. + 7 50µF 25V 2.2 kΩ 2N3053 + CA3140 1N914 6 1N914 2.7Ω 2.7Ω 51Ω 2W OUT 1 4 8 + OUTPUT DC LEVEL +15V ADJUSTMENT 3kΩ -15V 200Ω 50µF 25V 2.4pF 2pF 2.2 kΩ 2N4037 -15V 1.8kΩ NOMINAL BANDWIDTH = 10MHz tr = 35ns FIGURE 14. WIDEBAND OUTPUT AMPLIFIER Power Supplies High input impedance, common mode capability down to the negative supply and high output drive current capability are key factors in the design of wide range output voltage supplies that use a single input voltage to provide a regulated output voltage that can be adjusted from essentially 0V to 24V. Unlike many regulator systems using comparators having a bipolar transistor input stage, a high impedance reference voltage divider from a single supply can be used in connection with the CA3140 (see Figure 15). 12 CA3140, CA3140A A small heat sink VERSAWATT transistor is used as the series pass element in the fold back current system, Figure 17, since dissipation levels will only approach 10W. In this system, the D2201 diode is used for current sampling. Foldback is provided by the 3kΩ and 100kΩ divider network connected to the base of the current sensing transistor. Both regulators provide better than 0.02% load regulation. Because there is constant loop gain at all voltage settings, the 2N6385 CURRENT POWER DARLINGTON LIMITING ADJUST D2201 2 75Ω 3kΩ 100Ω 8 7 2 6 2.7kΩ 10µF INPUT 2.2kΩ 10 11 9 87 6 12 3 5 12 13 6 CA3086 1kΩ 62kΩ HUM AND NOISE OUTPUT