CA3162

® CA3162 A/D Converters for 3-Digit Display Description The CA3162E and CA3162AE are I2L monolithic A/D converters that provide a 3 digit multiplexed BCD output. They are used with the CA3161E BCD-to-Seven-Segment Decoder/Driver and a minimum of external parts to implement a complete 3-digit display. The CA3162AE is identical to the CA3162E except for an extended operating temperature range. The CA3161E is described in the Display Drivers section of this data book. April 2002 Features • Dual Slope A/D Conversion • Multiplexed BCD Display • Ultra Stable Internal Band Gap Voltage Reference • Capable of Reading 99mV Below Ground with Single Supply • Differential Input • Internal Timing - No External Clock Required • Choice of Low Speed (4Hz) or High Speed (96Hz) Conversion Rate • “Hold” Inhibits Conversion but Maintains Delay • Overrange Indication - “EEE” for Reading Greater than +999mV, “-” for Reading More Negative than -99mV When Used With CA3161E Ordering Information PART NUMBER CA3162E TEMP. RANGE ( oC) 0 to 70 PACKAGE 16 Ld PDIP PKG. NO. E16.3 Pinout CA3162 (PDIP) TOP VIEW BCD OUTPUTS 21 20 NSD 1 2 3 4 5 6 7 8 16 23 15 22 14 V+ BCD OUTPUTS DIGIT SELECT OUTPUTS MSD LSD 13 GAIN ADJ 12 INTEGRATING CAP HOLD/ BYPASS GND ZERO ADJ 11 HIGH INPUT 10 LOW INPUT 9 ZERO ADJ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved FN1080.3 1 CA3162 Functional Block Diagram V+ ZERO ADJ 8 9 V+ BCD OUTPUTS INTEGRATING CAP 12 21 1 20 2 22 15 23 16 V+ 14 3 CONTROL LOGIC COUNTERS AND MULTIPLEX DIGIT DRIVE 4 5 4 THRESHOLD DET. 5 = MSD = LSD = NSD DIGIT SELECT OUTPUTS † HIGH INPUT 11 LOW INPUT 10 V/I CONVERTER ÷2048 ÷96 3 REFERENCE CURRENT GENERATOR BAND GAP REFERENCE OSC HOLD/ BYPASS GATES 6 CONVERSION CONTROL 13 7 GND † MSD = MOST SIGNIFICANT DIGIT NSD = NEXT SIGNIFICANT DIGIT LSD = LEAST SIGNIFICANT DIGIT GAIN ADJ 2 CA3162 Absolute Maximum Ratings DC Supply Voltage (Between Pins 7 and 14) . . . . . . . . . . . . . . . +7V Input Voltage (Pin 10 or 11 to Ground) . . . . . . . . . . . . . . . . . . . ±15V Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) Operating Conditions Temperature Range CA3162E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.. Electrical Specifications PARAMETER TA = 25oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4kΩ , Unless Otherwise Specified TEST CONDITIONS MIN 4.5 100kΩ to V+ on Pins 3, 4, 5 Pins 10 and 11 V11-V10 = 0V, Read Decoded Output V11-V10 = 900mV, Read Decoded Output Notes 1 and 2 -12 846 -1 TYP 5 100 -80 MAX 5.5 17 +12 954 +1 UNITS V mA MΩ nA mV mV Count Operating Supply Voltage Range, V+ Supply Current, I+ Input Impedance, ZI Input Bias Current, IIB Unadjusted Zero Offset Unadjusted Gain Linearity Conversion Rate Slow Mode Fast Mode Conversion Control Voltage (Hold Mode) at Pin 6 Common Mode Input Voltage Range, VICR BCD Sink Current at Pins 1, 2, 15, 16 Digit Select Sink Current at Pins 3, 4, 5 Zero Temperature Coefficient Gain Temperature Coefficient NOTES: Notes 3, 4 VBCD ≥ 0.5V, at Logic Zero State VDIGIT Select = 4V at Logic Zero State VI = 0V, Zero Pot Centered VI = 900mV, Gain Pot = 2.4kΩ Pin 6 = Open or GND Pin 6 = 5V 0.8 4 96 1.2 1.6 Hz Hz V -0.2 0.4 1.6 - 1.6 2.5 10 0.005 +0.2 - V mA mA µV/oV %/oC 1. Apply 0V across V11 to V10 . Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to give 900mV reading. 2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include ±0.5 count bit digitizing error. 3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100kΩ resistance must be provided for input bias currents. 4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is, pin 11 may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input signal is less than 999mV, the common mode input voltage may be raised accordingly. 3 CA3162 Timing Diagram 12 5 (LSD) PIN NUMBER 200mV 500mV reference constant current source of opposite polarity is connected. The number of clock counts that elapse before the charge is restored to its original value is a direct measure of the signal induced current. The restoration is sensed by the comparator, which in turn latches the counter. The count is then multiplexed to the BCD outputs. The timing for the CA3162E is supplied by a 786Hz ring oscillator, and the input at pin 6 determines the sampling rate. A 5V input provides a high speed sampling rate (96Hz), and grounding or floating pin 6 provides a low speed (4Hz) sampling rate. When pin 6 is fixed at +1.2V (by placing a 12K resistor between pin 6 and the +5V supply) a “hold” feature is available. While the CA3162E is in the hold mode, sampling continues at 4Hz but the display data are latched to the last reading prior to the application of the 1.2V. Removal of the 1.2V restores continuous display changes. Note, however, that the sampling rate remains at 4Hz. Figure 1 shows the timing of sampling and digit select pulses for the high speed mode. Note that the basic A/D conversion process requires approximately 5ms in both modes. The “EEE” or “---” displays indicate that the range of the system has been exceeded in the positive or negative direction, respectively. Negative voltages to -99mV are displayed with the minus sign in the MSD. The BCD code is 1010 for a negative overrange (---) and 1011 for a positive overrange (EEE). 4 (MSD) 500mV 3 (NSD) 500mV 2ms/DIV. FIGURE 1. HIGH SPEED MODE Detailed Description The Functional Block Diagram of the CA3162E shows the V/I converter and reference current generator, which is the heart of the system. The V/I converter converts the input voltage applied between pins 10 and 11 to a current that charges the integrating capacitor on pin 12 for a predetermined time interval. At the end of the charging interval, the V/I converter is disconnected from the integrating capacitor, and a band gap NOTE 1 0.27µF NOTE 2 +5V 0.1 µF NORMAL 8 LOW SPEED MODE: V6 = GROUND OR OPEN HOLD: V6 = 1.2V 6 9 12 14 16 MSD NSD COMMON ANODE LED DISPLAYS LSD POWER 2N2907, 2N3906 OR EQUIV. a 5 3 4 a b f g c e d c e b f a b g c d f g e d 13 CA3161E 12 11 10 9 15 14 8 3 HIGH SPEED MODE: V6 = 5V CA3162E DIGIT DRIVERS BCD OUTPUTS 11 HIGH INPUTS LOW 10 13 GAIN ADJ 10 kΩ 7 16 15 1 2 6 2 1 7 R1 150Ω CA3162E PINS 3, 4, 5 1kΩ DIGIT DRIVER CA3162E PINS 1, 2, 15, 16 75Ω R2 150Ω R3 150Ω NOTES: 1. The capacitor used here must be a low dielectric absorption type such as a polyester or polystyrene type. 2. This capacitor should be placed as close as possible to the power and ground Pins of the CA3161E. BCD SEGMENT DRIVERS FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E 4 CA3162 CA3162E Liquid Crystal Display (LCD) Application Figure 3 shows the CA3162E in a typical LCD application. LCDs may be used in favor of LED displays in applications requiring lower power dissipation, such as battery-operated equipment, or when visibility in high-ambient-light conditions is desired. Multiplexing of LCD digits is not practical, since LCDs must be driven by an AC signal and the average voltage across each segment is zero. Three CD4056B liquid-crystal decoder/drivers are therefore used. Each CD4056B contains an input latch so that the BCD data for each digit may be latched into the decoder using the inverted digit-select outputs of the CA3162E as strobes. The capacitors on the outputs of inverters G3 and G4 filter out the decode spikes on the MSD and NSD signals. The capacitors and pull-up resistors connected to the MSD, NSD and LSD outputs are there to shorten the digit drive signal thereby providing proper timing for the CD4056B latches. Inverters G1 and G2 are used as an astable multivibrator to provide the AC drive to the LCD backplane. Inverters G3, G4 and G5 are the digit-select inverters and require pull-up resistors to interface the open-collector outputs of the CA3162E to CMOS logic. The BCD outputs of the CA3162E may be connected directly to the corresponding CD4056B inputs (using pull-up resistors). In this arrangement, the CD4056B decodes the negative sign (-) as an “L” and the positive overload indicator (E) as an “H”. The circuit as shown in Figure 3 using G7, G8 and G9 will decode the negative sign (-) as a negative sign (-), and the positive overload indicator (E) as “H”. +5V 0.047µF G3 0.047µF +5V 1 6 4 2 3 57 6x 10kΩ 0.27µF ZERO 50k Ω 8 14 9 CA3162E “HOLD” VIN+ VIN11 10 13 GAIN 10kΩ +5V G7 G1 - G6: CD4049UB HEX INVERTER G7, G8, G9: CD4023B TRIPLE 3 INPUT NAND GATE G8 G9 12 4 3 5 16 15 1 2 MSD NSD LSD 23 22 21 20 0.047 µF 0.047 µF G4 0.047 µF 1 6 4 2 3 57 8 CD4056B TO NSD OF LCD +5V 16 8 CD4056B TO MSD OF LCD 16 4x 7 100kΩ +5V G5 1 6 4 2 3 57 8 TO LCD BACKPLANE CD4056B TO LSD OF LCD 16 15k Ω 100kΩ 0.63µF FIGURE 3. TYPICAL LCD APPLICATION 5 CA3162 CA3162E Common-Cathode, LED Display Application Figure 4 shows the CA3162E connected to a CD4511B decode/driver to operate a common-cathode LED display. Unlike the CA3161E, the CD4511B remains blank for all BCD codes greater than nine. After 999mV the display blanks rather than displaying EEE, as with the CA3161E. When displaying negative voltage, the first digit remains blank, instead of (-), and during a negative or positive overrange the display blanks. The additional logic shown within the dotted area of Figure 4 restores the negative sign (-), allowing the display of negative numbers as low as -99mV. Negative overrange is indicated by a negative sign (-) in the MSD position. The rest of the display is blanked. During a positive overrange, only segment b of the MSD is displayed. One inverter from the CD4049B is used to operate the decimal points. By connecting the inverter input to either the MSD or NSD line either DP1 or DP2 will be displayed. V+ DP1 100kΩ 22k Ω 1/ 3 1/ CD4049UB 6 DP2 CD4049UB CD4012B 1/ 3 CD4049UB 1/ CD4049UB 6 V+ 1B CD4511B 2C 100k Ω V+ 100kΩ 100kΩ 100kΩ 3 LT 4 BL V+ 16 1.8k Ω 1.2k Ω 1.8k Ω 1.2k Ω 1.8k Ω 1.8k Ω 1.8k Ω 12 11 10 9 8 7 f 15 g 14 a 13 HP5082-7433 OR EQUIVALENT 5 LE/STROBE b 12 6D 7A 8 GND c 11 d 10 e9 f a g b c3 V+ DP1 1B 100 kΩ 100 kΩ 100 kΩ 2A 3 NSD 4 MSD 5 LSD 6 HOLD 7 GND 8 ZERO CA3162E D 16 C 15 V+ 14 GAIN 13 INT 12 HIGH 11 LOW 10 ZERO 9 V+ 50kΩ INPUT 6 BUFFERS (1 CD4050B) V+ 0.27µF DP2 c1 1 2 e d 3 c2 4 c 5 dP 6 10kΩ GAIN FIGURE 4. TYPICAL COMMON-CATHODE LED APPLICATION 6 CA3162 Die Characteristics DIE DIMENSIONS: 101 mils x 124 mils x 20 mils ±1 mil METALLIZATION: Type: Al Thickness: 17.5kÅ ±2.5kÅ PASSIVATION: Type: 3% PSG Thickness: 13kÅ ±2.5kÅ Metallization Mask Layout CA3162 LOW INPUT ZERO ADJ ZERO ADJ HIGH INPUT INTEGRATING CAP HOLD/BYPASS LSD GND MSD GAIN ADJ 21 V+ 20 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 NSD 22 23