CA3318CE

® November 2002 DUCT CT E P RO RO D U SOLET BSTITUTE P ter at OB LE S U o r t Ce n POSSIB chnical Supp rsil.com/tsc RA e e FO ww.int t our T contac TERSIL or w IN 1-888- CA3318 CMOS Video Speed, 8-Bit, Flash A/D Converter Features • CMOS Low Power with SOS Speed (Typ) . . . . . . . .150mW • Parallel Conversion Technique • 15MHz Sampling Rate (Conversion Time) . . . . . . . 67ns • 8-Bit Latched Three-State Output with Overflow Bit • Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB • Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V • 2 Units in Series Allow 9-Bit Output • 2 Units in Parallel Allow 30MHz Sampling Rate Description The CA3318 is a CMOS parallel (FLASH) analog-to-digital converter designed for applications demanding both low power consumption and high speed digitization. The CA3318 operates over a wide full scale input voltage range of 4V up to 7.5V with maximum power consumption depending upon the clock frequency selected. When operated from a 5V supply at a clock frequency of 15MHz, the typical power consumption of the CA3318 is 150mW. The intrinsic high conversion rate makes the CA3318 ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3318s in series to increase the resolution of the conversion system. A series connection of two CA3318s may be used to produce a 9-bit high speed converter. Operation of two CA3318s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz). 256 paralleled auto balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3318. 255 comparators are required to quantize all input voltage levels in this 8-bit converter, and the additional comparator is required for the overflow bit. Applications • • • • • • • • • • TV Video Digitizing (Industrial/Security/Broadcast) High Speed A/D Conversion Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research General-Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis µP Data Acquisition Systems Part Number Information PART NUMBER LINEARITY (INL, DNL) CA3318CE CA3318CM CA3318CD ±1.5 LSB ±1.5 LSB ±1.5 LSB SAMPLING RATE 15MHz (67ns) 15MHz (67ns) 15MHz (67ns) TEMP. RANGE (oC) -40 to 85 -40 to 85 -40 to 85 PACKAGE 24 Ld PDIP 24 Ld SOIC 24 Ld SBDIP PKG. NO. E24.6 M24.3 D24.6 Pinout CA3318 (PDIP, SBDIP, SOIC) TOP VIEW (LSB) B1 1 B2 2 B3 3 B4 4 B5 5 B6 6 B7 7 (MSB) B8 8 OVERFLOW 9 1/ R 10 4 24 VAA + (ANA. SUP.) 23 3/4R 22 VREF + 21 VIN 20 p 19 PHASE 18 CLK 17 VAA - (ANA. GND) 16 VIN 15 VREF 14 CE1 13 CE2 (DIG. GND) VSS 11 (DIG. SUP.) VDD 12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners. FN3103.3 1 CA3318 Functional Block Diagram VAA+ 24 VIN 21 VREF + 1 /2 R 22 CAB # 256 R = 2Ω LATCH 256 LATCH 256 ENCODER LOGIC ARRAY D Q D Q COUNT 256 ANALOG SUPPLY φ2 φ1 φ1 φ1 φ1 φ2 φ1 VDD DIGITAL SUPPLY 12 THREESTATE OUTPUT REGISTER DRIVERS OVERFLOW DQ CLK BIT 8 (MSB) DQ CLK BIT 7 DQ CLK 7 8 9 3/ REF 4 R D CAB # 193 LATCH LATCH Q D Q COUNT 193 23 = 7Ω R BIT 6 DQ 6 COUNT 129 1/ REF 2 R CAB # 129 R CLK BIT 5 DQ 5 D Q D Q 20 = 30Ω LATCH LATCH CLK BIT 4 1/ REF 4 R D CAB # 65 R LATCH LATCH Q D Q COUNT 65 DQ CLK 4 10 = 4Ω VIN 16 R VREF 15 BIT 3 DQ CLK COUNT 1 DQ CLK LATCH 1 LATCH 11 DQ BIT 1 (LSB) 1 BIT 2 2 3 ≅ 2K 1/ R 2 D CAB (NOTE 1) COMPARATOR #1 Q D Q ≅ 50K CLOCK 18 PHASE 19 VAA17 φ1 (AUTO BALANCE) CLK φ2 (SAMPLE UNKNOWN) CE1 14 ANALOG GND CE2 NOTE: 1. Cascaded Auto Balance (CAB). DIGITAL GND 13 VSS 11 2 CA3318 Absolute Maximum Ratings DC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V (Referenced to VSS or VAA- Terminal, Whichever is More Negative) Input Voltage Range CE2 and CE1 . . . . . . . . . . . . . . . . . . . . VAA- -0.5V to VDD + 0.5V Clock, Phase, VREF -, 1/2 Ref . . . . . . . VAA- -0.5V to VAA+ + 0.5V Clock, Phase, VREF -, 1/4 Ref . . . . . . . . VSS- -0.5V to VDD + 0.5V VIN , 3/4 REF, VREF + . . . . . . . . . . . . . .VAA- -0.5V to VAA- + 7.5V Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V Bits 1-8, Overflow (Outputs Off) DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Clock, Phase, CE1, CE2, VIN , Bits 1-8, Overflow Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . . . 60 22 PDIP Package . . . . . . . . . . . . . . . . . . . . . 60 N/A SOIC Package. . . . . . . . . . . . . . . . . . . . . 75 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 265oC (SOIC - Lead Tips Only) Operating Conditions Operating Voltage Range (VDD or VAA+) . . 4V (Min) to 7.5V (Max) Recommended VAA + Operating Range. . . . . . . . . . . . . . . VDD ±1V Recommended VAA - Operating Range . . . . . . . . . . . . . . . VSS ±1V Operating Temperature Range (TA). . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error Differential Linearity Error Offset Error, Unadjusted Gain Error Unadjusted DYNAMIC CHARACTERISTICS Maximum Input Bandwidth Maximum Conversion Speed Signal to Noise Ratio (SNR) RMSSignal = -------------------------------RMSNoise Signal to Noise Ratio (SINAD) RMSSignal = ----------------------------------------------------------RMSNoise+Distortion Total Harmonic Distortion, THD Effective Number of Bits (ENOB) Differential Gain Error Differential Phase Error ANALOG INPUTS At 25oC, VAA+ = VDD = 5V, VREF + = 6.4V, VREF - = VAA- = VSS , CLK = 15MHz, All Reference Points Adjusted, Unless Otherwise Specified TEST CONDITIONS MIN 8 VIN = VREF- + 1/2 LSB VIN = VREF+ - 1/2 LSB (Note 1) CA3318 CLK = Square Wave fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 4MHz fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 4MHz fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 4MHz fS = 15MHz, fIN = 100kHz fS = 15MHz, fIN = 4MHz Unadjusted Unadjusted Notes 2, 4 VIN = 5V, VREF+ = 5V -0.5 -1.5 TYP 4.5 0 MAX ± 1.5 +1, -0.8 6.4 1.5 UNITS Bits LSB LSB LSB LSB 2.5 15 4 270 5.0 17 47 43 45 35 -46 -36 7.2 5.5 2 1 30 500 7 3.5 800 MHz MSPS dB dB dB dB dBc dBc Bits Bits % % V pF mA Ω Full Scale Range, VIN and (VREF+) - (VREF -) Input Capacitance, VIN Input Current, VIN , (See Text) REFERENCE INPUTS Ladder Impedance 3 CA3318 Electrical Specifications PARAMETER DIGITAL INPUTS Low Level Input Voltage, VOL CE1, CE2 Phase, CLK High Level Input Voltage, VIN CE1, CE2 Phase, CLK Input Leakage Current, II (Except CLK Input) Input Capacitance, CI DIGITAL OUTPUTS Output Low (Sink) Current Output High (Source) Current Three-State Output Off-State Leakage Current, IOZ Output Capacitance, CO TIMING CHARACTERISTICS Auto Balance Time (φ1) Sample Time (φ2) Aperture Delay Aperture Jitter Data Valid Time, tD Data Hold Time, tH Output Enable Time, tEN Output Disable Time, tDIS POWER SUPPLY CHARACTERISTICS Device Current (IDD + IA) (Excludes IREF) Continuous Conversion (Note 4) Auto Balance (φ1) 30 30 60 60 mA mA Note 4 Note 4 Note 4 33 25 25 15 100 50 40 18 18 VO = 0.4V VO = 4.5V 4 -4 10 -6 ±0.2 4 ±5 mA mA µA pF ns ns ns ps ns ns ns ns Note 4 Note 4 Note 4 Note 4 Note 3 0.7VDD 0.7VAA ±0.2 3 0.2VDD 0.2VAA ±5 V V V V µA pF At 25oC, VAA+ = VDD = 5V, VREF + = 6.4V, VREF - = VAA- = VSS , CLK = 15MHz, All Reference Points Adjusted, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS ∞ 500 65 - NOTES: 1. A full scale sine wave input of greater than fCLOCK/2 or the specified input bandwidth (whichever is less) may cause an erroneous code. The -3dB bandwidth for frequency response purposes is greater than 30MHz. 2. VIN (Full Scale) or VREF+ should not exceed VAA+ + 1.5V for accuracy. 3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1VP-P minimum source. 4. Parameter not tested, but guaranteed by design or characterization. Timing Waveforms DECODED DATA IS SHIFTED TO OUTPUT REGISTERS COMPARATOR DATA IS LATCHED CLOCK (PIN 18) IF PHASE (PIN 19) IS LOW φ2 φ1 φ2 φ1 φ2 CLOCK IF PHASE IS HIGH SAMPLE N AUTO BALANCE SAMPLE N+1 AUTO BALANCE tD tH SAMPLE N+2 DATA N-2 DATA N-1 DATA N FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM 4 CA3318 Timing Waveforms (Continued) CE1 CE2 tDIS tEN tDIS BITS 1 - 8 DATA HIGH IMPEDANCE OF DATA HIGH IMPEDANCE DATA HIGH IMPEDANCE tEN DATA FIGURE 2. OUTPUT ENABLE TIMING DIAGRAM AUTO BALANCE CLOCK NO MAX LIMIT SAMPLE N 25ns MIN AUTO BALANCE SAMPLE N+1 33ns MIN 25ns MIN 50ns MIN DATA FIGURE 3A. STANDBY IN INDEFINITE AUTO BALANCE (SHOWN WITH PHASE = LOW) CLOCK SAMPLE N 500ns MAX AUTO BALANCE SAMPLE N+1 25ns MIN AUTO BALANCE SAMPLE N+2 33ns MIN 50ns TYP DATA DATA N-1 DATA N FIGURE 3B. STANDBY IN SAMPLE (SHOWN WITH PHASE = LOW) FIGURE 3. PULSE MODE OPERATION 5 CA3318 Typical Performance Curves 40 28 35 27 30 IDD (mA) IDD (mA) 0 10 fS (MHz) 20 30 26 25 25 20 24 15 10 23 -50 -25 25 0 50 TEMPERATURE (oC) 75 100 FIGURE 4. DEVICE CURRENT vs SAMPLE FREQUENCY FIGURE 5. DEVICE CURRENT vs TEMPERATURE 8.0 7.8 7.6 7.4 ENOB (LSB) 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 NON-LINEARITY (LSB) fS = 15MHz, fI = 1MHz 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 DNL INL fS = 15MHz TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 6. ENOB vs TEMPERATURE FIGURE 7. NON-LINEARITY vs TEMPERATURE 1.20 1.08 0.96 NON-LINEARITY (LSB) NON-LINEARITY (LSB) 0.84 0.72 0.60 0.48 0.36 0.24 0.12 0 0 5 10 fS (MHz) 15 20 25 DNL INL 1.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 0 1 2 4 3 VREF (V) 5 6 7 DNL INL fS = 15MHz FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY FIGURE 9. NON-LINEARITY vs REFERENCE VOLTAGE 6 CA3318 Typical Performance Curves 8.0 7.6 7.2 6.8 ENOB (LSB) 6.4 6.0 5.6 5.2 4.8 4.4 4.0 0.0 0.5 1.0 1.5 2.0 2.5 fI (MHz) 3.0 3.5 4.0 4.5 5.0 fS = 15MHz (Continued) FIGURE 10. ENOB vs INPUT FREQUENCY Pin Descriptions PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NAME B1 B2 B3 B4 B5 B6 B7 B8 OF 1/ R 4 CHIP ENABLE TRUTH TABLE DESCRIPTION Bit 1 (LSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 (MSB) Overflow Reference Ladder 1/4 Point Digital Ground Digital Power Supply, +5V Three-State Output Enable Input, Active Low, See Truth Table. Three-State Output Enable Input Active High. See Truth Table. Reference Voltage Negative Input Analog Signal Input Analog Ground Clock Input Sample clock phase control input. When PHASE is low, “Sample Unknown” occurs when the clock is low and “Auto Balance” occurs when the clock is high (see text). Reference Ladder Midpoint Analog Signal Input Reference Voltage Positive Input Reference Ladder 3/4 Point Analog Power Supply, +5V Output Data Bits (High = True) CE1 0 1 X X = Don’t Care CE2 1 1 0 B1 - B8 Valid Three-State Three-State OF Valid Valid Three-State Theory of Operation A sequential parallel technique is used by the CA3318 converter to obtain its high speed operation. The sequence consists of the “Auto-Balance” phase, φ1, and the “Sample Unknown” phase, φ2. (Refer to the circuit diagram.) Each conversion takes one clock cycle (see Note). With the phase control (pin 19) high, the “Auto-Balance” (φ1) occurs during the high period of the clock cycle, and the “Sample Unknown” (φ2) occurs during the low period of the clock cycle. NOTE: The device requires only a single phase clock The terminology of φ1 and φ2 refers to the high and low periods of the same clock. VSS VDD CE2 CE1 VREF VIN VAACLK PHASE During the “Auto-Balance” phase, a transmission switch is used to connect each of the first set of 256 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: VTAP (N) = [(N/256) VREF] - (1/512) VREF] = [(2N - 1)/512] VREF , Where: VTAP (n) = reference ladder tap voltage at point n, VREF N = voltage across VREF - to VREF +, = tap number (1 through 256). 20 21 22 23 24 1/ R 2 VIN VREF+ 3/ R 4 VAA+ The other side of these capacitors are connected to singlestage amplifiers whose outputs are shorted to their inputs by switches. This balances the amplifiers at their intrinsic trip points, which is approximately (VAA+ - VAA-)/2. The first set of capacitors now charges to their associated tap voltages. 7 CA3318 At the same time a second set of commutating capacitors and amplifiers is also auto-balanced. The balancing of the second-stage amplifier at its intrinsic trip point removes any tracking differences between the first and second amplifier stages. The cascaded auto-balance (CAB) technique, used here, increases comparator sensitivity and temperature tracking. In the “Sample Unknown” phase, all ladder tap switches and comparator shorting switches are opened. At the same time VlN is switched to the first set of commutating capacitors. Since the other end of the capacitors are now looking into an effectively open circuit, any input voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators that had tap voltages greater than VlN will go to a “high” state at their outputs. All comparators that had tap voltages lower than VlN will go to a “low” state. The status of all these comparator amplifiers is AC coupled through the second-stage comparator and stored at the end of this phase (φ2) by a latching amplifier stage. The latch feeds a second latching stage, triggered at the end of φ1. This delay allows comparators extra settling time. The status of the comparators is decoded by a 256 to 9-bit decoder array, and the results are clocked into a storage register at the end of the next φ2. A 3-stage buffer is used at the output of the 9 storage registers which are controlled by two chip-enable signals. CE1 will independently disable B1 through B6 when it is in a high state. CE2 will independently disable B1 through B8 and the OF buffers when it is in the low state. To facilitate usage of this device, a phase control input is provided which can effectively complement the clock as it enters the chip. Continuous-Clock Operation One complete conversion cycle can be traced through the CA3318 via the following steps. (Refer to timing diagram.) With the phase control in a “low” state, the rising edge of the clock input will start a “sample” phase. During this entire “high” state of the clock, the comparators will track the input voltage and the first-stage latches will track the comparator outputs. At the falling edge of the clock, all 256 comparator outputs are captured by the 256 latches. This ends the “sample” phase and starts the “auto-balance” phase for the comparators. During this “low” state of the clock, the output of the latches settles and is captured by a second row of latches when the clock returns high. The second-stage latch output propagates through the decode array, and a 9-bit code appears at the D inputs of the output registers. On the next falling edge of the clock, this 9-bit code is shifted into the output registers and appears with time delay tD as valid data at the output of the three-state drivers. This also marks the end of the next “sample” phase, thereby repeating the conversion process for this next cycle. Pulse-Mode Operation The CA3318 needs two of the same polarity clock edges to complete a conversion cycle: If, for instance, a negative going clock edge ends sample “N”, then data “N” will appear after the next negative going edge. Because of this requirement, and because there is a maximum sample time of 500ns (due to capacitor droop), most pulse or intermittent sample applications will require double clock pulsing. If an indefinite standby state is desired, standby should be in auto-balance, and the operation would be as in Figure 3A. If the standby state is known to last less than 500ns and lowest average power is desired, then operation could be as in Figure 3B. Increased Accuracy In most cases the accuracy of the CA3318 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, five adjustments can be made to obtain better accuracy, i.e., offset trim; gain trim; and 1/4 , 1/2 and 3/4 point trim. Offset Trim In general, offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the op amp. When this is not possible the VREF - input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equation is as follows: VlN (0 to 1 transition) = 1/2 LSB = 1/2 (VREF/256) = VREF /512. If VlN for the first transition is less than the theoretical, then a single-turn 50Ω pot connected between VREF - and ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0-to-1 transition occurs. If VlN for the first transition is greater than the theoretical, then the 50Ω pot should be connected between VREF - and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim In general, the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the op amp. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VlN should be set to the 255 to overflow transition. That voltage is 1/3 LSB less than VREF + and is calculated as follows: VlN (255 to 256 transition) = VREF - VREF /512 = VREF(511/512). To perform the gain trim, first do the offset trim and then apply the required VlN for the 255 to overflow transition. Now adjust VREF + until that transition occurs on the outputs. 8 CA3318 +10V TO 30V INPUT 3 CA3085E 6 4 7 2 1 8 (NOTE) 5K IOT + 18Ω VREF+ (PIN 22) + 4.7µF, TAN/IOV The first step for connecting a 9-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 13. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. The overflow output of the lower device now becomes the ninth bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overtlow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The threestate outputs of the two devices (bits 1 through 8) are now connected in parallel to complete the circuitry. The complete circuit for a 9-bit A/D converter is shown in Figure 13. Grounding/Bypassing The analog and digital supply grounds of a system should be kept separate and only connected at the A/D. This keeps digital ground noise out of the analog data to be converted. Reference drivers, input amps, reference taps, and the VAA supply should be bypassed at the A/D to the analog side of the ground. See Figure 15 for a block diagram of this concept. All capacitors shown should be low impedance 0.1µF ceramics and should be mounted as close to the A/D as possible. If VAA+ is derived from VDD , a small (10Ω resistor or inductor and additional filtering (4.7µF tantalum) may be used to keep digital noise out of the analog system. Input Loading The CA3318 outputs a current pulse to the VlN terminal at the start of every sample period. This is due to capacitor charging and switch feedthrough and varies with input voltage and sampling rate. The signal source must be capable of recovering from the pulse before the end of the sample period to guarantee a valid signal for the A/D to convert. Suitable high speed amplifiers include the HA-5033, HA-2542; and CA3450. Figure 16 is an example of an amplifier which recovers fast enough for sampling at 15MHz. Output Loading CW 10µF, TAN (NOTE) 1.5K NOTE: Bypass VREF+ to analog GND near A/D with 0.1µF ceramic cap. Parts noted should have low temperature drift. FIGURE 11. TYPICAL VOLTAGE REFERENCE SOURCE FOR DRIVING VREF+ INPUT 1/ Point Trims 4 The 1/4 , 1/2 and 3/4 points on the reference ladder are brought out for linearity adjusting or if the user wishes to create a nonlinear transfer function. The 1/4 points can be driven by the reference drivers shown (Figure 12) or by 2-K pots connected between VREF + and VREF -. The 1/2 (mid-) point should be set first by applying an input of 257/512 x (VREF) and adjusting for an output changing from 128 to 129. Similarly the 1/4 and 3/4 points can be set with inputs of 129/512 and 385/512 x (VREF) and adjusting for counts of 192 to 193 and 64 to 65. (Note that the points are actually 1/ , 1/ and 3 / of full scale +1 LSB.) 4 2 4 VREF+ (PIN 22) 510Ω 1K IOT 3 CW 2 5 CW + 6 10 CW + 9 +10V TO +30V 4 11 + 1 10Ω 3/ REF 4 7 10Ω (PIN 23) 1K IOT 8 10Ω 1/ REF 2 (PIN 20) 1K IOT 510Ω - 1/ REF 4 (PIN 10) The CMOS digital output stage, although capable of driving large loads, will reflect these loads into the local ground. It is recommended that a local QMOS buffer such as CD74HC541 E be used to isolate capacitive loads. NOTES: 1. All Op Amps = 3/4 CA324E. 2. Bypass all reference points to analog ground near A/D with 0.1µF ceramic caps. 3. Adjust VREF+ first, then 1/3 , 3/4 and 1/4 points. FIGURE 12. TYPICAL 1/4 POINT DRIVERS FOR ADJUSTING LINEARITY (USE FOR MAXIMUM LINEARITY) Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from fullscale for all these tests. Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. 9-Bit Resolution To obtain 9-bit resolution, two CA3318s can be wired together. Necessary ingredients include an open-ended ladder network, an overflow indicator, three-state outputs, and chip-enable controls - all of which are available on the CA3318. 9 CA3318 Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + VCORR)/6.02, where: VCORR = 0.5dB. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. +6.4V REF +5V VREF+ VAA+ VAAA OF VDD BIT 8 NC +5V VIN1 0V TO 6.4V VIN VIN BIT 1 CL PH CE2 CE1 6.4V REF MID-POINT DRIVER VREF- VSS D A VREF+ VIN VIN VDD CE2 CE1 OF BIT 8 +5V BIT 9 BIT 8 BIT 1 +5V VAA+ VAAVREF A A CL PH VSS D BIT 1 CLOCK PHASE FIGURE 13. USING TWO CA3318s FOR 9-BIT RESOLUTION 10 CA3318 4.7µF/10V TANTALUM A + +5V (ANALOG SUPPLY) VAA+ 3/ REF 4 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 OVF 1/ REF 4 +4V TO +6.5V REFERENCE VREF+ VIN OPTIONAL CAP (SEE TEXT) 0.01µF 1/ REF 2 DIGITAL OUTPUT PHASE CLK VAA- CLOCK SOURCE INPUT SIGNAL AMPLIFIER/BUFFER (SEE TEXT) A D VIN VREFCE1 CE2 CA3318 VSS VDD + D 4.7µF TANTALUM/10V A +5V (DIGITAL SUPPLY) FIGURE 14. TYPICAL CIRCUIT CONFIGURATION FOR THE CA3318 WITH NO LINEARITY ADJUST AMP SIGNAL SOURCE REF VIN VIN VREF+ OUTPUT DRIVERS TO DIGITAL SYSTEM SIGNAL GROUND REFERENCE TAPS VAA+ VREF VAAVDD VSS SYSTEM DIGITAL GROUND - ANALOG + SUPPLIES VAA SUPPLY VDD SUPPLY FIGURE 15. TYPICAL SYSTEM GROUNDING/BYPASSING +8V 75Ω 1VP-P VIDEO INPUT 14 75Ω 5pF 11 9 3 4 5 7 10Ω 0.001µF 8 6 13 12 0.001µF 390 10Ω 16 21 A/D FLASH INPUT CA3450 10Ω 750 110 0V TO -10V OFFSET SOURCE RS < 10Ω NOTE: Ground-planing and tight layout are extremely important. -4V 0.1 FIGURE 16. TYPICAL HIGH BANDWIDTH AMPLIFIER FOR DRIVING THE CA3318 11 CA3318 TABLE 1. OUTPUT CODE TABLE (NOTE 1) INPUT VOLTAGE CODE DESCRIPTION Zero 1 LSB 2 LSB • • • 1/ Full Scale 4 BINARY OUTPUT CODE MSB B8 0 0 0 LSB B1 0 1 0 DECIMAL COUNT 0 1 2 • • • 0 0 0 0 64 • • • 1 0 0 1 0 0 1 0 0 1 0 1 127 128 129 • • • 0 0 0 0 192 • • • 1 1 1 1 1 1 1 1 1 0 1 1 254 255 511 VREF 6.40V (V) 0.00 0.025 0.05 • • • 1.60 • • • 3.175 3.20 3.225 • • • 4.80 • • • 6.35 6.375 6.40 VREF 5.12V (V) 0.00 0.02 0.04 • • • 1.28 • • • 2.54 2.56 2.58 • • • 3.84 • • • 5.08 5.10 5.12 OF 0 0 0 B7 0 0 0 B6 0 0 0 B5 0 0 0 • • • B4 0 0 0 B3 0 0 0 B2 0 0 1 0 0 1 0 0 • • • • • • 1/ Full Scale - 1 LSB 2 1/ Full Scale 2 1/ Full Scale + 1 LSB 2 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 • • • • • • 3/ Full Scale 4 0 1 1 0 0 • • • • • • Full Scale - 1 LSB Full Scale Over Flow 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. Reducing Power Most power is consumed while in the auto-balance state. When operating at lower than 15MHz clock speed, power can be reduced by stretching the sample (φ2) time. The constraints are a minimum balance time (φ1) of 33ns, and a maximum sample time of 500ns. Longer sample times cause droop in the auto-balance capacitors. Power can also be reduced in the reference string by switching the reference on only during auto-balance. Clock Input The Clock and Phase inputs feed buffers referenced to VAA+ and VAA-. Phase should be tied to one of these two potentials, while the clock (if DC coupled) should be driven at least from 0.2 to 0.7 x (VAA+ - VAA-). The clock may also be AC coupled with at least a 1VP-P swing. This allows TTL drive levels or 5V QMOS levels when VAA+ is greater than 5V. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. 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