CA3420A

CA3420, CA3420A TM Data Sheet April 2000 File Number 1320.6 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifiers The CA3420A and CA3420 are integrated circuit operational amplifiers that combine PMOS transistors and bipolar transistors on a single monolithic chip. The CA3420A and CA3420 BiMOS operational amplifiers feature gate protected PMOS transistors in the input circuit to provide very high input impedance, very low input currents (less than 1pA). The internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leakage current for every 10oC increase in temperature. The CA3420 series operates at total supply voltages from 2V to 20V either single or dual supply. These operational amplifiers are internally phase compensated to achieve stable operation in the unity gain follower configuration. Additionally, they have access terminals for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common mode input voltage capability down to 0.45V below the negative supply terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that can swing essentially from rail-to-rail. The output driving current of 1.5mA (Min) is provided by using nonlinear current mirrors. Features • 2V Supply at 300µA Supply Current • 1pA Input Current (Typ) (Essentially Constant to 85oC) • Rail-to-Rail Output Swing (Drive ±2mA into 1kΩ Load) • Pin Compatible with 741 Operational Amplifiers Applications • pH Probe Amplifiers • Picoammeters • Electrometer (High Z) Instruments • Portable Equipment • Inaccessible Field Equipment • Battery-Dependent Equipment (Medical and Military) Functional Diagram X1 MOS BIPOLAR Ordering Information PART NUMBER CA3420AT CA3420E TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 8 Pin Metal Can 8 Ld PDIP PKG. NO. T8.C E8.3 X1 + MOS BIPOLAR BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK HIGH GAIN (50K) OTA BUFFER (X2) Pinouts CA3420 (PDIP) TOP VIEW 1 2 3 4 8 STROBE CA3420 (METAL CAN) TOP VIEW TAB STROBE 7 V+ + 8 1 OFFSET NULL INV. INPUT NON-INV. INPUT V- OFFSET NULL INV. 2 INPUT + 7 V+ 6 OUTPUT 5 OFFSET NULL - 6 OUTPUT 5 OFFSET NULL NON-INV. 3 INPUT 4 V- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 CA3420, CA3420A Absolute Maximum Ratings Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 105 N/A Metal Can Package . . . . . . . . . . . . . . . 165 80 Maximum Junction Temperature (Metal Can Package). . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Resistance Input Capacitance Output Resistance Equivalent Input Noise Voltage Short-Circuit Current To Opposite Supply Gain Bandwidth Product Slew Rate Transient Response Current from Terminal 8 Typical Values Intended Only for Design Guidance, VSUPPLY = ±10V, TA = 25oC SYMBOL RI CI RO eN IOM+ IOMfT SR f = 1kHz f = 10kHz RS = 100Ω TEST CONDITIONS CA3420A 150 4.9 300 62 38 2.6 2.4 0.5 0.5 RL = 2kΩ, CL = 100pF 0.7 15 20 2 CA3420 150 4.9 300 62 38 2.6 2.4 0.5 0.5 0.7 15 20 2 UNITS TΩ pF Ω nV/√Hz nV/√Hz mA mA MHz V/µs µs % µA mA Source Sink Rise Time Overshoot To VTo V+ tR OS I8+ I8- Electrical Specifications PARAMETER Input Offset Voltage Input Offset Current (Note 3) Input Current (Note 3) Large Signal Voltage Gain Common Mode Rejection Ratio For Equipment Design, At VSUPPLY = ±1V, TA = 25oC, Unless Otherwise Specified SYMBOL |VIO| |IIO| |II| AOL CMRR VlCR+ VlCRPSRR VOM+ VOMI+ PD ∆VlO/∆T ∆VIO/∆V RL = ∞ RL = 10kΩ TEST CONDITIONS CA3420 MIN 10 80 55 0.2 60 0.90 -0.85 TYP 5 0.01 1 100 100 560 65 0.5 -1.3 100 80 0.95 -0.91 350 0.7 4 MAX 10 4 5 1800 1000 650 1.1 MIN 20 86 60 0.2 -1 70 0.90 -0.85 CA3420A TYP 2 0.01 0.02 100 100 560 65 0.5 -1.3 32 90 0.95 -0.91 350 0.7 4 MAX 5 4 5 1000 320 650 1.1 UNITS mV pA pA kV/V dB µV/V dB V V µV/V dB V V µA mW µV/oC Common Mode Input Voltage Range Power Supply Rejection Ratio Max Output Voltage Supply Current Device Dissipation Input Offset Voltage Temperature Drift NOTE: 3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. 2 CA3420, CA3420A Electrical Specifications PARAMETER Input Offset Voltage Input Offset Current (Note 4) Input Current (Note 4) Large Signal Voltage Gain Common Mode Rejection Ratio Common Mode Input Voltage Range Power Supply Rejection Ratio Max Output Voltage Supply Current Device Dissipation Input Offset Voltage Temperature Drift NOTE: 4. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. For Equipment Design, at VSUPPLY = ±10V, TA = 25oC, Unless Otherwise Specified SYMBOL |VIO| |IIO| |II| AOL CMRR VlCR+ VlCRPSRR VOM+ VOMI+ PD ∆VlO/∆T ∆VIO/∆V RL = ∞ RL = 10kΩ TEST CONDITIONS CA3420 MIN 10 80 70 8.5 -10 70 9.7 -9.7 TYP 5 0.03 0.05 100 100 100 80 9.3 -10.3 32 90 9.9 -9.85 450 9 4 MAX 10 4 5 320 320 1000 14 MIN 20 86 70 9.0 -10 70 9.7 -9.7 CA3420A TYP 2 0.03 0.05 100 100 100 80 9.3 -10.3 32 90 9.9 -9.85 450 9 4 MAX 5 4 5 320 320 1000 14 UNITS mV pA pA kV/V dB µV/V dB V V µV/V dB V V µA mW µV/oC Typical Applications Picoammeter Circuit The exceptionally low input current (typically 0.2pA) makes the CA3420 highly suited for use in a picoammeter circuit. With only a single 10GΩ resistor, this circuit covers the range from ±1.5pA. Higher current ranges are possible with suitable switching techniques and current scaling resistors. Input transient protection is provided by the 1MΩ resistor in series with the input. Higher current ranges require that this resistor be reduced. The 10MΩ resistor connected to pin 2 of the CA3420 decouples the potentially high input capacitance often associated with lower current circuits and reduces the tendency for the circuit to oscillate under these conditions. 1MΩ 10GΩ 10pF +1.5V 2 10MΩ CA3420 + 5 1 7 6 4 BATTERY RETURNS 500-0-500 µA M ±50pA ±15pA ±5pA -1.5V ±1.5pA 11kΩ 1.5kΩ 1.5kΩ, 1% 1kΩ 430Ω, 1% 150Ω, 1% 3 10kΩ 68Ω 1% High Input Resistance Voltmeter Advantage is taken of the high input impedance of the CA3420 in a high input resistance DC voltmeter. Only two 1.5V “AA” type penlite batteries power this exceedingly high-input resistance (>1,000,000MΩ) DC voltmeter. Full-scale deflection is ±500mV, ±150mV, and ±15mV. Higher voltage ranges are easily added with external input voltage attenuator networks. The meter is placed in series with the gain network, thus eliminating the meter temperature coefficient error term. Supply current in the standby position with the meter undeflected is 300µA. At full-scale deflection this current rises to 800µA. Carbon-zinc battery life should be in excess of 1,000 hours. FIGURE 1. PICOAMMETER CIRCUIT +1.5V 22MΩ 10MΩ 100pF 2 3 + CA3420 7 6 4 5 1 10kΩ BATTERY RETURNS 500-0-500 µA M ±500mV 1.5kΩ 1.5kΩ, 1% 1kΩ 430Ω, 1% - ±150mV ±50mV -1.5V ±15mV 150Ω, 1% 1.1kΩ 68Ω 1% FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER 3 CA3420, CA3420A Typical Performance Curves INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 5 10 15 SUPPLY VOLTAGE (V) VO+ VICRVICR+ VOTA = 25oC RL = 100kΩ OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q19 (mV) 10 TA = 25oC V- = 0V V+ = 2V V+ = 5V V+ = 10V V+ = 20V 100 1000 0.01 0.1 1 10 LOAD (SOURCING) CURRENT (mA) FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE 1000 OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q17 (mV) TA = 25oC V+ = 0V FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) 1000 VS = ±10V VS = ±5V VS = ±1V 100 TA = 25oC 100 V- = -20V V- = -10V V- = -5V V- = -2V 10 10 0.01 0.1 1 10 1 101 102 103 104 105 106 LOAD (SINKING) CURRENT (mA) FREQUENCY (Hz) FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT FIGURE 6. INPUT NOISE VOLTAGE vs FREQUENCY 100 OPEN LOOP VOLTAGE GAIN (dB) 0 -45 -90 80 60 -135 -180 40 20 0 1 101 102 103 104 105 106 FREQUENCY (Hz) FIGURE 7. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE 4 OPEN LOOP PHASE (DEGREES) TA = 25oC VS = ±5V RL = 10kΩ CL = 0pF CA3420, CA3420A Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 5 CA3420, CA3420A Metal Can Packages (Can) REFERENCE PLANE A L L2 L1 A A ØD ØD1 Øe 2 1 Øb1 Øb BASE AND SEATING PLANE BASE METAL LEAD FINISH β N k1 ØD2 T8.C MIL-STD-1835 MACY1-X8 (A1) e1 8 LEAD METAL CAN PACKAGE INCHES SYMBOL A Øb Øb1 Øb2 ØD MIN 0.165 0.016 0.016 0.016 0.335 0.305 0.110 MAX 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS MIN 4.19 0.41 0.41 0.41 8.51 7.75 2.79 MAX 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES 1 1 2 1 1 1 3 3 4 Rev. 0 5/18/94 α k ØD1 C L F Q ØD2 e e1 F k k1 0.200 BSC 0.100 BSC 0.027 0.027 0.500 0.250 0.010 45o BSC 45o BSC 8 0.040 0.034 0.045 0.750 0.050 0.045 - 5.08 BSC 2.54 BSC 1.02 0.86 1.14 19.05 1.27 1.14 0.69 0.69 12.70 6.35 0.25 Øb1 Øb2 L L1 SECTION A-A L2 Q NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. α β N 45o BSC 45o BSC 8 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6