CA5420A

® CA5420A Data Sheet December 8, 2009 FN1925.6 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifiers The CA5420A is an integrated circuit operational amplifier that combines PMOS transistors and bipolar transistors on a single monolithic chip. It is designed and guaranteed to operate in microprocessor logic systems that use V+ = 5V, V- = GND, since it can operate down to ±1V supplies. It will also be suitable for 3.3V logic systems. The CA5420A BiMOS operational amplifier features gateprotected PMOS transistors in the input circuit to provide very high input impedance, very low input currents (less than 1pA). The internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leakage current for every +10°C increase in temperature. The CA5420A operates at total supply voltages from 2V to 20V either single or dual supply. This operational amplifier is internally phase compensated to achieve stable operation in the unity gain follower configuration. Additionally, it has access terminals for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common-mode input voltage capability down to 0.45V below the negative supply terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that can swing essentially from rail-to-rail. The output driving current of 1.0mA (Min) is provided by using nonlinear current mirrors. This device has guaranteed specifications for 5V operation over the full military temperature range of -55°C to +125°C. The CA5420A has the same 8 lead pinout used for the industry standard 741. Features • CA5420A at 5V Supply Voltage with Full Military Temperature Range Guaranteed Specifications • CA5420A Guaranteed to Operate from ±1V to ±10V Supplies • 2V Supply at 300µA Supply Current • 1pA (Typ) Input Current (Essentially Constant to +85°C) • Rail-to-Rail Output Swing (Drive ±2mA Into 1kΩ Load) • Pin Compatible with 741 Op Amp • Pb-Free Available (RoHS Compliant) Applications • pH Probe Amplifiers • Picoammeters • Electrometer (High Z) Instruments • Portable Equipment • Inaccessible Field Equipment • Battery Dependent Equipment (Medical and Military) • 5V Logic Systems • Microprocessor Interface Functional Diagram X1 MOS BIPOLAR + - MOS BIPOLAR X1 BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK HIGH GAIN (50k) OTA BUFFER (X2) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA5420A Ordering Information PART NUMBER (Note 3) CA5420AM CA5420AMZ (Notes 1, 2) NOTES: 1. Add “96” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for CA5420A. For more information on MSL please see techbrief TB363. 5420A 5420 AMZ PART MARKING TEMP. RANGE (°C) -55 to +125 -55 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC (Tape and Reel) PKG. DWG. # M8.15 M8.15 Pinout CA5420A (8 LD SOIC) TOP VIEW OFFSET 1 NULL INV. 2 INPUT NON-INV. 3 INPUT V- 4 8 STROBE + 7 V+ 6 OUTPUT 5 OFFSET NULL NOTE: Pin is connected to Case. 2 FN1925.6 December 8, 2009 CA5420A Absolute Maximun Ratings Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 22V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 4). . . . . . . . . . . . . . . . Indefinite Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Thermal Information Thermal Resistance (Typical, Note 5) θJA (°C/W) θJC (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . 157 N/A Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range (All Types) . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Short circuit may be applied to ground or to either supply. 5. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Resistance Input Capacitance Output Resistance Equivalent Input Noise Voltage Short-Circuit Current To Opposite Supply Gain Bandwidth Product Slew Rate Transient Response Typical Values Intended Only for Design Guidance. V+ = +5V; V- = GND, TA = +25°C SYMBOL RI CI RO eN f = 1kHz f = 10kHz Source Sink IOM+ IOMfT SR Rise Time Overshoot tr OS I8 + I80.01% 0.10% AV = 1 AV = 1 2VP-P Input 2VP-P Input RL = 2kΩ, CL = 100pF RS = 100Ω TEST CONDITIONS CA5420A 150 4.9 300 62 38 2.6 2.4 0.5 0.5 0.7 15 20 2 8 4.5 UNITS TΩ pF Ω nV/√Hz nV/√Hz mA mA MHz V/µs µs % µA mA µs µs Current from Terminal 8 To VCurrent from Terminal 8 To V+ Settling Time + Electrical Specifications PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified TEST CONDITIONS VO = 2.5V VO = 2.5V VO = 2.5V VCM = 0 to 3.7V, VO = 2.5V VO = 2.5V ΔV+ = 1V; ΔV- = 1V RL = ∞ RL = 10kΩ RL = 2kΩ ISOURCE ISINK V O = 0V V O = 5V CA5420A MIN 75 3.7 75 TYP 1 0.02 0.02 83 4 -0.3 83 MAX 5 4 5 0 UNITS mV pA pA dB V V dB SYMBOL VIO IIO II CMRR VlCR+ VlCR- Common Mode Input Voltage Range Power Supply Rejection Ratio Large Signal Voltage Gain VO = 0.5 to 4V VO = 0.5 to 4V VO = 0.7 to 3V Source Current Sink Current PSRR AOL 85 85 80 1.2 1.2 87 87 85 2.7 2.1 - dB dB dB mA mA 3 FN1925.6 December 8, 2009 CA5420A Electrical Specifications PARAMETER Output Voltage TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified (Continued) TEST CONDITIONS RL = ∞ RL = 10kΩ RL = 2kΩ CA5420A MIN 4.85 4.7 3.5 V O = 0V VO = 2.5V TYP 4.94 0.13 4.9 0.12 4.6 0.1 400 430 MAX 0.15 0.15 0.15 500 550 UNITS V V V V V V µA µA SYMBOL VOM+ VOMVOM+ VOMVOM+ VOM- Supply Current ISUPPLY Electrical Specifications TA = -55°C to +125°C, V+ = 5V, V- = 0, Unless Otherwise Specified CA5420A PARAMETER Input Offset Voltage Input Offset Current Up to TA = +85°C Input Current Up to TA = +85°C Common Mode Rejection Ratio Common Mode Input Voltage Range SYMBOL VIO IIO |II| TEST CONDITIONS VO = 2.5V VO = 2.5V MIN (Note 6) - TYP 2 1.5 2 2 10 80 4 -0.3 83 MAX (Note 6) 10 3 10 5 15 0 - UNITS mV nA pA nA pA dB V V dB VO = 2.5V - CMRR VlCR+ VlCR- VCM = 0 to 3.7V, VO = 2.5V VO = 2.5V ΔV+ = 1V; ΔV- = 1V RL = ∞ RL = 10kΩ R L = 2k Ω 70 3.7 70 Power Supply Rejection Ratio Large Signal Voltage Gain VO = 0.5 to 4V VO = 0.7 to 4V VO = 0.7 to 2.5V Source Current Sink Current Output Voltage PSRR AOL 65 80 75 1 1 4.8 - 75 87 80 2.7 2.1 4.9 0.16 4.9 0.15 4 0.14 430 480 0.2 0.2 0.2 550 600 dB dB dB mA mA V V V V V V µA µA ISOURCE ISINK VOM+ VOMVOM+ VOMVOM+ VOM- V O = 0V V O = 5V RL = ∞ RL = 10kΩ R L = 2k Ω 4.7 3 - Supply Current ISUPPLY V O = 0V VO = 2.5V - 4 FN1925.6 December 8, 2009 CA5420A Electrical Specifications PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain For Equipment Design at VSUPPLY = ±1V, TA = +25°C, Unless Otherwise Specified TEST CONDITIONS CA5420A MIN RL = 10kΩ 10 80 Common Mode Rejection Ratio CMRR 60 Common Mode Input Voltage Range VlCR+ VlCRPower Supply Rejection Ratio PSRR RL = ∞ 0.2 -1 70 Maximum Output Voltage VOM+ VOMSupply Current Device Dissipation Input Offset Voltage Temp. Drift ISUPPLY PD ΔVIO/ΔT 0.9 -0.85 TYP 2 0.01 0.02 100 100 560 65 0.5 -1.3 32 90 0.95 -0.91 350 0.7 4 MAX 5 4 5 1000 320 650 1.1 UNITS mV pA pA kV/V dB µV/V dB V V µV/V dB V V µA mW µV/°C SYMBOL VIO |IIO| |II| AOL Electrical Specifications PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain For Equipment Design at VSUPPLY = ±10V, TA = +25°C, Unless Otherwise Specified SYMBOL VIO |IIO| |II| AOL CMRR RL = 10kΩ TEST CONDITIONS CA5420A MIN 20 80 TYP 2 0.03 0.05 100 100 100 80 9.3 -10.3 32 90 9.9 -9.85 450 9 4 MAX 5 4 5 320 320 1000 14 UNITS mV pA pA kV/V dB µV/V dB V V µV/V dB V V µA mW µV/°C Common Mode Rejection Ratio 70 Common Mode Input Voltage Range VlCR+ VlCRPSRR RL = ∞ 9 -10 70 Power Supply Rejection Ratio Maximum Output Voltage VOM+ VOMISUPPLY PD ΔVIO/ΔT 9.7 -9.7 - Supply Current Device Dissipation Input Offset Voltage Temperature Drift NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5 FN1925.6 December 8, 2009 CA5420A Typical Applications Picoammeter Circuit The exceptionally low input current (typically 0.2pA) makes the CA5420A highly suited for use in a picoammeter circuit. With only a single 10GΩ resistor, this circuit covers the range from ±1.5pA. Higher current ranges are possible with suitable switching techniques and current scaling resistors. Input transient protection is provided by the 1MΩ resistor in series with the input. Higher current ranges require that this resistor be reduced. The 10MΩ resistor connected to pin 2 of the CA5420A decouples the potentially high input capacitance often associated with lower current circuits and reduces the tendency for the circuit to oscillate under these conditions. 10GΩ High Input Resistance Voltmeter Advantage is taken of the high input impedance of the CA5420A in a high input resistance DC voltmeter. Only two 1.5V “AA” type penlite batteries power this exceedingly high-input resistance (>1,000,000MΩ) DC voltmeter. Full-scale deflection is ±500mV, ±150mV, and ±15mV. Higher voltage ranges are easily added with external input voltage attenuator networks. The meter is placed in series with the gain network, thus eliminating the meter temperature co-efficient error term. Supply current in the standby position with the meter undeflected is 300µA. At full-scale deflection this current rises to 800µA. Carbon-zinc battery life should be in excess of 1,000 hours. +1.5V 500-0-500 µA 6 M ±50pA BATTERY RETURNS 1.5kΩ 1.5kΩ 1% 1kΩ 430Ω 1% -1.5V ±1.5pA 150Ω 1% ±15mV 150Ω 1% 68Ω 1% 3 + 7 6 500-0-500 µA M ±500mV BATTERY RETURNS 1.5kΩ 1.5kΩ 1% 1kΩ 430Ω 1% 10pF 2 +1.5V 7 1MΩ 10MΩ + 5 1 CA5420A 3 4 22MΩ 10MΩ 100pF CA5420A 2 5 1 4 10kΩ ±15pA 10kΩ ±150mV ±5pA -1.5V ±50mV 11kΩ 68Ω 1% 1.1kΩ FIGURE 1. PICOAMMETER CIRCUIT FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER Typical Performance Curves INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 5 10 SUPPLY VOLTAGE (V) 15 VO+ VICRVICR+ VOTA = +25°C RL = 100kΩ OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q19 (mV) 10 TA = +25°C V- = 0V V+ = 2V 100 V+ = 5V V+ = 10V V+ = 20V 1000 0.001 0.1 1 LOAD (SOURCING) CURRENT (mA) 10 FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT 6 FN1925.6 December 8, 2009 CA5420A Typical Performance Curves OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q17 (mV) 1000 TA = +25°C V+ = 0V SUPPLY CURRENT (µA) 2400 2000 1600 1200 800 400 10 0.01 0.1 1 LOAD (SINKING) CURRENT (mA) 10 (Continued) V+ = 5V V- = GND 100 V- = -20V V- = -10V V- = -5V V- = -2V 0 1 2 3 OUTPUT VOLTAGE (V) 4 5 FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT 5.00 OUTPUT VOLTAGE SWING (V) TA = +25°C V+ = 5V V- = GND RL TO GND FIGURE 6. SUPPLY CURRENT vs OUTPUT VOLTAGE 800 700 INPUT BIAS CURRENT (pA) 600 500 400 300 200 100 V+ = 5V V- = GND 3.75 2.50 1.25 0 0 1 10 100 LOAD RESISTANCE (kΩ) 1000 0 25 35 45 55 65 75 85 95 TEMPERATURE (°C) 105 115 125 FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 8. INPUT BIAS CURRENT DRIFT (ΔIB/ΔT) EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz) 1000 VS = ±10V VS = ±5V VS = ±1V 100 TA = +25°C OPEN LOOP VOLTAGE GAIN (dB) 100 0 -45 -90 80 60 -135 -180 101 40 20 1 101 102 103 104 105 106 0 1 101 102 103 104 105 106 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 9. INPUT NOISE VOLTAGE vs FREQUENCY FIGURE 10. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE Small Outline Plastic Packages (SOIC) 7 FN1925.6 December 8, 2009 OPEN LOOP PHASE (DEGREES) TA =+ 25°C V+ = +10V, V- = 10V RL = 10kΩ CL = 0pF CA5420A N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 7. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 10. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 11. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 12. “L” is the length of terminal for soldering to a substrate. 13. “N” is the number of terminal positions. 14. Terminal numbers are shown for reference only. 15. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 16. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN1925.6 December 8, 2009