CD22202E

DTMF Receivers/Generators CD22202, CD22203 January 1997 5V Low Power DTMF Receiver Description The CD22202 and CD22203 complete dual-tone multiple frequency (DTMF) receivers detect a selectable group of 12 or 16 standard digits. No front-end pre-filtering is needed. The only externally required components are an inexpensive 3.579545MHz TV “colorburst’’ crystal (for frequency reference) and a bias resistor. Extremely high system density is possible through the use of the clock output of a crystal connected CD22202/CD22203 receiver to drive the time bases of additional receivers. This is a monolithic integrated circuit fabricated with low-power, complementary symmetry CMOS processing. It only requires a single low tolerance power supply. The CD22202 and CD22203 employ state-of-the-art circuit technology to combine the digital and analog functions on the same CMOS chip using a standard digital semiconductor process. The analog input is preprocessed by 60Hz reject and band splitting filters and then hard limited to provide AGC. Eight Bandpass filters detect the individual tones. The digital post processor times the tone durations and provides the correctly coded digital outputs. Outputs interface directly to standard CMOS circuitry and are three-state enabled to facilitate bus oriented architectures. Features • Central Office Quality • No Front End Band Splitting Filters Required • Single, Low Tolerance, 5V Supply • Detects Either 12 or 16 Standard DTMF Digits • Uses Inexpensive 3.579545MHz Crystal for Reference • Excellent Speech Immunity • Output in Either 4-Bit Hexadecimal Code or Binary Coded 2-of-8 • Synchronous or Handshake Interface • Three-State Outputs • Excellent Latch-Up Immunity Ordering Information PART NUMBER CD22202E CD22203E TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 18 Ld PDIP 18 Ld PDIP PKG. NO. E18.3 E18.3 Pinout CD22202, CD22203 (PDIP) TOP VIEW D1 HEX/B28 EN IN1633 VDD ED (203 ONLY), NC (202) VSS XEN ANALOG IN 1 2 3 4 5 6 7 8 9 Functional Diagram 6 PREPROCESSOR/ BANDSPLIT FILTER LOW B/P FILTERS 15 CLRDV 14 HIGH B/P FILTERS DETECTORS AND SIGNALPROCESSING CIRCUITS DV 2 HEX/B28 1 D1 18 D2 17 D4 16 D8 VOLTAGE REG./REF. 5 VDD 10 VSS 7 4 INI633 3 EN ED-203 NC-202 18 D2 17 D4 16 D8 15 CLRDV 14 DV 13 ATB ANALOG IN 9 13 ATB XEN 8 CHIP CLOCKS 12 CLOCK GENERATOR 12 XIN XIN 11 XOUT 10 VSS 11 XOUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 1695.3 4-245 CD22202, CD22203 Absolute Maximum Ratings DC Supply Voltage (VDD)(Referenced to VSS Terminal). . . . . . . . 7V Power Dissipation TA = 25oC (Derate above TA = 25oC at 6.25mW/oC. . . . . . . . 65mW Input Voltage Range All Inputs Except Analog In . . . . . . . . . . . . . . (VDD +0.5V) to -0.5V Analog in Voltage Range . . . . . . . . . . . . (VDD +0.5V) to (VDD -10V) DC Current into any Input or Output . . . . . . . . . . . . . . . . . . . . . .±20mA NOTE: Unused inputs must be connected to VDD or VSS as appropriate. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Thermal Information Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Electrical Specifications PARAMETER Frequency Detect Bandwidth Amplitude for Detection Minimum Acceptable Twist 0oC ≤ TA ≤ +70oC, VDD = 5V ±10% TEST CONDITIONS MIN ±(1.5 + 2Hz) Each Tone High To ne Tw ist = --------------------------Low To ne -32 -10 TYP ±2.3 MAX ±3.5 -2 +10 % of fO dBm Referenced to 600Ω dB UNITS 60Hz Tolerance Dial Tone Tolerance “Precise” Dial Tone - - 0.8 0 VRMS dB Referenced to Lower Amplitude Tone Hits V V V V mA dB Referenced to Lowest Amplitude Tone Talk Off Digital Outputs (except XOUT) MITEL Tape #CM7291 “0” Level, 400µA Load “1” Level, 200µA Load 0 VDD -0.5 0 0.7VDD - 2 10 - 0.5 VDD 0.3VDD VDD 16 -12 Digital Inputs “0” Level “1” Level Supply Current Noise Tolerance TA = +25oC MITEL Tape #CM7291 (Note 1) VDD ≥ VIN ≥ (VDD -10) Input Impedance NOTE: 100kΩ//15pF 300kΩ - 1. Bandwidth limited (3kHz) Gaussian noise. 4-246 CD22202, CD22203 Functional Block Diagram CD22202 CD22203 BANDPASS FILTERS BAND SPLIT FILTERS BS1 ZERO CROSSING DETECTORS 697 770 852 941 BS2 1209 1336 ATB 13 XEN 8 AMPLITUDE DETECTORS ANALOG IN 9 PREPROCESSOR 60Hz REJECT PRE EMP EARLY DETECT OUTPUT 6 TIMING CIRCUITRY CLRDV 15 CLR 1477 1633 DV STROBE DATA STROBE DV F.F DV 14 12 XIN ÷8 CLOCK GENERATOR H/B28 CHIP CLOCKS 2 1 D1 1MΩ 18 D2 XOUT 11 POWER REGULATOR VOLTAGE REF OUTPUT DECODER OUTPUT REGISTER 17 D4 16 D8 DATA CLEAR 3 EN 5 VDD 10 VSS 7 VSS IN1633 4 NOTE: Pin 6: Early detect output on CD22203 only. System Functions Analog In The Analog In pin accepts the analog input. It is internally biased so that the input signal may be either AC or DC coupled, as long as it does not exceed the positive supply voltage. Proper input coupling is illustrated below. CD22202, CD22203 VDD The CD22202 and CD22203 are designed to accept sinusoidal input waveforms, but will operate satisfactorily with any input that has the correct fundamental frequency with harmonics that are at least 20dB below the fundamental. Crystal Oscillator 0.01µF AUDIO INPUT (+4dBm MAXIMUM) 270kΩ 9 (ON CHIP) 10pF >100kΩ VSS 1500pF 33kΩ ANALOG IN OPTIONAL HIGH FREQUENCY NOISE FILTER (fC = 3.9kHz) The CD22202 and CD22203 contain an on-board inverter with sufficient gain to provide oscillation when connected to a low cost television “color-burst” (3.579545MHz) crystal. The crystal oscillator is enabled by tying XEN high. The crystal is connected between XIN and XOUT. A 1MΩ resistor is also connected between these pins in this mode. ATB is a clock frequency output. Other CD22202 and CD22203 devices may use the same frequency reference by tying their ATB pins to the ATB output of a crystal connected device. XIN and XEN of the auxiliary devices must then be tied high and low, respectively. Up to ten devices may be run from a single crystal connected CD22202 and CD22203 as shown in Figure 2. FIGURE 1. ANALOG IN 4-247 CD22202, CD22203 3.579545MHz DV remains high until a valid pause occurs or CLRDV is raised high, whichever is sooner. This handshake can save microprocessor time. XOUT VDD 1M XIN 12 ATB 13 11 CD22202/22203 8 XEN DTMF Dialing Matrix COL 0 1209Hz ROW 0 697Hz 1 4 7 * COL 1 1336Hz 2 5 8 0 COL 2 1477Hz 3 6 9 # COL 3 1633Hz A B C D XIN CONNECTED TO VDD 12 13 CD22202/22203 XEN 8 ROW 1 770Hz ROW 2 852Hz ROW 3 941Hz UP TO 10 DEVICES FIGURE 2. CRYSTAL OSCILLATOR NOTE: Column 3 is for special applications and is not normally used in telephone dialing. HEX/B28 This pin selects the format of the digital output code. When HEX/B28 is tied high, the output is hexadecimal. When tied low, the output is binary coded 2-of-8. The following table describes the two output codes. TABLE 1. OUTPUT CODES HEXADECIMAL DIGIT 1 2 3 4 5 6 7 8 9 0 * # A B C D D8 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D4 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 BINARY CODED 2-OF-8 D8 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 D4 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 D2 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 D1 0 1 0 0 1 0 0 1 0 1 0 0 1 1 1 1 VSS DIGITAL INPUT CMOS DIGITAL CIRCUITRY DIGITAL OUTPUT IN1633 When tied high, this pin inhibits detection of tone pairs containing the 1633Hz component. For detection of all 16 standard digits, IN1633 must be tied low. N/C Pin This pin has no internal connection and should be left floating. Digital Inputs and Outputs All digital inputs and outputs of the DTMF receivers are represented by the schematic below. Only the “analog in” pin is different, and is described above. Care must be exercised not to exceed the voltage or current ratings on these pins as listed in the “maximum ratings” section. VDD FIGURE 3. DIGITAL INPUTS AND OUTPUTS ED Input Filter This pin, on the CD22203 only, indicates the presence of frequencies which are likely to be DTMF digits, but have not yet been verified by a DV signal. It is comparable to a “buttondown” output, and it is useful as an EARLY DETECT signal to interrupt a microprocessor for digit storage and validation. DV and CLRDV DV signals a detection by going high after a valid tone pair is sensed and decoded at the output pins D1, D2, D4, and D8. The CD22202 and CD22203 will tolerate total input noise of a maximum of 12dB below the lowest amplitude tone. For most telephone applications, the combination of the high frequency attenuation of the telephone line and internal band limiting make special circuitry at the input to these receivers unnecessary. However, noise near the 56kHz internal sampling frequency will be aliased (folded back) into the audio spectrum, so if excessive noise is present 4-248 CD22202, CD22203 above 28kHz, the simple RC filter shown below may be used to band limit the incoming signal. The cut off frequency is 3.9kHz. PARAMETER Tone Time For Detection 270kΩ ANALOG IN 33kΩ SYMBOL MIN TYP MAX UNITS tON tON 40 - - 20 ms ms For Rejection CD22202 CD22203 NOISY SIGNAL Pause Time For Detection For Rejection Detect Time tOFF tOFF tD tR tSU tH tCL tPW tED tER 40 25 35 7 4.2 200 7 2 160 200 20 46 50 5 250 22 18 300 ms ms ms ms µs ms ns ns ms ms ns 0.0015µF FIGURE 4. FILTER FOR USE IN EXTREME HIGH FREQUENCY INPUT NOISE ENVIRONMENT Release Time Data Setup Time Noise will also be reduced by placing a grounded trace around XIN and XOUT pins on the circuit board layout when using a crystal. It is important to note that XOUT is not intended to drive an additional device. XIN may be driven externally; in this case, leave XOUT floating. Data Hold Time DV Clear Time CLRDV Pulse Width ED Detect Time Timing Waveforms TONE BURST 1 ANALOG INPUT tD D1, D2 D4, D8 tON tOFF PAUSE tR TONE BURST 2 ED Release Time Output Enable Time CL = 50pF, RL = 1kΩ Output Disable Time CL = 35pF, RL = 500Ω Output Rise Time CL = 50pF - - 150 200 ns - - 200 300 ns tSU tH tCL Output Fall Time CL = 50pF - - 160 250 ns DV tPW Guard Time Whenever the DTMF receiver is continually monitoring a voice channel containing distorted or musical voices or tones, additional guard time may be added in order to prevent false decoding. This may be done in software by verifying that both ED and DV are present simultaneously for about 55ms. An appropriate guard time should be selected to balance the fastest expected dialing speed against the rejection of distorted or musical voices or tones (most autodialers operate in the 65ms to 75ms range although a few generate 50ms tones). A hardware guard time circuit is shown in Figure 6. R3 and R4 should keep the voice amplitude as low as practical, while R2 and R5 adjust detection speed. CLRDV tED ED (NOTE) tER NOTE: Early Detect output is available only on the CD22203. FIGURE 5. 4-249 CD22202, CD22203 +5V R2 10µF ≈ 240K (55ms) D1 HEX/B28 EN IN1633 1 2 3 4 18 17 16 15 14 13 12 11 10 D2 D4 D8 CLRDV DV ATB XIN XOUT VSS 3.58 MHz R1 1M VDD IN4148 ED C2 0.15µF VSS XEN ANALOG IN R5 1.8M 5 6 7 8 9 R6 100K ENABLE INPUT 1/3 CD74HC04 R4 33K R3 ≈ 390K C1 4700pF D8 D4 D2 D1 HEX DATA OUT AUDIO IN DV OUT (BUFFERS OPTIONAL) FIGURE 6. CD22203 DTMF RECEIVER WITH GUARD TIME CIRCUIT TO PROVIDE EXCEPTIONAL TALK-OFF PERFORMANCE Operating and Handling Considerations Handling All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in ICAN-6525 “Guide to Better Handling and Operation of CMOS Integrated Circuits”. Input Signals To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 20mA even when the power supply is off. Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS, whichever is appropriate. Output Short Circuits Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. Operating Operating Voltage During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turnoff transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-250