CD4007

CD4007UBMS November 1994 CMOS Dual Complementary Pair Plus Inverter Pinout CD4007UBMS TOP VIEW Q2 (P) DRAIN 1 Q2 (P) SOURCE 2 Q2 GATES 3 Q2 (N) SOURCE 4 Q2 (N) DRAIN 5 Q1 GATES 6 VSS, Q1, Q2, Q3 (N) SUBSTRATES Q1 (N) SOURCE Features • High-Voltage Type (20V Rating) • Standardized Symmetrical Output Characteristics • Medium Speed Operation - tPHL, tPLH = 30 ns (typ) at 10V • 100% Tested for Maximum Quiescent Current at 20V • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Devices” • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC 14 VDD, Q1, Q2, Q3 (P) SUBSTRATES, Q1(P) DRAIN 13 Q1 (P) SOURCE 12 Q3 (N) DRAIN, Q3 (P) SOURCE 11 Q3 (P) DRAIN 10 Q3 GATES 9 Q3 (N) SOURCE 8 Q1 (N) DRAIN 7 Applications • Extremely High-Input Impedance Amplifiers • Shapers • Inverters • Threshold Detector • Linear Amplifiers • Crystal Oscillators 6 13 8 n n 3 1 5 n 10 12 Functional Diagram 14 2 11 p p p Description CD4007BMS types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Figure 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. The CD4007BMS is supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4Q H1B H3W 7 4 9 TERMINAL NO. 14 - VDD TERMINAL NO. 7 - VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3291 7-666 Specifications CD4007UBMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25 oC PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 - MAX 0.5 50 0.5 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +125oC -55oC +25o C +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 4.0 12.5 0.53 1.4 3.5 -2.8 0.7 VOH > VOL < VDD/2 VDD/2 1.0 2.5 - V V V V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-667 Specifications CD4007UBMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 110 149 200 270 UNITS ns ns ns ns PARAMETER Propagation Delay SYMBOL TPHL TPLH TTHL TTLH CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND Transition Time +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. 55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55 C, +25 C +125 C VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125 C -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay VIL VIH TPHL TPLH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC 8 60 50 V ns ns o o o o MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 - MAX 0.25 7.5 0.5 15 0.5 30 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 2 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V 7-668 Specifications CD4007UBMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Transition Time SYMBOL TTHL TTLH CIN CONDITIONS VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC o MIN - MAX 100 80 15.0 UNITS ns ns pF Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VNTH VPTH ∆VPTH F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25 C +25oC +25oC +25oC +25oC +25oC o MIN -2.8 0.2 VOH > VDD/2 - MAX 2.5 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ±0.1µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A 7-669 Specifications CD4007UBMS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group D MIL-STD-883 METHOD Sample 5005 GROUP A SUBGROUPS 1, 2, 3, 8A, 8B, 9 READ AND RECORD Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ±5%, VDD = 18V ±0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ±0.5V OPEN 1, 5, 8, 12, 13 1, 5, 8, 12, 13 1, 5, 8, 12, 13 GROUND 3, 4, 6, 7, 9, 10 4, 7, 9 4, 7, 9 4, 7, 9 VDD 2, 11, 14 2, 3, 6, 10, 11, 14 2, 11, 14 2, 3, 6, 10, 11, 14 1, 5, 8, 12, 13 3, 6, 10 9V ± -0.5V 50kHz 25kHz Schematic Diagram 14 2 ** 11 ** D2 D2 D2 * D2 6 D1 D1 R1 D2 D2 * D2 R1 D1 D1 D2 D2 * D2 R1 D1 D1 D2 D2 12 Q3 D1 ** 13 8 Q1 3 D1 ** 1 Q2 10 5 D1 D1 ** *CMOS INPUT PROTECTION NETWORK D1 7 VDD D2 OUTPUT TERMINAL D1 4 D1 D1 PARASITIC AND NETWORK COMPONENTS D1 = N+ TO P WELL D2 = P+ TO SUBSTRATE R1 = 1 - 5 KΩ R2 = 15 - 30Ω 9 ** ** **CMOS OUTPUT PROTECTION NETWORK BETWEEN TERMINAL NOS. 1, 2, 4, 5, 8, 9, 11, 12, 13 AND THE CORRESPONDING DRAINS AND/OR SOURCES R2 D1 VSS FIGURE 1. DETAILED SCHEMATIC DIAGRAM OF CD4007UBMS SHOWING INPUT, OUTPUT, AND PARASITIC DIODES 7-670 CD4007UBMS Logic Circuits 6 8 3 5 6 3 12 10 (13, 2); (1, 11); (12, 5, 8); (7, 4, 9) 6 3 10 12 (14, 2, 11); (8, 13); (1, 5); (7, 4, 9) 10 12 (1, 12, 13); (2, 14, 11); (4, 8); (5, 9) a) TRIPLE INVERTERS b) 3 - INPUT NOR GATE VDD # A OUT 12 A B C VDD c) 3 - INPUT NAND GATE B 10 A 3 OUT B C VSS (13, 12, 5); (4, 9, 8); (14, 2); (1, 11) OUT (VDD) = C + AB OUT (VSS) = CA + CB C 6 #ALL P- UNIT SUBSTRATES ARE CONNECTED TO VDD ALL N- UNIT SUBSTRATES ARE CONNECTED TO VSS VSS d) TREE (RELAY) LOGIC VDD (OPTIONAL VDD PULL-UP) VDD (6, 3, 10); (13, 1, 12); (14, 2, 11); (7, 9) 6 12 6 (6, 3, 10); (8, 5, 12); (11, 14); (7, 4, 9) VSS 12 (OPTIONAL VSS PULL-DOWN) VSS e) HIGH SINK-CURRENT DRIVER VDD f) HIGH SOURCE-CURRENT DRIVER 2 6 CLOCK 12 IN (OUT) 12 TG2 4 TG1 OUT1 (IN1) 6 OUT2 (IN2) (6, 3, 10); (14, 2, 11); (7, 4, 9); (13, 8, 1, 5, 12) VSS (1, 5, 12); (2, 9); (11, 4); (8, 13, 10); (6, 3) g) HIGH SINK - AND SOURCE-CURRENT DRIVER h) DUAL BI-DIRECTIONAL TRANSMISSION GATING FIGURE 2. SAMPLE CMOS LOGIC CIRCUIT ARRANGEMENTS USING TYPE CD4007UBMS 7-671 CD4007UBMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC A - SINGLE INPUT ONLY B - TWO INPUTS ONLY C - THREE INPUTS * OTHER INPUT SWITCHES TO VDD VI AMBIENT TEMPERATURE (TA) = +25oC VI OUTPUT VOLTAGE (VO) (V) SUPPLY VOLTAGE (VDD) = 15V A B C 10V A B C 5V A B C 0 2.5 VO OUTPUT VOLTAGE (VO) (V) * 16 14 12 10 8 6 4 2 0 SUPPLY VOLTAGE (VDD) = 15V A B C A B C 16 14 12 10 8 6 4 2 10V VO 5V C B A VDD A - SINGLE INPUT ONLY B - TWO INPUTS ONLY C - THREE INPUTS * OTHER INPUT * 2.5 5.0 7.5 10 12.5 INPUT VOLTAGE (VI) (V) 15 5.0 7.5 10.0 12.5 INPUT VOLTAGE (VI) (V) 15.0 FIGURE 3. TYPICAL VOLTAGE-TRANSFER CHARACTERISTICS FOR NAND GATE AMBIENT TEMPERATURE (TA) = +25oC FIGURE 4. TYPICAL VOLTAGE-TRANSFER CHARACTERISTICS FOR NOR GATE OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT VOLTAGE (VO) (V) 30 25 20 15 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 10V GATE-TO-SOURCE VOLTAGE (VGS) = 15V SUPPLY VOLTAGE (VDD) = 15V 15.0 12.5 10V 10.0 7.5 5V 5.0 2.5 VI VO 0 2.5 5.0 7.5 10.0 12.5 INPUT VOLTAGE (VI) (V) 15.0 FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 15.0 OUTPUT VOLTAGE (VO) (V) 12.5 10 10.0 15 7.5 5 5.0 10 2.5 5 0 2.5 5.0 7.5 10.0 12.5 15.0 INPUT VOLTAGE (VI) (V) TERM 3 & 6 TO GND 2.5 7 ID 9 VO ID VI 10 VO 12 7.5 5.0 10.0 SUPPLY VOLTAGE (VDD) = 15V FIGURE 6. MINIMUM AND MAXIMUM VOLTAGE-TRANSFER CHARACTERISTICS FOR INVERTER 14 11 VDD 12.5 OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY MILLIAMPERES (ID) 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 7. TYPICAL CURRENT AND VOLTAGE-TRANSFER CHARACTERISTICS FOR INVERTER FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-672 CD4007UBMS Typical Performance Characteristics DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 (Continued) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC 100 SUPPLY VOLTAGE (VDD) = 5V 80 15 OUTPUT VOLTAGE (VO) (V) TA 10 SUPPLY VOLTAGE (VDD) = 15V =125oC -55oC 10V -55oC 125oC 5V 60 10V 40 15V 20 5 125oC -55oC 0 5 10 15 INPUT VOLTAGE (VI) (V) 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 11. TYPICAL VOLTAGE-TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FIGURE 12. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC DISSIPATION PER GATE (PD) (µW) 105 SUPPLY VOLTAGE (VDD) = 15V 104 10V 103 5V 102 10 1 LOAD CAPACITANCE (CL) = 15pF (CL) = 50pF 2 468 2 468 2 468 2 468 2 468 2 468 AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (fTHL, fTLH) (ns) 200 SUPPLY VOLTAGE (VDD) = 5V 10V 150 100 10V 50 5V 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 102 103 104 105 106 INPUT FREQUENCY (fi) (Hz) 107 FIGURE 13. TYPICAL TRANSISTION TIME vs LOAD CAPACITANCE FIGURE 14. TYPICAL DISSIPATION vs FREQUENCY CHARACTERISTICS 7-673 CD4007UBMS Chip Dimension and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 674