CD40102BMS

CD40102BMS CD40103BMS December 1992 CMOS 8-Stage Presettable Synchronous Down Counters Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is configured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESETENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 represent two 4-bit BCD words for the CD40102BMS and a single 8-bit binary word for the CD40103BMS. When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102BMS and 25510 for the CD40103BMS) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD output to go low to enable the clock on each succeeding clock pulse. CD40102BMS, CD40130BMS TOP VIEW CLOCK CLEAR 1 2 3 4 5 6 7 8 16 VDD SYNCHRONOUS 15 PRESET ENABLE 14 CARRY OUT/ ZERO DETECT 13 J7 12 J6 11 J5 10 J4 9 ASYNCHRONOUS PRESET ENABLE Features • High Voltage Type (20V Rating) • CD40102BMS: 2-Decade BCD Type • CD40103BMS: 8-Bit Binary Type • Synchronous or Asynchronous Preset • Medium Speed Operation - fCL = 3.6MHz (Typ) at 10V • Cascadable • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Divide-By- “N” Counters • Programmable Times • Interrupt Timers • Cycle/Program Counter Pinout The CD40102BMS and CD40103BMS may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode as shown in Figures 16 and 17. The CD40102MS and CD40103BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD40102B Only *H4W †H4X *H1L †H1F H6W †CD40130B Only CARRY IN/ COUNTER ENABLE J0 J1 J2 J3 VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3351 7-1294 Specifications CD40102BMS, CD40103BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance θja θjc Ceramic DIP Package . . . . . . . . . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20V 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20V 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VOH > VOL < VDD/2 VDD/2 NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-1295 Specifications CD40102BMS, CD40103BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN .7 .52 MAX 600 810 400 540 1300 1755 750 1012 200 270 UNITS ns ns ns ns ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to Output Propagation Delay Carry In/Counter Enable to Output Propagation Delay Asynchronous Preset Enable to Output Propagation Delay Clear to Output Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPLH4 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC Maximum Clock Input Frequency NOTES: +25oC +125oC, -55oC 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC 7-1296 Specifications CD40102BMS, CD40103BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH10 CONDITIONS VDD = 10V, VOUT = 9.5V NOTES 1, 2 TEMPERATURE +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Clock to Output Propagation Delay Carry In/Counter Enable to Output Propagation Delay Asynchronous Preset Enable to Output Propagation Delay Clear to Output Transition Time VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPLH4 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TTHL1 TTLH1 FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TSU VDD = 5V VDD = 10V VDD = 15V Minimum CI/CE Setup Time TSU VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum APE Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum JAM Setup Time (Synchronous Presetting) Minimum APE Removal Time TSU VDD = 5V VDD = 10V VDD = 15V TREM VDD = 5V VDD = 10V VDD = 15V Minimum CLR Pulse Width TW VDD = 5V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC o o MIN 7 1.8 2.4 - MAX -0.9 -1.6 -2.4 -4.2 3 260 190 180 130 600 400 360 200 100 80 280 140 100 500 250 150 300 180 80 360 160 120 200 80 60 220 100 70 320 160 100 UNITS mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Maximum Clock Input Frequency Minimum SPE Setup Time 7-1297 Specifications CD40102BMS, CD40103BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V SYMBOL CIN CONDITIONS Any Input NOTES 1, 2 TEMPERATURE +25oC MIN MAX 7.5 UNITS pF ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A 7-1298 Specifications CD40102BMS, CD40103BMS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group D MIL-STD-883 METHOD Sample 5005 GROUP A SUBGROUPS 1, 2, 3, 8A, 8B, 9 READ AND RECORD Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz PART NUMBER CD40102BMS, CD40103BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 14 14 1 - 13, 15 8 3, 8, 15 16 1 - 7, 9 - 13, 15, 16 2, 16 14 1, 4, 6, 11, 13 5, 7, 9, 10, 12 Functional Diagram SPE APE CI/CE CLR JAM J0 8 - STAGE DOWN COUNTER C0/ZD J7 CLOCK CD40102BMS, CD40103BMS 7-1299 CD40102BMS, CD40103BMS Logic Diagrams LSD J0 J1 J2 J3 * 4 * 5 * 6 * 7 (MSB) A B TO FF1 - FF7 C CLR CLR CLR SPE SPE APE CL CL CI FF1 Q CI CI FF2 FF3 CI Q FF3 Q J Q J Q J Q J * * * * 2 SPE 15 APE 9 CLOCK 1 TO FF1 - FF7 D CI/CE * E 3 MSD J4 J5 J6 J7 * A B C 10 * 11 * 12 * 13 (MSB) 14 CARRY OUT/ ZERO DETECT J FF4 Q CI J Q J Q J FF7 Q CI VDD FF5 CI FF6 CI D VSS *ALL INPUTS ARE E PROTECTED BY COS/MOS PROTECTION NETWORK FIGURE 1. LOGIC DIAGRAM FOR CD40102BMS 7-1300 CD40102BMS, CD40103BMS Logic Diagrams (Continued) J0 J1 J2 J3 * 4 * 5 * 6 * 7 A B TO FF1 - FF7 C CLR CLR CLR SPE SPE APE CL CL CI FF1 Q CI Q CI FF2 Q CI FF3 Q FF3 Q J J J Q J * * * * 2 SPE 15 APE 9 CLOCK 1 VDD TO FF1 - FF7 D CI/CE * E 3 J4 J5 J6 J7 * A B C 10 * 11 * 12 * 13 (MSB) 14 CARRY OUT/ ZERO DETECT J FF4 Q CI J FF5 Q CI J FF6 Q CI J FF7 Q CI VDD D VSS *ALL INPUTS ARE VDD E PROTECTED BY COS/MOS PROTECTION NETWORK FIGURE 2. LOGIC DIAGRAM FOR CD40103BMS 7-1301 CD40102BMS, CD40103BMS TRUTH TABLE CONTROL INPUTS CLR 1 1 1 1 0 NOTES: 1. 0 = Low Level 1 = High Level X = Don’t Care 2. Clock connected to clock input 4. JAM inputs: CD40102BMS; MSD = J7, J6, J5, J4, (J7 is MSB) LSD = J3, J2, J1, J0 (J3 is MSB) CD40103BMS Binary; MBS = J7, LSB = J0 APE 1 1 1 0 X SPE 1 1 0 X X CI/CE 1 0 X X X Asynchronous PRESET MODE Synchronous Inhibit Counter Count Down* Preset on next positive clock transition Preset Asynchronously Clear to maximum count ACTION 3. Synchronous operation: changes occur on negative-to-positive clock transitions *At zero count, the counters will jump to the maximum count on the next clock transition to “High” Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-1302 CD40102BMS, CD40103BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) (Continued) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 SUPPLY VOLTAGE (VDD) = 5V 150 200 10V 100 10V 50 15V 100 15V 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 100 FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE MAXIMUM CLOCK INPUT FREQUENCY (fCL MAX) (MHz) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO CO/ZD) POWER DISSIPATION /PACKAGE (PD) (µW) 105 8 6 4 2 AMBIENT TEMPERATURE (TA) = 25oC LOAD CAPACITANCE (CL) = 50pF 7.5 AMBIENT TEMPERATURE (TA) = +25oC tr, tf = 20ns RL = 200kΩ 104 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 5 103 2 8 6 4 2 10V 10V 5V 2.5 102 8 6 4 2 CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 10 0 5 10 15 20 1 SUPPLY VOLTAGE (VDD) (V) 103 10 102 INPUT FREQUENCY (fI) (kHz) 104 FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF FREQUENCY 7-1303 CD40102BMS, CD40103BMS Q CI CI CI Q CL CL D SQ TO GATING CL CL R Q TO GATING SPE SPE J CLR APE CLR FIGURE 11. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS, FF0 - FF7, USED IN LOGIC DIAGRAMS FOR CD40102BMS AND CD40103BMS CLK CLR CI/CE SPE APE J0 J1 J2 J3 J4 J5 J6 J7 CO/ZD CD40102BMS COUNT CD40103BMS COUNT 99 255 98 254 3 3 2 2 1 1 0 0 99 255 98 254 98 254 97 253 8 8 7 7 6 6 5 5 4 4 99 255 98 254 97 253 96 252 FIGURE 12. TIMING DIAGRAM FOR CD40102BMS AND CD40103BMS 7-1304 CD40102BMS, CD40103BMS VDD VDD J0 J1 J2 J3 N J4 J5 J6 J7 CO/ZD fOUT = fIN ÷ (N + 1) J0 J1 CO/ZD TIME-OUT CI/CE SPE N APE CLR J2 J3 J4 J5 J6 CI/CE SPE COUNT DOWN APE CLR PRESET CLOCK fIN J7 CLOCK fIN VSS VSS FIGURE 13. DIVIDE-BY- “N” COUNTER VDD FIGURE 14. PROGRAMMABLE TIMER J0 J1 J2 FROM MICROPROCESSOR DATA BUS J3 J4 J5 J6 J7 CO/ZD TO MICROPROCESSOR INTERRUPT LINE CI/CE SPE APE CLR EXT OSC CLOCK PRESET TIMER (I/O COMMAND) VSS FIGURE 15. MICROPROCESSOR INTERRUPT TIMER CD4071BMS* CLOCK ENABLE INPUT CLOCK CI/CE CO/ZD CLOCK CI/CE CO/ZD CLOCK CI/CE CO/ZD CLOCK CASCADED OUTPUT *An output spike (160ns at VDD = 5V) occurs whenever two or more devices are cascaded in the parallel-clocked mode because the clock-to-carry out delay is greater than the carry-in-to-carry out delay. This spike is eliminated by gating the output of the last device with the clock as shown. FIGURE 16. SYNCHRONOUS CASCADING CLOCK ENABLE INPUT CLOCK CI/CE CO/ZD CLOCK CI/CE CO/ZD CLOCK CI/CE CO/ZD CLOCK CASCADED OUTPUT VSS VSS FIGURE 17. RIPPLE CASCADING 7-1305 CD40102BMS, CD40103BMS Chip Dimensions and Pad Layouts CD40102BMS Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). CD40103BMS METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 1306