CD4017BMS

CD4017BMS, CD4022BMS Data Sheet August 1998 File Number 3297 CMOS Counter/Dividers CD4017BMS - Decade Counter with 10 Decoded Outputs CD4022BMS - Octal Counter with 8 Decoded Outputs CD4017BMS and CD4022BMS are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high speed operation, 2-input decode gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counter sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRYOUT signal completes one cycle every 10 clock input cycles in the CD4017BMS or every 8 clock input cycles in the CD4022BMS and is used to ripple-clock the succeeding device in a multi-device counting chain. The CD4017BMS and CD4022BMS series types are supplied in these 16 lead outline packages Features • High Voltage Types (20V Rating) • Fully Static Operation • Medium-Speed Operation 10MHz (Typ) at VDD = 10V • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard Number 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Decade Counter/Decimal Decode Display (CD4017BMS) • Binary Counter/Decoder • Frequency Division • Counter Control/Timers • Divide-by-N Counting • For Further Application Information, See ICAN-6166 “COS/MOS MSI Counter and Register Design and Applications” Pinouts CD4017BMS TOP VIEW 51 12 03 16 VDD 15 RESET 14 CLOCK 13 CLOCK INHIBIT 12 CARRY OUT 11 9 10 4 98 Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4017B Only *H4W †H4X *H1F †H1E H6W † CD4022B Only Functional Diagrams CD4017BMS CLOCK CLOCK INHIBIT RESET 14 13 15 3 2 4 7 10 1 5 6 9 11 12 “0” “1” “2” “3” “4” “5” “6” “7” “8” “9” 24 65 76 37 DECODED DECIMAL OUT NC = NO CONNECTION VSS 8 VCC = 16 VSS = 8 CD4022BMS TOP VIEW 11 02 16 VDD 15 RESET 14 CLOCK 13 CLOCK INHIBIT 12 CARRY OUT 11 4 10 7 9 NC CARRY OUT CD4022BMS CLOCK CLOCK INHIBIT RESET 14 13 15 2 1 3 7 11 4 5 10 12 “0” “1” “2” “3” “4” “5” “6” “7” 23 54 DECODED OUT 65 NC 6 37 NC = NO CONNECTION VSS 8 VCC = 16 VSS = 8 CARRY OUT 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4017BMS, CD4022BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance. . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VOH > VOL < VDD/2 VDD/2 NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 2 CD4017BMS, CD4022BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2.5 1.85 MAX 650 878 600 810 530 716 200 270 UNITS ns ns ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to Decode Out Propagation Delay Clock to Carry Out Propagation Delay Reset to Out Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TTHL TTLH FCL CONDITIONS (Note 1, 2) VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low Input Voltage High VOL VOL VOH VOH IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VIH VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 7 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V 3 CD4017BMS, CD4022BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Clock to Decode Out Propagation Delay Clock to Carry Out Propagation Delay Reset to out Transition Time Maximum Clock Input Frequency Minimum Setup Time Clock Inhibit to Clock Setup Minimum Reset Pulse Width SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TTHL TTLH FCL TS CONDITIONS VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VTN ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.7 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 5.0 5.5 MAX 270 170 250 160 230 170 100 80 230 100 70 260 110 60 200 90 60 7.5 UNITS ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns pF ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT 4 CD4017BMS, CD4022BMS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND PART NUMBER CD4017BMS AND CD4002B Static Burn-In 1 1 - 7, 9 - 12 8, 13, 15 Note 1 Static Burn-In 2 1 - 7, 9 - 12 8, 14 Note 1 Dynamic Burn8, 13, 15 In Note 1 Irradiation 1 - 7, 9 - 12 8 Note 2 NOTE: VDD 14, 16 13, 15, 16 16 13 - 16 9V ± -0.5V 1 - 7, 9 - 12 50kHz 14 25kHz - 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 5 CD4017BMS, CD4022BMS Logic Diagram 0 3 1 2 2 4 3 7 4 10 5 1 6 5 7 6 8 9 9 11 CARRY OUT 12 D C R Q1 Q1 D C R Q2 Q2 D C R Q3 Q3 D C R Q4 Q4 D C R Q5 Q5 *RESET 15 VDD *CLOCK 14 13 *CLOCK INHIBIT VSS * All Inputs Protected by CMOS Protection Network FIGURE 1. CD4017BMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6 CD4017BMS, CD4022BMS Logic Diagram (Continued) 0 2 1 1 2 3 3 7 4 11 5 4 6 5 7 10 CARRY OUT 12 D C R Q1 Q1 D C R Q2 Q2 D C R Q3 Q3 D C R Q4 Q4 *RESET 15 VDD *CLOCK 14 13 *CLOCK INHIBIT * All Inputs Protected by CMOS Protection Network VSS FIGURE 2. CD4022BMS Timing Diagram CLOCK RESET CLOCK INHIBIT “0” “1” “2” “3” “4” “5” “6” “7” “8” “9” CARRY OUT CLOCK RESET CLOCK INHIBIT 0 1 2 3 4 5 6 7 8 9 “6” “7” CARRY OUT 6 7 6 7 0 1 2 “2” “3” “4” “5” 2 3 4 5 2 3 4 5 “0” “1” 0 1 0 1 0 FIGURE 3. CD4017BMS FIGURE4. CD4022BMS 7 CD4017BMS, CD4022BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 12.5 10 7.5 5 2.5 0 10V 10V 5V 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100 -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) FIGURE 8. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC 700 600 500 400 300 200 100 200 SUPPLY VOLTAGE (VDD) = 5V 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 50 15V 10V 15V 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO DECODE OUTPUT) 8 CD4017BMS, CD4022BMS Typical Performance Characteristics PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC POWER DISSIPATION (PD) (µW) (Continued) 105 LOAD CAPACITANCE CL = 50pF CL = 15pF 700 600 500 400 300 200 100 104 SUPPLY VOLTAGE (VDD) = 15V 103 5V 102 AMBIENT TEMPERATURE (TA) = +25oC INPUT tr = tf = 20ns 10 1 10 102 103 104 105 10V 10V SUPPLY VOLTAGE (VDD) = 5V 10V 15V 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 100 CLOCK INPUT FREQUENCY (fCL) (kHz) FIGURE 11. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO CARRY OUT) FIGURE 12. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY CLOCK TS CLOCK INHIBIT RESET TPHL DECODE 1-9 OUTPUT DECODE “0” OR CARRY OUTPUT TPLH TPRHL CLOCK CLOCK INHIBIT 0 CD4017BMS OR CD4022BMS 1 2 ... N COUT FOR N ≥ 6 f = CLOCK ÷ N N DECODED O DECODED OUTPUTS OUTPUTS ALTERNATE COUT FOR N = 2 TO 10 f = CLOCK ÷ N TPHL TPRLH Delays Measured Between 50% levels on All Waveforms FIGURE 13. PROPAGATION DELAY, SETUP, AND RESET REMOVAL TIME WAVEFORMS FIGURE 14. DIVIDE BY N COUNTER (N ≤ 10) WITH N DECODED OUTPUTS C R C R C R CE CD4017BMS Q0 Q1 . . . Q8 Q9 CE CD4017BMS Q0 Q1 . . . Q8 Q9 CE CD4017BMS Q0 Q1 . . . Q8 Q9 9 DECODED OUTPUTS 8 DECODED OUTPUTS 8 DECODED OUTPUTS CLOCK FIRST STAGE INTERMEDIATE STAGE LAST STAGE FIGURE 15. CASCADING THE CD4017BMS When the Nth decoded output is reached (Nth clock pulse) the S-R flip-flop (constructed from two NOR gates of the CD4001B) generates a reset pulse which clears the CD4017BMS or CD4022BMS to its zero count. At this time, if the Nth decoded output is greater than or equal to 6 in the CD4017BMS or 5 in the CD4022BMS, the COUT line goes high to clock the next CD4017BMS or CD4022BMS counter section. The “0” 9 decoded output also goes high at this time. Coincidence of the clock low and decoded “0” output low resets the S-R flip-flop to enable the CD4017BMS or CD4022BMS. If the Nth decoded output is less than 6 (CD4017BMS) or 5 (CD4022BMS), the COUT line will not go high and, therefore, cannot be used. In this case “0” decoded output may be used to perform the clocking function for the next counter. CD4017BMS, CD4022BMS Chip Dimensions and Pad Layouts CD4017BMSH Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) CD4022BMSH METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 10