CD4040BMS

CD4020BMS, CD4024BMS, CD4040BMS October 1996 CMOS Ripple-Carry Binary Counter/Dividers Pinouts CD4020BMS TOP VIEW Features • High Voltage Types (20V Rating) • Medium Speed Operation • Fully Static Operation • Buffered Inputs and Outputs • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • Common Reset • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications For Description Of ‘B’ Series CMOS Devices” Q12 1 Q13 2 Q14 3 Q6 4 Q5 5 Q7 6 Q4 7 VSS 8 16 VDD 15 Q11 14 Q10 13 Q8 12 Q9 11 RESET 10 θ 9 Q1 CD4024BMS TOP VIEW θ1 RESET 2 Q7 3 Q6 4 Q5 5 Q4 6 VSS 7 14 VDD 13 NC 12 Q1 11 Q2 10 NC 9 Q3 8 NC Applications • Control Counters • Timers • Frequency Dividers • Time-Delay Circuits Description NC = NO CONNECTION CD4020BMS - 14 Stage CD4024BMS - 7 Stage CD4040BMS - 12 Stage CD4020BMS, CD4024BMS, and CD4040BMS are ripplecarry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and the CD4040BMS is supplied in these 14 lead outline packages: CD4020B CD4024B H4Q H1B H3W CD4040B H4X H1F H6W Q12 1 Q6 2 Q5 3 Q7 4 Q4 5 Q3 6 Q2 7 VSS 8 CD4040BMS TOP VIEW 16 VDD 15 Q11 14 Q10 13 Q8 12 Q9 11 R 10 θ 9 Q1 Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4W H1F H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3300.1 7-359 Specifications CD4020BMS, CD4024BMS, CD4040BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, +25oC, LIMITS TEMPERATURE +25 C +125 C -55 oC o o PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 - MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +25o C +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC -55oC -55oC 14.95 0.53 1.4 3.5 -2.8 0.7 VOH > VOL < VDD/2 VDD/2 3.5 11 1.5 4 - V V V V +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-360 Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN 3.5 2.22 MAX 360 486 330 446 280 378 200 270 UNITS ns ns ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay 0 To Q1 Propagation Delay Qn To Qn + 1 Propagation Delay Reset To Q Transition Time Q1 Maximum Clock Input Frequency NOTES: SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPLH3 TPHL3 TTHL TTLH FCL CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA MIN MAX 5 150 10 300 10 600 50 UNITS µA µA µA µA µA µA mV 7-361 Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage Low Input Voltage High Propagation Delay Input To Q1 Propagation Delay QN To QN + 1 Propagation Delay Reset To Q Transition Time SYMBOL VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Reset Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Input Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTND VTP ∆VTPD F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V CIN Any Input NOTES 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25 oC o MIN 7 8 12 - MAX 3 160 130 80 60 120 100 100 80 200 80 60 350 150 100 140 60 40 7.5 UNITS V V ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns pF +25oC +25 C +25 C +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25 oC o o o Maximum Clock Input Frequency Minimum Reset Pulse Width +25oC +25 C +25 oC o +25oC +25 oC +25oC ns 7-362 Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz PART NUMBER CD4020BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 1 - 7, 9, 12 - 15 1 - 7, 9, 12 - 15 1 - 7, 9, 12 - 15 8, 10, 11 8 8, 11 8 16 10, 11, 16 16 10, 11, 16 1 - 7, 9, 12 - 15 10 PART NUMBER CD4024BMS Static Burn-In 1 Note 1 3 - 6, 8 - 13 1, 2, 7 14 7-363 Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued) OSCILLATOR FUNCTION Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 OPEN 3 - 6, 8 - 13 8, 10, 13 3 - 6, 8 - 13 GROUND 7 2, 7 7 VDD 1, 2, 14 14 1, 2, 14 3 - 6, 9, 11, 12 1 9V ± -0.5V 50kHz 25kHz PART NUMBER CD4040BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 1 - 7, 9, 12 - 15 1 - 7, 9, 12 - 15 1 - 7, 9, 12 - 15 8, 10, 11 8 8, 11 8 16 10, 11, 16 16 10, 11, 16 1 - 7, 9, 12 - 15 10 Functional Diagrams VDD 16 10 INPUT PULSES 14 STAGE RIPPLE COUNTER 9 Q1 7 Q4 12 BUFFERED OUTPUTS 5 Q5 4 Q6 6 Q7 13 Q8 12 Q9 14 Q10 15 Q11 1 Q12 2 Q13 3 Q14 1 INPUT PULSES RESET 2 7 STAGE RIPPLE COUNTER 12 Q1 11 Q2 9 Q3 6 Q4 5 Q5 4 Q6 3 Q7 11 RESET 8 VSS NC = 8, 10, 13 7 VSS 8 VSS 7 BUFFERED OUTPUTS VDD 14 10 INPUT PULSES 12 STAGE RIPPLE COUNTER VDD 16 9 Q1 7 Q2 5 Q4 3 Q5 2 Q6 4 Q7 13 Q8 12 Q9 14 Q10 15 Q11 1 Q12 12 BUFFERED OUTPUTS 6 Q3 11 RESET CD4020BMS CD4024BMS CD4040BMS 7-364 CD4020BMS, CD4024BMS, CD4040BMS Logic Diagrams Ø1 Q1 Ø2 Q2 Ø3 Q13 Ø14 Q14 FF14 Ø* R* FF1 Ø1 Q1 R Q1 VDD FF2 Ø2 R FF3 - FF13 Q2 Ø3 Q13 Ø14 Q14 R *INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK Q1 Q4 Q13 Q14 VSS FIGURE 1. LOGIC DIAGRAM FOR CD4020BMS Ø1 Q1 Ø2 Q2 Ø3 Q6 Ø7 Q7 Ø* R* FF1 Ø1 Q1 R Q1 VDD FF2 Ø2 R FF3 - FF6 Q2 Ø3 Q6 FF14 Ø7 R Q7 *INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK Q1 Q2 Q3 Q6 Q7 VSS FIGURE 2. LOGIC DIAGRAM FOR CD4024BMS Ø1 Q1 Ø2 Q2 Ø3 Q11 Ø7 Q12 Ø* R* FF1 Ø1 Q1 R Q1 VDD FF2 Ø2 R FF3 - FF11 Q2 Ø3 Q11 FF12 Ø7 R Q12 *INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK Q1 Q2 Q3 Q11 Q12 VSS FIGURE 3. LOGIC DIAGRAM FOR CD4040BMS 7-365 CD4020BMS, CD4024BMS, CD4040BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100 -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (φ TO Q1) AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 300 200 SUPPLY VOLTAGE (VDD) = 5V SUPPLY VOLTAGE (VDD) = 5V 200 150 100 10V 50 15V 100 10V 15V 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (φ TO Q1)) 7-366 CD4020BMS, CD4024BMS, CD4040BMS Typical Performance Characteristics 105 8 6 4 2 (Continued) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V ∅ p 10V ∅ p R ∅ p n ∅ R POWER DISSIPATION (PD) (µW) * Q1 104 8 6 4 2 n ∅ R ∅ p n ∅ Q 103 10V 8 6 4 2 5V 102 8 6 4 2 CD = 15pF CL = 50pF n ∅ Q 10 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 * ON FIRST STAGE ONLY 1 10 102 103 104 INPUT PULSE FREQUENCY (fφ) (kHz) 105 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT PULSE FREQUENCY FOR CD4020BMS FIGURE 11. DETAIL OF TYPICAL FLIP-FLOP STAGES Chip Dimensions and Pad Layouts Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) DIMENSIONS AND PAD LAYOUT FOR CD4020BMS. DIMENSIONS AND PAD LAYOUT FOR CD4040BMS ARE IDENTICAL DIMENSIONS AND PAD LAYOUT FOR CD4024BMSH METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-367 CD4020BMS, CD4024BMS, CD4040BMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 File Number 368