CD4044BMS

CD4043BMS CD4044BMS December 1992 CMOS Quad 3 State R/S Latches Pinout CD4043BMS TOP VIEW Features • High Voltage Types (20V Rating) • Quad NOR R/S Latch- CD4043BMS • Quad NAND R/S Latch - CD4044BMS • 3 State Outputs with Common Output ENABLE • Separate SET and RESET Inputs for Each Latch • NOR and NAND Configuration • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Q4 1 Q1 2 R1 3 S1 4 ENABLE 5 S2 6 R2 7 VSS 8 16 VDD 15 R4 14 S4 13 NC 12 S3 11 R3 10 Q3 9 Q2 NC = NO CONNECTION CD4044BMS TOP VIEW Q4 1 NC 2 S1 3 R1 4 ENABLE 5 R2 6 S2 7 VSS 8 16 VDD 15 S4 14 R4 13 Q1 12 R3 11 S3 10 Q3 9 Q2 Applications • Holding Register in Multi-Register System • Four Bits of Independent Storage with Output ENABLE • Strobed Register • General Digital Logic • CD4043BMS for Positive Logic Systems • CD4044BMS for Negative Logic Systems NC = NO CONNECTION Description CD4043BMS types are quad cross-coupled 3-state CMOS NOR latches and the CD4044BMS types are quad cross-coupled 3state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the ENABLE input connects the latch states to the Q outputs. A logic “0” or low on the ENABLE input disconnects the latch states from the Q outputs, results in an open circuit feature allows common busing of the outputs. The CD4043BMS and CD4044BMS are supplied in these 16lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4043B Only *H4T †H4T *H1C †HIE *H3X †H6W †CD4044B Only CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3311 7-876 Specifications CD4043BMS, CD4044BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V µA µA µA µA µA µA -55oC o PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +25oC, +125oC, -55oC 14.95 VOH > VOL < VDD/2 VDD/2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-877 Specifications CD4043BMS, CD4044BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 300 405 230 311 180 243 200 270 UNITS ns ns ns ns ns ns ns ns PARAMETER Propagation Delay Set or Reset to Q Propagation Delay 3 - State Enable to Q Propagation Delay 3 - State Enable to Q Transition Time SYMBOL TPHL TPLH TPHZ TPZH TPLZ TPZL TTHL TTLH CONDITIONS VDD = 5V, VIN = VDD or GND (Notes 1, 2) VDD = 5V, VIN = VDD or GND (Notes 2, 3) VDD = 5V, VIN = VDD or GND (Notes 2, 3) VDD = 5V, VIN = VDD or GND (Notes 1, 2) +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 1. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, o MIN - MAX 1 30 2 60 2 120 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA +25oC o +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125 VDD = 15V, VIN = VDD or GND 1, 2 oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 - -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 7-878 Specifications CD4043BMS, CD4044BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage Low Input Voltage High Propagation Delay Set or Reset to Q Propagation Delay 3 State Enable to Q Propagation Delay 3 State Enable to Q Transition Time SYMBOL VIL VIH TPLH TPHL TPHZ TPZH TPLZ TPZL TTHL TTLH TW CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 7.5 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V CIN Any Input NOTES 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25 oC o MIN 7 - MAX 3 140 100 110 80 100 70 100 80 160 80 40 7.5 UNITS V V ns ns ns ns ns ns ns ns ns ns ns pF +25oC +25 C +25 C +25oC +25oC +25oC +25oC +25 C +25oC o o o Minimum Set or Reset Pulse Width ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 0.2µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT 7-879 Specifications CD4043BMS, CD4044BMS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz PART NUMBER CD4043BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 1, 2, 9, 10, 13 1, 2, 9, 10, 13 13 1, 2, 9, 10, 13 3 - 8, 11, 12, 14, 15 8 8 8 16 3 - 7, 11, 12, 14 - 16 5, 16 3 - 7, 11, 12, 14 - 16 1, 2, 9, 12 4, 6, 12, 14 3, 7, 11, 15 PART NUMBER CD4044BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 1, 2, 9, 10, 13 1, 2, 9, 10, 13 2 1, 2, 9, 10, 13 3 - 8, 11, 12, 14, 15 8 8 8 16 3 - 7, 11, 12, 14 - 16 5, 16 3 - 7, 11, 12, 14 - 16 1, 9, 10, 13 4, 6, 12, 14 3, 7, 11, 15 7-880 Specifications CD4043BMS, CD4044BMS Functional Diagram VDD 16 S1 R1 4 3 LATCH 1 R1 2 Q1 S1 3 4 VDD 16 LATCH 1 13 Q1 S2 R2 6 7 LATCH 2 R2 9 Q2 S2 6 7 LATCH 2 9 Q2 S3 R3 12 11 LATCH 3 R3 10 Q3 S3 12 11 LATCH 3 10 Q3 S4 R4 ENABLE 14 15 5 LATCH 4 R4 1 13 Q4 S4 NC ENABLE 14 15 5 LATCH 4 1 2 Q4 NC 8 VSS VSS 8 CD4043BMS CD4044BMS Logic Diagram EQUIVALENT NOR LATCH S1 E VDD S1 EQUIVALENT NAND LATCH E VDD * 4 Q1 2 R1 * 3 Q1 13 R1 * 3 E E E E VDD VSS * 4 E * 5 * 5 E E VDD E VSS *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS VSS CD4043BMS TRUTH TABLE CD4043BMS S X O 1 O 1 R X O O 1 1 E O 1 1 1 1 Q OC* NC** 1 O ∆ S X 1 O 1 O CD4044BMS CD4044BMS R X 1 1 O O E O 1 1 1 1 Q OC* NC** 1 O ∆∆ * Open Circuit ** No Change ∆ Dominated by S = 1 input * Open Circuit ** No Change ∆∆ Dominated by R = O input 7-881 CD4043BMS, CD4044BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 175 150 SUPPLY VOLTAGE (VDD) = 5V 125 100 75 50 15V 25 10V 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 50 15V 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pF) FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - SET, RESET, to Q, Q 7-882 CD4043BMS, CD4044BMS Typical Performance Characteristics POWER DISSIPATION PER DEVICE (PD) (µW) 106 105 104 103 10V 102 5V 10 1 103 104 105 106 107 CL =15pF CL = 50pF 10V SUPPLY VOLTAGE (VDD) = 15V (Continued) AMBIENT TEMPERATURE (TA) = +25oC INPUT FREQUENCY (fI) (kHz) FIGURE 7. TYPICAL POWER DISSIPATION vs FREQUENCY VDD 1MΩ S Q LATCH R 1MΩ VDD CD4044BMS CD4043BMS OUTPUT 1MΩ S Q LATCH R 1MΩ OUTPUT VDD FIGURE 8. SWITCH BOUNCE ELIMINATOR TEST VDD 1 2 3 ENABLE 4 5 6 7 8 16 15 14 13 IN 12 11 10 9 IN 1KΩ A CL = 50pF IN VDD VSS VDD VSS IN VSS VDD VSS VDD A VSS VDD VSS VDD ENABLE 50% tPZH 50% VDD VSS 90% tPHZ 10% 90% 10% ≈ 2/3 VDD ≈ 1/3 VDD ≈ 2/3 VDD ≈ 1/3 VDD tPHZ tPLZ tPZH tPZL Z = HIGH IMPEDANCE POINT A (IN = VDD, IN = VSS) POINT A (IN = VSS, IN = VDD) tPZL tPLZ VSS FIGURE 9. ENABLE PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORM 7-883 CD4043BMS 1 2 5 6 8 9 12 13 CD4001 1 OF 4 3 4 10 11 4 6 12 14 3 7 11 15 CD4043 2 9 10 1 BUS A LOAD A 5 ENABLE A 1 2 5 6 8 9 12 13 CD4001 3 4 10 11 4 6 12 14 3 7 11 15 CD4043 2 9 10 1 3 2 BUS B LOAD B 5 ENABLE B 5 4 OUTPUT DATA BUS 7 6 1 2 5 6 8 9 12 13 CD4001 3 4 10 11 4 6 12 14 3 7 11 15 CD4043 2 9 10 1 9 10 2/3 CD4009 BUS C LOAD C 5 ENABLE C 1 2 5 6 8 9 12 13 CD4001 3 4 10 11 4 6 12 14 3 7 11 15 CD4043 2 9 10 1 BUS D LOAD D 5 ENABLE D RESET FIGURE 10. MULTIPLE BUS STORAGE 7-884 CD4043BMS Chip Dimensions and Pad Layouts CD4043BMSH Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) CD4044BMSH METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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