CD4051

CD4051BMS, CD4052BMS CD4053BMS December 1992 CMOS Analog Multiplexers/Demultiplexers* Description CD4051BMS, CD4052BMS and CD4053BMS analog multiplexers/demultiplexers are digitally controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V peak-topeak can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be controlled; for VDD-VEE level differences above 13V, a VDDVSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0, and VEE = -13.5V, analog signals from 13.5V to +4.5V can be controlled by digital inputs of 0 to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD-VSS and VDD-VEE supply voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal all channels are off. The CD4051BMS is a single 8 channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052BMS is a differential 4 channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053BMS is a triple 2 channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single pole double-throw configuration. The CD4051BMS, CD4052BMS and CD4053BMS are supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4051B Only *H4X H1E H6W †CD4052B, CD4053 Only †H4T Features • Logic Level Conversion • High-Voltage Types (20V Rating) • CD4051BMS Signal 8-Channel • CD4052BMS Differential 4-Channel • CD4053BMS Triple 2-Channel • Wide Range of Digital and Analog Signal Levels: - Digital 3V to 20V - Analog to 20Vp-p • Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal Input Range for VDD - VEE = 15V • High OFF Resistance: Channel Leakage of ±100pA (typ) at VDD - VEE = 18V • Logic Level Conversion: - Digital Addressing Signals of 3V to 20V (VDD - VSS = 3V to 20V) - Switch Analog Signals to 20Vp-p (VDD - VEE = 20V); See Introductory Text • Matched Switch Characteristics: RON = 5Ω (typ) for VDD - VEE = 15V • Very Low Quiescent Power Dissipation Under All Digital Control Input and Supply Conditions: 0.2µW (typ) at VDD - VSS = VDD - VEE = 10V • Binary Address Decoding on Chip • 5V, 10V and 15V Parametric Ratings • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Break-Before-Making Switching Eliminates Channel Overlap Applications • Analog and Digital Multiplexing and Demultiplexing • A/D and D/A Conversion • Signal Gating * When these devices are used as demultiplexers the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3316 7-937 CD4051BMS, CD4052BMS, CD4053BMS Pinouts CD4051BM TOP VIEW CHANNELS IN/OUT 4 6 1 2 16 VDD 15 2 14 1 13 0 12 3 11 A 10 B 9C CHANNELS IN/OUT Y CHANNELS IN/OUT 0 2 1 2 CD4052BMS TOP VIEW 16 VDD 15 2 14 1 X CHANNELS IN/OUT COM OUT/IN 3 CHANNELS IN/OUT 7 5 4 5 COMMON “Y” OUT/IN 3 Y CHANNELS IN/OUT 3 1 4 5 13 COMMON “X” OUT/IN 12 0 11 3 10 A 9B X CHANNELS IN/OUT INH 6 VEE 7 VSS 8 INH 6 VEE 7 VSS 8 CD4053BMS TOP VIEW by IN/OUT bx cy OUT/IN CX or CY IN/OUT CX 1 2 3 4 5 16 VDD 15 OUT/IN bx or by 14 OUT/IN ax or ay 13 ay IN/OUT 12 ax 11 A 10 B 9C INH 6 VEE 7 VSS 8 Functional Diagrams CHANNEL IN/OUT 7 16 VDD 4 6 2 5 5 4 1 3 12 2 15 1 14 0 13 TG * A 11 TG TG * B 10 LOGIC LEVEL CONVERSION * C 9 BINARY TO 1 OF 8 DECODER WITH INHIBIT TG 3 TG COMMON OUT/IN TG * INH 6 TG TG VDD 8 VSS 7 VEE * ALL INPUTS PROTECTED BY STANDARD CMOS PROTECTION NETWORK VSS CD4051BMS 7-938 CD4051BMS, CD4052BMS, CD4053BMS Functional Diagrams (Continued) X CHANNELS IN/OUT 3 11 2 15 1 14 0 12 TG 16 VDD TG TG COMMON X OUT/IN 13 * A 10 LOGIC LEVEL CONVERSION BINARY TO 1 OF 4 DECODER WITH INHIBIT TG TG 3 COMMON Y OUT/IN * B 9 TG * INH 6 TG TG 1 0 8 VSS 7 VEE 5 1 2 2 4 3 Y CHANNELS IN/OUT CD4052BMS VDD * ALL INPUTS PROTECTED BY STANDARD CMOS PROTECTION NETWORK VSS BINARY TO 1 OF 2 DECODERS WITH INHIBIT 16 VDD IN/OUT cy 3 cx 5 by 1 bx 2 ay 13 ax 12 OUT/IN ax or ay 14 TG OUT/IN bx or by 15 TG LOGIC LEVEL CONVERSION TG * A 11 * B 10 TG * C 9 TG OUT/IN cx or cy 4 * INH 6 TG 8 VSS 7 VEE CD4053BMS 7-939 Specifications CD4051BMS, CD4052BMS, CD4053BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V On-State Resistance RL = 10K Returned to VDD - VSS/2 RON VDD = 5V VIS = VSS to VDD 3 1 2 3 1 2 3 1 2 3 VDD = 10V VIS = VSS to VDD 1 2 3 VDD = 15V VIS = VSS to VDD VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Off Channel Leakage Any Channel OFF Or All Channels Off (Common Out/In) VIL VIH VIL VIH IOZL VDD = 5V = VIS thru 1k, VEE = VSS RL = 1k to VSS, |IIS| < 2µA OFF Channels VDD = 15V = VIS thru 1K VEE = VSS RL = 1K to VSS, |ISS|, VOL < VDD/2 VDD/2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 4. VDD = 2.8V/3.0V, RL = 200k to VDD VDD = 20V/18V, RL = 10k to VDD 7-940 Specifications CD4051BMS, CD4052BMS, CD4053BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 720 972 UNITS ns ns PARAMETER Propagation Delay (Note 1) Address to Signal Out Channels On or Off Propagation Delay (Note 1) Inhibit to Signal Out (Channel Turning On) Propagation Delay (Note 1) Inhibit to Signal Out (Channel Turning Off) NOTES: SYMBOL TPHL TPLH CONDITIONS (Notes 1, 2) VDD = 5V, VIN = VDD or GND VEE = VSS = 0V TPZH TPZL VDD = 5V, VIN = VDD or GND VEE = VSS = 0V 9 10, 11 +25oC +125oC, -55oC - 720 972 ns ns TPHZ TPLZ VDD = 5V, VIN = VDD or GND VEE = VSS = 0V 9 10, 11 +25oC +125oC, -55oC - 450 608 ns ns 1. -55oC and +125oC limits guaranteed, 100% testing being implemented. 2. CL = 50pF, RL = 10KΩ, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Input Voltage Low Input Voltage High Propagation Delay Address to Signal Out (Channels On or Off) VIL VIH TPHL TPLH VDD = VIS = 10V, VEE = VSS RL = 1K to VSS |IIS|, 2µA On/Off Channel 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 VEE = VSS = 0V 1, 2, 3 1, 2, 3 1, 2, 3 VEE = VSS = 0V 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25 oC o o MIN +7 - MAX 5 150 10 300 10 600 3 320 240 450 320 240 400 210 160 300 7.5 UNITS µA µA µA µA µA µA V V ns ns ns ns ns ns ns ns ns pF VDD = 10V VDD = 15V VDD = 5V VEE = -5V VEE = VSS = 0V Propagation Delay Inhibit to Signal Out (Channel Turning On) TPZH TPZL VDD = 10V VDD = 15V VDD = 5V VEE = -10V +25oC +25oC +25oC +25oC +25oC +25oC +25oC Propagation Delay Inhibit to Signal Out (Channel Turning Off) TPHZ TPLZ VDD = 10V VDD = 15V VDD = 5V VEE = -15V Input Capacitance NOTES: CIN Any Address or Inhibit Input 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 10K, Input TR, TF < 20ns. 7-941 Specifications CD4051BMS, CD4052BMS, CD4053BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 ON Resistance SYMBOL IDD RONDEL10 ± 1.0µA ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A, RONDEL10 READ AND RECORD IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz PART NUMBER CD4051BMS 7-942 Specifications CD4051BMS, CD4052BMS, CD4053BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 OPEN 3 3 3 GROUND 1, 2, 4 - 6, 7, 8, 9 - 15 7, 8 4 - 6, 7, 8, 9, 12, 14 7, 8 VDD 16 1, 2, 4 - 6, 9 - 16 1, 2, 13, 15, 16 1, 2, 4 - 6, 9 - 16 3 11 10 9V ± -0.5V 50kHz 25kHz PART NUMBER CD4052BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 3, 13 3, 13 3, 13 1, 2, 4 - 6, 7, 8, 9 - 12, 14, 15 7, 8 4 - 6, 7, 8, 12, 15 7, 8 16 1, 2, 4 - 6, 9 - 12, 14 - 16 1, 2, 11, 14, 16 1, 2, 4 - 6, 9 - 12, 14 - 16 3, 13 10 9 PART NUMBER CD4053BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except pin 7 VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except pin 7 VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 4, 14, 15 4, 14, 15 4, 14, 15 1 - 3, 5 - 8, 9 - 13 7, 8 1, 5 - 8, 12 7, 8 16 1 - 3, 5, 6, 9 - 13, 16 2, 3, 13, 16 1 - 3, 5, 6, 9 - 13, 16 4, 14, 15 9 - 11 Typical Performance Characteristics SUPPLY VOLTAGE (VDD - VEE) = 5V CHANNEL ON RESISTANCE (RON) (Ω) CHANNEL ON RESISTANCE (RON) (Ω) 600 500 400 300 200 100 0 -4 -3 -2 -1 0 1 2 3 4 INPUT SIGNAL VOLTAGE (VIS) (V) +25oC -55oC AMBIENT TEMPERATURE (TA) = +125oC 300 250 200 150 100 50 0 -10.0 -7.5 +25oC -55oC AMBIENT TEMPERATURE (TA) = +125oC SUPPLY VOLTAGE (VDD - VEE) = 10V -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE 1. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) FIGURE 2. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 7-943 CD4051BMS, CD4052BMS, CD4053BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD - VEE) = 5V (Continued) CHANNEL ON RESISTANCE (RON) (Ω) CHANNEL ON RESISTANCE (RON) (Ω) SUPPLY VOLTAGE (VDD - VEE) = 15V 300 250 200 150 100 50 0 600 500 400 300 200 AMBIENT TEMPERATURE (TA) = +125oC +25oC -55oC 10V 100 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) 15V -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE 3. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLATGE (ALL TYPES) 6 OUTPUT SIGNAL VOLTAGE (VOS) (V) SUPPLY VOLTAGE (VDD) = 5V VSS = 0V VEE = -5V AMBIENT TEMPERATURE (TA) = +25 2 oC FIGURE 4. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 105 POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) = +25oC ALTERNATING “O” AND “I” PATTERN LOAD CAPICATANCE (CL) = 50pF SUPPLY VOLTAGE (VDD) (15V) TEST CIRCUIT VDD f VDD 100Ω B/D CD4029 LOAD RESISTANCE (RL) = 100kΩ, 10kΩ 1kΩ 1500Ω 100Ω 4 104 ABC 11 10 9 0 103 -2 10V 102 5V CL = 15pF 10 10V -4 13 14 15 CD4051 12 1 5 2 48 7 6 100Ω Ι CL 3 -6 -6 -4 -2 0 2 4 INPUT SIGNAL VOLTAGE (VIS) (V) 6 1 10 103 104 102 SWITCHING FREQUENCY (f) (kHz) 105 FIGURE 5. TYPICAL ON CHARACTERISTICS FOR 1 OF 8 CHANNELS (CD4051BMS) 105 POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) = +25oC ALTERNATING “O” AND “I” PATTERN LOAD CAPICATANCE (CL) = 50pF SUPPLY VOLTAGE (VDD) (15V) TEST CIRCUIT VDD f VDD CD4029 B/D FIGURE 6. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4051BMS) 105 POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) = +25oC ALTERNATING “O” AND “I” PATTERN LOAD CAPICATANCE (CL) = 50pF SUPPLY VOLTAGE (VDD) (15V) TEST CIRCUIT VDD f 100 Ω 100Ω 9 3 5 CD4051 10 11 6 7 Ι 8 105 4 CL 12 13 2 1 15 14 104 104 AB 100Ω 10 9 103 10V 102 5V CL = 15pF 10 1 10 10V 100Ω 1 5 12 2 4 CD4051 14 1 15 6 11 7 8 Ι 3 CL 13 103 10V 102 5V CL = 15pF 10 10V 103 104 102 SWITCHING FREQUENCY (f) (kHz) 105 1 10 103 104 102 SWITCHING FREQUENCY (f) (kHz) FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052BMS) FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4053BMS) 7-944 CD4051BMS, CD4052BMS, CD4053BMS VDD = +15V VDD = +7.5V VDD = +5V VDD = +5V 16 7.5V 16 5V 16 5V 16 VSS = 0V VSS = 0V VEE = 0V 7 8 VSS = 0V VEE = -7.5V 7 8 VEE = -10V 7 8 VSS = 0V 7 VEE = -5V 8 (a) (b) (c) (d) The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD FIGURE 9. TYPICAL BIAS VOLTAGES 7-945 CD4051BMS, CD4052BMS, CD4053BMS TRUTH TABLE INPUT STATES CD4051BMS INHIBIT 0 0 0 0 0 0 0 0 1 CD4052BMS INHIBIT 0 0 0 0 1 CD4053BMS INHIBIT 0 0 1 X = Don’t Care VDD OUTPUT 1 VDD 2 3 4 5 VEE 6 7 8 VSS VSS 16 15 14 13 12 11 10 9 VDD VSS CLOCK IN VSS VSS VEE VEE VEE RL CL CL RL VDD “ON” CHANNEL(S) B 0 0 1 1 0 0 1 1 X A 0 1 0 1 0 1 0 1 X A 0 1 0 1 x 0x, 0y 1x, 1y 2x, 2y 3x, 3y NONE 10% tr = 20ns 90% 90% 50% tf = 20ns C 0 0 0 0 1 1 1 1 X B 0 0 1 1 x 50% 10% 10% TURN-ON TIME 0 1 2 3 4 5 6 7 NONE tPZL 90% 50% 10% TURN-OFF TIME 10% tPLZ FIGURE 10. WAVEFORM, CHANNEL BEING TURNED ON, OFF (RL = 1kΩ) tr = 20ns 90% 50% 90% 50% 10% tf = 20ns 90% 10% TURN-OFF TIME TURN-ON TIME tPZH A OR B OR C 0 1 X ax or bx or cx ay or by or cy NONE tPHZ FIGURE 11. WAVEFORM, CHANNEL BEING TURNED OFF, ON (RL = 1kΩ) OUTPUT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VSS CLOCK IN VDD CD4051 VDD OUTPUT 1 2 3 4 5 VEE 6 7 8 VSS VSS 16 15 14 13 12 11 10 9 VSS CLOCK IN VDD VEE RL CL CD4052 CD4053 FIGURE 12. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT 7-946 CD4051BMS, CD4052BMS, CD4053BMS VDD OUTPUT 1 RL 50pF 2 3 VEE 4 5 VDD VDD VSS CLOCK IN VEE 8 VSS VSS tPHL AND tPLH tPHL AND tPLH 9 6 7 16 15 14 13 12 11 10 VDD VSS CLOCK IN VEE 8 VSS VSS 9 VDD RL 50pF VDD OUTPUT 1 2 3 VEE 4 5 6 7 16 15 14 13 12 11 10 CD4051 CD4052 OUTPUT 1 RL 50pF 2 3 VEE 4 5 VDD VDD VSS CLOCK IN VEE 8 VSS VSS tPHL AND tPLH 9 6 7 16 15 14 13 12 11 10 VDD CD4053 FIGURE 13. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT DIFFERENTIAL SIGNALS CD4052 CD4052 COMMUNICATIONS LINK DIFF AMPLIFIER/ LINE DRIVER DIFF RECEIVER DIFF MULTIPLEXING DEMULTIPLEXING FIGURE 14. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052BMS 7-947 CD4051BMS, CD4052BMS, CD4053BMS Chip Dimensions and Pad Layouts CD4051BMSH CD4052BMSH CD4053BMSH Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 948