CD4095BMS

CD4095BMS CD4096BMS December 1992 CMOS Gated J-K Master-Slave Flip-Flops Pinouts NC 1 RESET 2 J1 3 J2 4 J3 5 Q6 VSS 7 Features • Set-Reset Capability • High Voltage Types (20V Rating) • CD4095BMS Non-Inverting J and K Inputs • CD4096BMS Inverting and Non-Inverting J and K Inputs • 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V • Gated Inputs • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD4095BMS TOP VIEW 14 VDD 13 SET 12 CLOCK 11 K1 10 K2 9 K3 8Q CD4096BMS TOP VIEW NC 1 RESET 2 J1 3 J2 4 J3 5 Q6 VSS 7 14 VDD 13 SET 12 CLOCK 11 K1 10 K2 9 K3 8Q NC = NO CONNECTION Applications • Registers • Counters • Control Circuits SET 3 J1 4 J2 5 J3 12 CLOCK 11 K1 10 K2 9 K3 RESET 13 J CL K 2 Q 6 Q S Q 8 Q Functional Diagrams CD4095BMS Description CD4095BMS and CD4096BMS are J-K Master-Slave FlipFlops featuring separate AND gating of multiple J and K inputs. The gated J-K inputs control transfer of information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation. The CD4095BMS and CD4096BMS are supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP H4Q H1A R VDD = 14 VSS = 7 NC = 1 CD4096BMS SET 3 J1 4 J2 5 J3 12 CLOCK 11 K1 10 K2 9 K3 RESET 13 J CL K 2 Q 6 Q S Q 8 Q R VDD = 14 VSS = 7 NC = 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3331 7-1094 Specifications CD4095BMS, CD4096BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25 oC PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 - MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +125oC -55oC +25o C +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 0.53 1.4 3.5 -2.8 0.7 VOH > VOL < VDD/2 VDD/2 1.5 4 - V V V V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-1095 Specifications CD4095BMS, CD4096BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN o PARAMETER Propagation Delay Clock to Output Propagation Delay Set or Reset to Output Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH FCL CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND MAX 500 675 300 405 200 270 - UNITS ns ns ns ns ns ns MHz MHz +25oC +125 C, -55 C +25oC +125oC, -55oC o 3.5 2.59 Maximum Clock Input Frequency NOTES: +25 C +125oC, -55oC o 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 1 30 2 60 2 120 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA 7-1096 Specifications CD4095BMS, CD4096BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES 1, 2 TEMPERATURE +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Clock to Output Propagation Delay Set or Reset to Output Transition Time VIL VIH TPHL TPLH TPHL TPLH TTHL TTLH FCL VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time TS VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Maximum Clock Input Rise or Fall Time TRCL TFCL VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. CIN Any Input 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC o MIN +7 8 12 - MAX -2.4 -4.2 3 200 150 150 100 100 80 200 100 50 400 160 100 140 60 40 15 5 5 7.5 UNITS mA mA V V ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns µs µs µs pF Maximum Clock Input Frequency Minimum Set or Reset Pulse Width TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD VNTH CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA NOTES 1, 4 1, 4 TEMPERATURE +25oC +25oC MIN -2.8 MAX 7.5 -0.2 UNITS µA V 7-1097 Specifications CD4095BMS, CD4096BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL ∆VTN VTP ∆VTP F CONDITIONS VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC MIN 0.2 VOH > VDD/2 MAX ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 0.2µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 7-1098 Specifications CD4095BMS, CD4096BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION CD4095BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 CD4096BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 1, 6, 8 1, 6, 8 1 1, 6, 8 2-5, 7, 9-13 7 2, 5, 7, 9, 13 7 14 2-5, 9-14 3, 4, 10, 11, 14 2-5, 9-14 6, 8 12 1, 6, 8 1, 6, 8 1 1, 6, 8 2-5, 7, 9-13 7 2, 7, 13 7 14 2-5, 9-14 3-5, 9-11, 14 2-5, 9-14 6, 8 12 OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz 7-1099 CD4095BMS, CD4096BMS Logic Diagram * * * CL 1 CL 1 TG 2 CL CL 1 CL TG CL CL 8Q 2 2 6Q SET 13 J1 3 FOR CD4095BMS J3 5 FOR CD4096BMS J3 5 * * J2 4 TG K1 11 * * 1 CL FOR CD4095BMS J3 9 FOR CD4096BMS J3 9 * * K2 10 2 TG RESET 2 * CL TRANSMISSION GATE IN TG 2 1 OUT CLOCK 12 * CL INPUT TO OUTPUT IS: VDD a) A BIDIRECTIONAL LOW IMPEDANCE WHEN CONTROL INPUT 1 IS “LOW” AND CONTROL INPUT 2 IS “HIGH” b) AN OPEN CIRCUIT WHEN CONTROL INPUT 1 IS “HIGH” AND CONTROL INPUT 2 IS “LOW” *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 1. CD4095BMS AND CD4096BMS LOGIC DIAGRAM TRUTH TABLES SYNCHRONOUS OPERATION (S = 0, R = 0) INPUTS BEFORE POSITIVE CLOCK TRANSITION J* 0 0 1 1 * For CD4095BMS J = J1 • J2 • J3 K = K1 • K2 • K3 K* 0 1 0 1 OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q No Change 0 1 Toggles For CD4096BMS J = J1 • J2 • J3 K = K1 • K2 • K3 Q No Change 1 0 Toggles ASYNCHRONOUS OPERATION (J AND K = Don’t Care) INPUTS BEFORE POSITIVE CLOCK TRANSITION S 0 0 1 1 0 = VSS, 1 = VDD R 0 1 0 1 OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q No Change 0 1 0 Q No Change 1 0 0 7-1100 CD4095BMS, CD4096BMS trCL CLOCK* INPUT tfCL VDD 90% 50% 10% 0 I fCL VDD 90% 50% 10% tWH J OR K GATE INPUTS tSLH Q OR Q OUTPUT tPLH tPHL tTLH tSHL tTHL 50% 0 VDD 90% 50% 10% 0 trCL CLOCK tWL tfCL tWL + tWH = 0 FIGURE 2. PROPAGATION DELAY, TRANSITION, AND SETUP TIME WAVEFORMS FIGURE 3. CLOCK PULSE RISE AND FALL TIME WAVEFORMS VDD VSS 3 4 5 12 13 J S Q CL Q K 2 VSS R CLOCK VDD 11 10 9 D 3 4 5 VSS CLOCK 9 10 11 12 CL Q K 2 VSS R 13 J S Q VSS FIGURE 4. CD4095BMS CONNECTED IN TOGGLE MODE FIGURE 5. CD4096BMS CONNECTED AS A “D” TYPE FLIP-FLOP QA CLOCK INPUT VDD 3 4 5 12 3 4 5 12 QB QC QD J CL Q 8 J CL Q 8 3 4 5 12 J CL Q 8 3 4 5 12 J CL Q 8 CD4095BMS 9 10 11 9 10 11 CD4095BMS 9 10 11 CD4095BMS 9 10 11 CD4095BMS 6 K Q K Q K Q K Q STATE STATE 0 CLOCK QA QB QC QD 1 2 3 4 5 6 7 8 9 0 1 QA 0 1 0 1 0 1 0 1 0 1 QB 0 0 1 1 0 0 1 1 0 0 QC 0 0 0 0 1 1 1 1 0 0 QD 0 0 0 0 0 0 0 0 1 1 0 1 2 3 4 5 6 7 8 9 NOTE: PINS 2 & 13 RESET & SET, GO TO VSS ON ALL UNITS FIGURE 6. SYNCHRONOUS BINARY DIVIDE-BY-TEN COUNTER 7-1101 CD4095BMS, CD4096BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V GATE-TO-SOURCE VOLTAGE (VGS) = 15V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 7. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) 300 250 200 150 SUPPLY VOLTAGE (VDD) = 5V 200 SUPPLY VOLTAGE (VDD) = 5V 150 10V 100 50 15V 100 10V 50 15V 0 25 50 75 100 LOAD CAPACITANCE (CL) (pF) 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 11. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE FIGURE 12. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 7-1102 CD4095BMS, CD4096BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC trl tf = 5ns CL = 50pF (Continued) 106 4 2 2 CLOCK FREQUENCY (fCL) (MHz) 30 25 20 15 10 5 POWER DISSIPATION PER (PD) (µW) AMBIENT TEMPERATURE (TA) = +25oC MAXIMUM PACKAGE DISSIPATION =200mW 105 4 SUPPLY VOLTAGE (VDD) = 15V 104 4 2 4 103 2 10V 10V 4 102 2 10 1 4 2 4 2 5V LOAD CAPACITANCE (CL) = 50pF CL = 15pF 2 46 2 46 0 5 10 15 20 1 10 102 2 46 103 2 46 104 2 46 SUPPLY VOLTAGE (VDD) (V) INPUT FREQUENCY (fIN) (kHz) FIGURE 13. TYPICAL CLOCK FREQUENCY vs SUPPLY VOLTAGE (TOGGLE MODE - SEE FIGURE 4) FIGURE 14. TYPICAL POWER DISSIPATION vs INPUT CLOCK FREQUENCY Chip Dimensions and Pad Layouts CD4095BHMS Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). CD4096BHMS METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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