CD4097BMS

CD4067BMS CD4097BMS December 1992 CMOS Analog Multiplexers/Demultiplexers Pinout CD4067BMS TOP VIEW Features • High Voltage Types (20V Rating) • CD4067BMS Single 16 Channel Multiplexer/Demultiplexer • CD4097BMS Differential 8 Channel Multiplexer/Demultiplexer • Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal Input Range for VDD - VSS = 15V • High OFF Resistance: Channel Leakage of ±10pA (typ) at VDD - VSS = 18V • Matched Switch Characteristics: RON = 5Ω (typ) for VDD - VSS = 15V • Very Low Quiescent Power Dissipation Under All Digital Control Input and Supply Conditions: 0.2µW (typ) at VDD - VSS = 10V • Binary Address Decoding on Chip • 5V, 10V and 15V Parametric Ratings • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Standardized Symmetrical Output Characteristics COMMON OUT/IN 1 72 63 54 45 24 VDD 23 8 22 9 21 10 20 11 19 12 18 13 17 14 16 15 15 INHIBIT 14 C 13 D * 36 27 18 09 A 10 B 11 * * CHANNEL IN/OUT VSS 12 Applications • Analog and Digital Multiplexing and Demultiplexing • A/D and D/A Conversion • Signal Gating * When these devices are used as demultiplexers the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. COMMON X OUT/IN 1 72 63 54 CHANNEL X IN/OUT 45 36 27 18 09 A 10 B 11 VSS 12 24 VDD 23 0 22 1 21 2 20 3 19 4 18 5 17 COMMON Y OUT/IN 16 6 Y CHANNEL 15 7 14 C 13 INHIBIT IN/OUT Y CHANNEL IN/OUT CD4097BMS TOP VIEW Description CD4067BMS and CD4097BMS CMOS analog multiplexers/ demultiplexers* are digitally controlled analog switches having low ON Impedance, low OFF leakage current, and internal address decoding. In addition, the ON resistance is relatively constant over the full input-signal range. The CD4067BMS is a 16 channel multiplexer with four binary control inputs, A, B, C, D and an inhibit input, arranged so that any combination of the inputs selects one switch. The CD4097BMS is a differential 8 channel multiplexer having three binary control inputs A, B, C and an inhibit input. The inputs permit selection of one of eight pairs of switches. A logic “1” present at the inhibit input turns all channels off. The CD4067BMS and CD4097BMS are supplied in these 24 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4067B Only *H4V †H6M *H1Z †HFN *H4P †H4P †CD4097B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3190 7-1 Specifications CD4067BMS, CD4097BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V ON-State Resistance RL = 10K Returned to VDD - VSS/2 RON VDD = 5V VIS = VSS to VDD 3 1 2 3 VDD = 10V VIS = VSS to VDD 1 2 3 VDD = 15V VIS = VSS to VDD 1 2 3 N Threshold Voltage P Threshold Voltage Functional (Note 4) VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VDD = 5V = VIS Thru 1K VEE = VSS RL = 1K to VSS |ISS| < 2µA on all OFF Channels VDD = 15V = VIS Thru 1K VEE = VSS RL = 1K to VSS |ISS| < 2µA on all OFF Channels 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25 oC PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 -2.8 0.7 MAX 10 1000 10 100 1000 100 1050 1300 800 400 500 310 240 320 220 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA Ω Ω Ω Ω Ω Ω Ω Ω Ω V V V +125oC -55oC +25o C +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC VOH > VOL < VDD/2 VDD/2 3.5 1.5 - V V VIL VIH 1, 2, 3 1, 2, 3 +25oC, +125oC, -55oC +25oC, +125oC, -55oC 11 4 - V V 7-2 Specifications CD4067BMS, CD4097BMS TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V IOZH VOUT = VDD VDD = 20V 3 1 2 VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC MIN -0.1 -1.0 -0.1 MAX 0.1 1.0 0.1 UNITS µA µA µA µA µA µA PARAMETER OFF Channel Leakage Any Channel OFF or All Channels OFF (Common OUT/IN) SYMBOL IOZL CONDITIONS (NOTE 1) VOUT = 0V VDD = 20V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 4. VDD = 2.8/3.0V, RL = 200K VDD = 20V/18V, RL = 10K - 25K TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX 60 81 650 878 UNITS ns ns ns ns PARAMETER Propagation Delay (Signal In to Output) Propagation Delay Address or Inhibit to Signal Out. (Channel Turning On) NOTES: SYMBOL TPHL TPLH TPZH TPZL CONDITIONS VDD = 5V, VIN = VDD or GND (Notes 1, 2) VDD = 5V, VIN = VDD or GND (Notes 2, 3) 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 10K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, -55oC, +25oC +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Input Voltage Low Input Voltage High VIL VIH VDD = VIS = 10V VEE = VSS RL = 1K to VSS IIS < 2µA ON OFF Channel VDD = 10V VDD = 15V 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +7 V MIN MAX 5 150 10 300 10 600 3 UNITS µA µA µA µA µA µA V Propagation Delay Address or Inhibit to Signal Out. (Channel Turning On) Propagation Delay Signal In to Output TPZH TPZL 1, 2, 4 1, 2, 4 - 270 190 ns ns TPHL TPLH VDD = 10V VDD = 15V VIS = VDD or GND 1, 2, 3 1, 2, 3 +25oC +25oC - 30 20 ns ns 7-3 Specifications CD4067BMS, CD4097BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Address or Inhibit to Signal Out (Channel Turning Off) Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 10K, Input TR, TF < 20ns. 5. CL = 50pF, RL = 300Ω, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25o C MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V SYMBOL TPHZ TPLZ CONDITIONS VDD = 5V VDD = 10V VDD = 15V CIN Any Address or Inhibit NOTES 1, 2, 5 1, 2, 5 1, 2, 5 1, 2 TEMPERATURE +25oC +25 C +25oC +25 C o o MIN - MAX 440 180 130 7.5 UNITS ns ns ns pF +25oC +25 C +25oC +25 C +25oC o o ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 ON Resistance SYMBOL IDD RONDEL10 ± 1.0µA ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 IDD, IOL5, IOH5A, RONDEL10 READ AND RECORD IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 7-4 Specifications CD4067BMS, CD4097BMS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 READ AND RECORD NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION PART NUMBER CD4067BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic Burn-In Note 1 Irradiation Note 2 PART NUMBER CD4097BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic Burn-In Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 3. Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 13 is at 1.7kHz, Pin 14 is at 3.5kHz 4. Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 14 is at 3.5kHZ 1, 17 1, 17 1, 17 2 - 16, 18 - 23 12 12, 13 12 24 2 - 11, 13 - 16, 18 - 24 24 2 - 11, 13 - 16, 18 - 24 1, 17 2 - 9, 15, 16, 18 - 23 10, 11, 14 (Note 4) 1 1 1 2 - 23 12 12, 15 12 24 2 - 11, 13 - 24 24 2 - 11, 13 - 24 1 2 - 9, 16 - 23 10, 11, 13, 14 (Note 3) OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz 7-5 CD4067BMS, CD4097BMS Functional Diagram INHIBIT 3 INHIBIT 4 1 of 16 DECODERS X IN/OUT 0 1 IN/OUT 15 VDD = 24 VSS = 12 OUT/IN VDD = 24 VSS = 12 Y IN/OUT 7 0 1 Y OUT/IN 0 1 X OUT/IN 1 of 8 DECODERS 7 CD4067 CD4067 TRUTH TABLE A X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inh 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELECTED CHANNEL None 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 10% tPZL 90% 50% 10% tr = 20ns 90% 50% CD4097 CD4097 TRUTH TABLE A X 0 1 0 1 0 1 0 1 B X 0 0 1 1 0 0 1 1 C X 0 0 0 0 1 1 1 1 Inh 1 0 0 0 0 0 0 0 0 SELECTED CHANNEL None 0X, 0Y 1X, 1Y 2X, 2Y 3X, 3Y 4X, 4Y 5X, 5Y 6X, 6Y 7X, 7Y tf = 20ns 90% 50% 10% TURN-ON TIME 10% tPLZ TURN-OFF TIME FIGURE 1. WAVEFORM CHANNEL BEING TURNED ON, OFF tr = 20ns 90% 50% 10% 90% 50% 10% tf = 20ns 90% 10% TURN-ON TIME tPZH tPHZ TURN-OFF TIME FIGURE 2. PROPAGATION DELAY WAVEFORM, CHANNEL BEING TURNED OFF, ON 7-6 CD4067BMS, CD4097BMS 16 CHANNEL IN/OUT VDD 24 15 16 14 17 13 18 12 19 11 20 10 21 9 22 8 23 7 2 6 3 5 4 4 5 3 6 2 7 1 8 0 9 TG TG TG TG TG TG * * * * * 10 A 11 B 14 C 13 D 15 BINARY 1 OF 16 DECODERS WITH INHIBIT TG TG 1 TG COMMON OUT/IN TG INHIBIT TG TG TG TG TG TG VDD 12 VSS *ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 3. CD4067BMS LOGIC DIAGRAM 7-7 CD4067BMS, CD4097BMS VDD 24 7 15 6 16 5 18 8 CHANNEL IN/OUT Y 4 3 19 20 2 21 1 22 0 23 7 2 6 3 5 4 8 CHANNEL IN/OUT X 4 3 5 6 2 7 1 8 0 9 TG TG TG TG 1 TG COMMON X OUT/IN TG * * * * 10 A 11 B 14 C 13 BINARY 1 OF 8 DECODERS WITH INHIBIT TG TG TG INHIBIT TG TG TG 17 TG COMMON Y OUT/IN TG TG TG VDD 12 VSS *ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS FIGURE 4. CD4097BMS LOGIC DIAGRAM 7-8 CD4067BMS, CD4097BMS Typical Performance Characteristics SUPPLY VOLTAGE (VDD - VSS) = 5V CHANNEL ON RESISTANCE (RON) (Ω) CHANNEL ON RESISTANCE (RON) (Ω) 600 500 400 300 200 100 0 -4 -3 -2 -1 0 1 2 3 4 INPUT SIGNAL VOLTAGE (VIS) (V) +25oC -55oC AMBIENT TEMPERATURE (TA) = +125oC 300 250 200 150 100 50 0 -10.0 -7.5 +25oC -55oC AMBIENT TEMPERATURE (TA) = +125oC SUPPLY VOLTAGE (VDD - VSS) = 10V -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE 5. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) FIGURE 6. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) CHANNEL ON RESISTANCE (RON) (Ω) CHANNEL ON RESISTANCE (RON) (Ω) 600 500 400 300 200 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD - VSS) = 5V SUPPLY VOLTAGE (VDD - VSS) = 15V 300 250 200 150 100 50 0 AMBIENT TEMPERATURE (TA) = +125oC +25oC -55oC 10V 100 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) 15V -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE 7. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) FIGURE 8. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 7-9 CD4067BMS, CD4097BMS Chip Dimensions and Pad Layouts CD4067BMSH Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) CD4097BMSH Special Considerations In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4067BMS or CD4097BMS. When switching from one address to another, some of the ON periods of the channels of the multiplexers will overlap momentarily, which may be objectionable in certain applications. Also when a channel is turned on or off by an address input, there is a momentary conductive path from the channel to VSS, which will dump some charge from any capacitor connected to the input or output of the channel. The inhibit input turning on a channel will similarly dump some charge to VSS. The amount of charge dumped is mostly a function of the signal level above VSS. Typically, at VDD - VSS = 10V, a 100pF capacitor connected to the input or output of the channel will lose 3 to 4% of its voltage at the moment the channel turns on or off. This loss of voltage is essentially independent of the address or inhibit signal transition time, if the transition time is less than 1 - 2µs. When the inhibit signal turns a channel off, there is no charge dumping to VSS. Rather, there is a slight rise in the channel voltage level (65mV typ.) due to capacitive coupling from inhibit input to channel input or output. Address inputs also couple some voltage steps onto the channel signal levels. In certain applications, the external load resistor current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.8 volt (calculated from RON values shown in ELECTRICAL CHARACTERISTICS CHART - Table 1). no VDD current will flow through RL if the switch current flows into terminal 1 on the CD4067BMS, terminals 1 and 17 on the CD4097BMS. METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 10