CD4099BMS

CD4099BMS December 1992 CMOS 8-Bit Addressable Latch Pinout CD4099BMS TOP VIEW Features • High Voltage Type (20V Rating) • Serial Data Input • Active Parallel Output Q7 1 2 16 VDD 15 Q6 14 Q5 13 Q4 12 Q3 11 Q2 10 Q1 9 Q0 • Storage Register Capability • Master Clear • Can Function as Demultiplexer • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” RESET DATA 3 WRITE DISABLE A0 A1 A2 VSS 4 5 6 7 8 Functional Diagram Applications • Multi-Line Decoders • A/D Converters A0 A1 WRITE DISABLE DATA 5 4 3 9 10 11 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8 6 7 DECODER 8 LATCHES 12 13 14 15 Description CD4099BMS 8-bit addressable latch is a serial input, parallel output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic “0” level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1 of 8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic “0” level. The CD4099BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W A2 RESET VDD = 16 VSS = 8 2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3333 7-494 Specifications CD4099BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25 oC PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 - MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +125oC -55oC +25o C +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 0.53 1.4 3.5 -2.8 0.7 VOH > VOL < VDD/2 VDD/2 1.5 4 - V V V V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-495 Specifications CD4099BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TPHL4 TPLH4 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 400 540 400 540 350 473 450 608 200 270 UNITS ns ns ns ns ns ns ns ns ns ns PARAMETER Propagation Delay Data to Output Propagation Delay Write Disable to Output Propagation Delay Reset to Output Propagation Delay Address to Output Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC 7-496 Specifications CD4099BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES 1, 2 TEMPERATURE +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Data to Output Propagation Delay Write Disable to Output Propagation Delay Reset to Output Propagation Delay Address to Output Transition Time VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TPHL4 TPLH4 TTHL TTLH TH VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time Data to Write Disable Minimum Pulse Width Data TS VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Minimum Pulse Width Address TW VDD = 5V VDD = 10V VDD = 15V Minimum Pulse Width Reset TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. CIN Any inputs 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25 C +25 C +25oC +25 C +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC o o o o o MIN +7 - MAX -2.4 -4.2 3 150 100 160 120 160 130 200 150 100 80 150 75 50 100 50 35 200 100 80 400 200 125 150 75 50 7.5 UNITS mA mA V V ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns pF Minimum Hold time Data to Write Disable TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD VNTH CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA NOTES 1, 4 1, 4 TEMPERATURE +25oC +25oC MIN -2.8 MAX 25 -0.2 UNITS µA V 7-497 Specifications CD4099BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL ∆VTN VTP ∆VTP F CONDITIONS VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC MIN 0.2 VOH > VDD/2 MAX ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 7-498 Specifications CD4099BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 1, 9-15 1, 9-15 1, 9-15 GROUND 2-8 8 5-8 8 VDD 16 2-7, 16 16 2-7, 16 1, 9-15 2, 4 3 9V ± -0.5V 50kHz 25kHz Logic Diagram A0 5* A0 A0 A0 A1 6* A1 A1 A2 7* A1 A2 A2 DATA 3* D A1 A2 WD A0 A1 RESET 2* A2 R A0 A1 A2 R ADDRESS WD A0 A1 A2 D WD R LATCH 7 D WD R LATCH 6 D WD R LATCH 5 D WD R LATCH 4 A2 A0 A1 A2 A0 WRITE DISABLE 4* D WD R LATCH 3 D WD R LATCH 2 A1 A2 A0 D WD R LATCH 1 A1 A2 A0 D WD R LATCH 0 9 Q0 10 Q1 11 Q2 12 Q3 13 Q4 14 Q5 15 Q6 1 Q7 p DATA n Q VDD p n VSS = 8 VDD = 16 VSS *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 7-499 CD4099BMS MODE SELECTION A0 70% 30% 70% 30% WD 0 0 R 0 1 ADDRESSED LATCH Follows Data Follows Data UNADDRESSED LATCH Holds Previous State Reset to “0” A1 A2 (Active High 8-Channel Demultiplexer) 70% tW 1 1 0 1 Holds Previous State Reset to “0” R = Reset Reset to “0” WD WD = Write Disable FIGURE 2. DEFINITION OF WRITE DISABLE ON TIME A0, A1, A2 tW 8 WRITE DISABLE 4 DATA tW tS 6 tW 5 Q0 tP 2 tP 9 Q7 tP tP 1 tP tP 3 tP tH 7 RESET Q7 FIGURE 3. MASTER TIMING DIAGRAM A0 A1 A2 A3 DATA IN 5 6 7 4 3 A0 A1 CD4099BMS A2 WD DATA Q0 Q1 Q2 Q3 Q4 Q5 Q6 R 2 VDD Q7 9 10 11 12 13 14 15 1 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7 DO 8 DATA CD4099BMS Q0 D Q1 Y 1/4 CD4016 IN/OUT 0 1 2 3 0 S0 WD R CD4099BMS D S5 S1 S2 1 X IN/OUT 2 5 6 7 A0 A1 CD4099BMS A2 WD DATA Q0 Q1 Q2 Q3 Q4 Q5 Q6 R 2 VDD Q7 9 10 11 12 13 14 15 1 DO 9 DO 10 DO 11 DO 12 DO 13 DO 14 DO 15 DO 16 A0 A1 A2 A3 * *1/6 CD4069 4 3 WD WD WD R Q15 3 FIGURE 4. 1 OF 16 DECODER/DEMULTIPLEXER FIGURE 5. MULTIPLE SELECTION DECODING - 4 x 4 CROSSPOINT SWITCH 7-500 CD4099BMS VDD t2 5 4 AST C 1 7 8 9 12 6 14 2 9 10 15 16 CD4520 Q2A 4 6 A1 Q3A 5 7 A2 2 R 7 VDD CD4047 R 2 330Ω 100 kΩ OSC 13 OUT R-C 3 1 CLOCK Q1A 3 5 4 3 8 9 A0 470pF (t1 < t2) t1 START CONVERSION WD CD4099BMS R DATA Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 10 11 12 13 14 15 1 * 10 1 2 LSB * 3 12 13 5 6 * VDD 11 CD4099BMS OUTPUTS TO DISPLAY * 4 7 10kΩ + 3 1 2 OUT 8 56pF 10kΩ 16 R2R LADDER NETWORK** 9 10 11 12 13 2 3 4 5 6 7 8 MSB 6 4 CA3130 5 1 100 kΩ * CD4001 ** HYCOMP HC210SLD-2R OR EQUIVALENT ANALOG IN FIGURE 6. A/D CONVERTER Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 7. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-501 CD4099BMS Typical Performance Characteristics DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 (Continued) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) 300 250 200 150 100 50 15V 0 10 20 30 40 50 60 70 80 90 100 10V 200 SUPPLY VOLTAGE (VDD) = 5V SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 50 5V LOAD CAPACITANCE (CL) (pF) 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 11. TYPICAL PROPAGATION DELAY TIME (DATA TO Qn) vs LOAD CAPACITANCE POWER DISSIPATION PER GATE (PD) (µW) 6 4 2 FIGURE 12. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL ) = 15pF CL = 50pF 105 6 4 2 104 6 103 4 2 6 4 2 4 2 SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V 102 6 101 100 6 4 2 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 100 101 102 103 ADDRESS CYCLE TIME (µs) 104 105 FIGURE 13. TYPICAL DYNAMIC POWER DISSIPATION vs ADDRESS CYCLE TIME 7-502 CD4099BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 File Number 503