CD4516BMS

CD4510BMS, CD4516BMS Data Sheet December 1992 File Number 3338 CMOS Presettable Up/Down Counters CD4510BMS Presettable BCD Up/Down Counter and the CD4516BMS Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510BMS will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. If the CARRY IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY OUT of a less significant stage to the CARRY IN of a more significant stage. The CD4510BMS and CD4516BMS can be cascaded in the ripple mode by connecting the CARRY OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Figures 13, 14.) These devices are similar to types MC14510 and MC14516. The CD4510BMS and CD4516BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4510B Only *H4W †H45 *FBF †H1F H6W †CD4516B Only Features • High Voltage Types (20V Rating) • CD4510BMS - BCD Type • CD4516BMS - Binary Type • Medium Speed Operation - fCL = 8MHz Typ. at 10V • Synchronous Internal Carry Propagation • Reset and Preset Capability • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Up/Down Difference Counting • Multistage Synchronous Counting • Multistage Ripple Counting • Synchronous Frequency Dividers Pinout CD4510BMS, CD4516BMS TOP VIEW Functional Diagram PRESET ENABLE 1 P1 P2 P3 P4 4 12 13 3 6 11 14 2 Q1 Q2 Q3 Q4 PRESET ENABLE Q4 P4 P1 CARRY IN Q1 CARRY OUT VSS 1 2 3 4 5 6 7 8 16 VDD 15 CLOCK 14 Q3 13 P3 12 P2 11 Q2 CLOCK 10 UP/DOWN 9 RESET UP/DOWN CARRY IN 15 10 5 7 CARRY OUT 9 RESET VDD = 16 VSS = 8 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4510BMS, CD4516BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance. . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VOH > VOL < VDD/2 VDD/2 NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 2 CD4510BMS, CD4516BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND (Note 3) VDD = 5V, VIN = VDD or GND 9 10, 11 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 1.48 MAX 400 540 420 567 480 648 250 338 640 864 200 270 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to Q Output Propagation Delay Preset or Reset to Q Propagation Delay Clock to Carry Out Propagation Delay Carry In to Carry Out Propagation Delay Preset or Reset to Carry Out Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 TTHL TTLH FCL CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. Reset to Carry Out (TPLH) only. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA 3 CD4510BMS, CD4516BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH5B CONDITIONS VDD = 5V, VOUT = 2.5V NOTES 1, 2 TEMPERATURE +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Clock to Q Output Propagation Delay Preset or Reset to Q Propagation Delay Clock to Carry Out Propagation Delay Carry In to Carry Out Propagation Delay Preset or Reset to Carry Out Transition Time VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 TTLH TTHL FCL VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TH VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time Preset Enable to JN TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time Clock to Carry In TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Hold Time Clock to Up/Down TH VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Reset to Carry Out (TPLH) only. CIN Any Input 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN +7 4 5.5 MAX -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 200 150 210 160 240 180 120 100 320 250 100 80 70 40 40 25 10 10 60 30 30 30 30 30 7.5 UNITS mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns pF Maximum Clock Input Frequency Minimum Hold Time Preset Enable to JN 4 CD4510BMS, CD4516BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 5 CD4510BMS, CD4516BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION CD4510BMS Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic BurnIn (Note 1) Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 2, 6, 7, 11, 14 2, 6, 7, 11, 14 2, 6, 7, 11, 14 1, 3-5, 8-10, 12, 13, 15 8 1, 3, 4, 8, 9, 12, 13 8 16 1, 3-5, 9, 10, 12, 13, 15, 16 10, 16 1, 3-5, 9, 10, 12, 13, 15, 16 2, 6, 7, 11, 14 15 5 OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz Logic Diagrams P1* 4 RESET* 9 Q1 6 P2* 12 Q2 11 P3* 13 Q3 14 P4* 3 Q4 2 PRESET* ENABLE CLOCK* CARRY OUT 1 15 7 C T P PE Q P PE Q C Q Q1 T Q Q2 Q2 P PE Q C T Q Q3 Q3 P PE Q C T Q Q4 Q4 CARRY IN* UP/DOWN* 5 10 U/D U/D Q1 VDD U/D U/D Q3 Q4 Q2 Q4 U/D Q3 U/D U/D Q2 Q2 Q4 U/D Q3 Q2 Q3 Q2 U/D Q3 Q4 * VSS ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK FIGURE 1. CD4510BMS 6 CD4510BMS, CD4516BMS Logic Diagrams (Continued) P1* 4 RESET* 9 Q1 6 P2* 12 Q2 11 P3* 13 Q3 14 P4* 3 Q4 2 PRESET* ENABLE CLOCK* CARRY OUT 1 15 7 C T P PE Q P PE Q C Q Q1 T Q Q2 Q2 P PE Q C T Q Q3 Q3 P PE Q C T Q Q4 Q4 CARRY IN* UP/DOWN* 5 10 U/D U/D Q1 VDD U/D Q3 U/D Q3 Q2 Q4 Q2 Q4 U/D U/D Q2 Q2 U/D Q3 Q2 Q2 U/D Q3 * VSS ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK FIGURE 2. CD4516BMS TRUTH TABLE CL X CI 1 0 0 X X X X U/D X 1 0 X X PE 0 0 0 1 X R 0 0 0 0 1 ACTION NO COUNT COUNT UP COUNT DOWN PRESET RESET X = DON’T CARE 7 CD4510BMS, CD4516BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTLH) (ns) FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC 250 200 SUPPLY VOLTAGE (VDD) = 5V 200 SUPPLY VOLTAGE (VDD) = 5V 150 150 10V 100 15V 100 10V 50 15V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE FOR CLOCK-TO-Q OUTPUTS 8 CD4510BMS, CD4516BMS Typical Performance Characteristics MAXIMUM CLOCK INPUT FREQUENCY (fCL MAX) (MHz) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF (Continued) POWER DISSIPATION PER GATE (PD) (µW) 104 AMBIENT TEMPERATURE (TA) 15 8 = +25oC 6 4 tr, tf = 20ns 2 103 8 6 4 2 SUPPLY VOLTS (VDD) = 15V 10V 10V 5V 10 102 8 6 4 2 5 CL = 50pF CL = 15pF 10 0 5 10 15 20 01 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 SUPPLY VOLTAGE (VDD) 1 10 102 103 INPUT FREQUENCY (fCL) (kHz) 104 FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs SUPPLY VOLTAGE FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY Test Circuit and Waveform 100µF 1 2 3 4 CL 5 6 CL CL 7 8 16 15 14 13 CL 12 11 10 9 CL 50% 10% VARIABLE WIDTH VSS PULSE GENERATOR 20ns 90% 20ns VDD ID 500µF FIGURE 11. POWER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM Acquisition System SAMPLE AND HOLD START CLOCK CONVERSION LOGIC SELECT INPUTS END AMPLIFIER ANALOG DATA INPUTS 16 CHANNEL MULTIPLEXER CD4067 10 BIT A/D CONVERTER PARALLEL DATA OUTPUTS Q1 PRESET INPUTS Q4 CD4516BMS NOTE: This acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the CD4516BMS. CLOCK PRESET ENABLE FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM 9 CD4510BMS, CD4516BMS Timing Diagrams CLOCK CARRY IN UP/DOWN RESET PE P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0 FIGURE 13. CD4510BMS CLOCK CARRY IN UP/DOWN RESET PE P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 5 6 7 8 9 10 11 12 13 14 15 9 8 7 6 5 4 3 2 1 0 0 15 0 VDD VSS FIGURE 14. CD4516BMS 10 CD4510BMS, CD4516BMS PARALLEL CLOCKING UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 CI R CLOCK RESET CD4510/16BMS CO CL Q1 Q2 Q3 Q4 UP/D PE J1 J2 J3 J4 CI R CD4510/16BMS CO CL Q1 Q2 Q3 Q4 UP/D PE J1 J2 J3 J4 CI R CD4510/16BMS CO CL Q1 Q2 Q3 Q4 * * CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edgesensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as CD4071BMS. RIPPLE CLOCKING UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 CI R CD4510/16BMS CO CL Q1 Q2 Q3 Q4 UP/D PE J1 J2 J3 J4 CI R CD4510/16BMS CO CL Q1 Q2 Q3 Q4 UP/D PE J1 J2 J3 J4 CI R CD4510/16BMS CO CL Q1 Q2 Q3 Q4 CLOCK RESET 1/4 CD4071B Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded. FIGURE 15. CASCADING COUNTER PACKAGES All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 11