CD4517BMS

CD4517BMS December 1992 CMOS Dual 64-Stage Static Shift Register Description CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the opeation of the CD4517BMS. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus. The CD4517BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6P Features • High-Voltage Types (20-Volt Rating) • Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V • Clock Frequency 12MHz (Typ.) at VDD = 10V • Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock Rise and Fall Times • Capable of Driving Two Low-power TTL Loads, One Low-power Schottky TTL Load, or Two HTL Loads • 3-State Outputs • 100% Tested for Quiescent Current at 20V • Standardized, Symmetrical Output Characteristics • 5V, 10V, and 15V Parametric Ratings • Meets all Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ‘B’ Series CMOS Devices" Applications • Time-delay Circuits • Scratch-pad Memories • General-purpose Serial Shift-register Applications Pinout CD4517BMS TOP VIEW Q16A 1 Q48A 2 WEA 3 CLA 4 Q64A 5 Q32A 6 DA 7 VSS 8 16 VDD 15 Q16B 14 Q48B 13 WEB 12 CLB 11 Q64B 10 Q32B 9 DB Functional Diagram CL CL Q16 D D1 16 STAGES WE = 0 CL Q32 D17 16 STAGES WE = 1 CL Q48 D33 16 STAGES CL Q64 D49 16 STAGES WE STAGE 16 OUT/IN TAP STAGE32 OUT/IN TAP STAGE 48 OUT/IN TAP STAGE 64 OUT/IN TAP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3341 7-1197 Specifications CD4517BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V µA µA µA µA µA µA -55oC o PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +25oC, +125oC, -55oC 14.95 VOH > VOL < VDD/2 VDD/2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-1198 Specifications CD4517BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN 3 2.22 MAX 400 540 200 270 UNITS ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to 16 Transition Time SYMBOL TPHL TPLH TTHL TTLH FCL CONDITIONS (Note 1, 2) VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC Maximum Clock Input Frequency NOTES: +25oC +125oC, -55oC 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC oC o o MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 +7 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 - UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V +125 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 Input Voltage Low Input Voltage High VIL VIH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V 1, 2 1, 2 7-1199 Specifications CD4517BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Clock to Q16 Propagation Delay 3-State WE to Q16 SYMBOL TPHL TPLH CONDITIONS VDD = 10V VDD = 15V NOTES 1, 2, 3 1, 2, 3 1, 2, 5 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3, 5 1, 2 TEMPERATURE +25oC +25 C +25oC +25 oC o MIN 6 8 0 0 0 - MAX 220 180 150 80 60 100 80 20 10 10 200 100 50 180 80 50 100 50 40 15 5 5 7.5 UNITS ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs µs pF TPHZ, ZH VDD = 5V TPLZ, ZL VDD = 10V VDD = 15V +25oC +25oC +25oC +25o C +25oC +25 oC Transition Time TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V Maximum Clock Input Frequency Minimum Data to Clock Setup Time TS VDD = 5V VDD = 10V VDD = 15V +25oC +25 C +25o C +25oC +25oC +25 oC o Minimum Data to Clock Hold Time TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V +25oC +25 C +25 oC o Minimum Write Enable to-Clock Release Time TR VDD = 5V VDD = 10V VDD = 15V +25oC +25 oC Write Enable-to-Clock Setup Time TS VDD = 5V VDD = 10V VDD = 15V +25oC +25oC +25 oC Maximum Clock Input Rise and Fall Time TRCL TFCL VDD = 5V VDD = 10V VDD = 15V +25oC +25oC +25oC +25 C o Input Capacitance NOTES: CIN Any Input 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Measured at the point of 10% change in output with an output load 50pF, RL = 1KΩ to VDD for TPZL and TPLZ and RL = 1KΩ to VSS for TPZH and TPHZ 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage SYMBOL IDD VNTH ∆VTN VTP CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA NOTES 1, 4 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC +25oC MIN -2.8 0.2 MAX 25 -0.2 ±1 2.8 UNITS µA V V V 7-1200 Specifications CD4517BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER P Threshold Voltage Delta Functional SYMBOL ∆VTP F CONDITIONS VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1 TEMPERATURE +25oC +25oC MIN VOH > VDD/2 MAX ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic BurnIn (Note 1) OPEN 1, 2, 5, 6, 10, 11, 14, 15 1, 2, 5, 6, 10, 11, 14, 15 GROUND 3, 4, 7-9, 12, 13 8 3, 8, 13 VDD 16 3, 4, 7, 9, 12, 13, 16 16 1, 2, 5, 6, 10, 11, 14, 15 4, 12 7, 9 9V ± -0.5V 50kHz 25kHz 7-1201 Specifications CD4517BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued) OSCILLATOR FUNCTION Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 1, 2, 5, 6, 10, 11, 14, 15 GROUND 8 VDD 3, 4, 7, 9, 12, 13, 16 9V ± -0.5V 50kHz 25kHz Logic Diagram CL * CL CL 17 DQ CL CL 31 DQ D * CL CL 1 DQ CL CL 2 DQ CL CL 15 DQ CL CL 16 DQ Q16* WE p n WE WE p n WE VDD WE WE * WE WE WE VSS VDD VDD CL CL 32 D SAME AS STAGES Q32* 16 WE WE Q VSS VSS CL CL 33 DQ CL CL 47 DQ CL CL 48 D SAME AS STAGES Q48* 16 & 32 WE WE Q CL CL 49 DQ CL CL 63 DQ CL CL 64 D SAME AS STAGES WE 16, 32, 48 EXCEPT WE FOR Q* Q Q64* * All inputs protected by CMOS protection network. Q32* Q48* FIGURE 1. LOGIC BLOCK DIAGRAM TRUTH TABLE CLOCK 0 0 1 1 WRITE ENABLE 0 1 0 1 0 1 0 1 1 = HIGH LEVEL 0 = LOW LEVEL DATA X X X X DI In DI In X X STAGE 16 TAP Q16 Z Q16 Z Q16 D17 In Q16 Z STAGE 32 TAP Q32 Z Q32 Z Q32 D33 In Q32 Z STAGE 48 TAP Q48 Z Q48 Z Q48 D49 In Q48 Z STAGE 64 TAP Q64 Z Q64 Z Q64 Z Q64 Z X = DON’T CARE Z = HIGH IMPEDANCE 7-1202 CD4517BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 3. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 4. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) - ns FIGURE 5. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 300 250 200 150 100 10V 50 15V 0 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 100 0 0 TRANSITION TIME (fTHL, fTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 50 15V 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1203 CD4517BMS Typical Performance Characteristics 105 8 6 4 2 POWER DISSIPATION (PD) - µW (Continued) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V 104 8 6 4 103 2 8 6 4 2 102 8 6 4 2 CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 10 10 101 103 102 INPUT FREQUENCY (fIN) (kHz) 104 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY Waveforms and Test Circuits CLK 1 2 16 17 trel WE ts tH D tPHL Q48/49, Q32/33, Q16/17 tPLH ts tH 18 33 ts Q64 HIGH Z FIIGURE 9. DYNAMIC TEST WAVEFORMS VDD CL D C QQQQ D C 16 32 48 64 WE D C WE Q16 Q32 Q48Q64 50µF VSS ID CL CL CL fo C D (f = 1/2 fo) REPETITIVE WAVEFORM VDD VSS VDD VSS FIGURE 10. DYNAMIC POWER DISSIPATION TEST CIRCUIT AND WAVEFORMS 7-1204 CD4517BMS Chip Dimensions and Pad Layouts 0 106 100 90 80 70 60 50 40 30 20 10 0 4-10 (0.102-0.254) 140-148 (3.556-3.759) 103-111 (2.617-2.819) 10 20 30 40 50 60 70 80 90 100 110 120 130 140 143 Dimensions in parentheses are in milimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch.) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 1205