CD4536BMS

CD4536BMS December 1992 CMOS Programmable Timer Description 0 24 Features • High Voltage Type (20V Rating) • 24 Flip-Flop Stage - Counts from 2 to 2 • Last 16 Stages Selectable by BCD Select Code • Bypass Input Allows Bypassing First 8 Stages • On-Chip RC Oscillator Provision • Clock Inhibit Input • Schmitt Trigger in clock Line Permits Operation with Very Long Rise and Fall Times • On-Chip Monostable Output Provision • Typical fCL = 3MHz at VDD = 10V • Test Mode Allows Fast Test Sequence • Set and Reset Inputs • Capable of Driving Two Low Power TTL Loads, One Lower Power Schottky Load, or Two HTL Loads Over the Rated Temperature Range • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized, Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD4536BMS is a programmable timer consisting of 24 ripple binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using combinations of these capabilities. A logic 1 on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10kΩ or higher, disables the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and controls its pulse width. A fast test mode is enabled by a logic 1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence. The CD4536BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W Pinout CD4536BMS TOP VIEW 16 VDD Functional Diagram CLOCK INHIBIT OSC INHIBIT 8-BYPASS RESET IN 1 OUT 1 OUT 2 2 3 4 5 15 MONO IN 14 OSC INHIBIT A 13 DECODE OUT 12 D 11 C 10 B 9A BINARY SELECT BINARY SELECT B C D SET RESET MONO IN 6 9 10 11 12 1 2 15 14 7 3 4 OUT 1 5 OUT 2 13 DECODE OUT VSS = 8 VDD = 16 IN 1 RS SET 1 RT 8-BYPASS 6 CLOCK INHIBIT VSS 7 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3345 7-1236 Specifications CD4536BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VOH > VOL < VDD/2 VDD/2 NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-1237 Specifications CD4536BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN .5 .37 MAX 2000 2700 5000 6750 8000 10800 6000 8100 200 270 UNITS ns ns ns ns ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to Q1 8-Bypass High Propagation Delay Clock to Q1 8-Bypass Low Propagation Delay Clock to Q16 Propagation Delay Reset to QN Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25 C +125oC, -55oC o Maximum Clock Input Frequency NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55 C, +25 C +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125 C VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25 C, +125 C, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +25oC, +125oC, 55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC o o o o o o o MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 - MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA 7-1238 Specifications CD4536BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES 1, 2 TEMPERATURE +125 C -55 C Input Voltage Low Input Voltage High Propagation Delay Clock to Q1 8-Bypass High Propagation Delay Clock to Q1 8-Bypass Low Propagation Delay Clock to Q16 Propagation Delay Qn to Qn+1 VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL TPLH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Propagation Delay Set to Qn TPLH VDD = 5V VDD = 10V VDD = 15V Propagation Delay Reset to Qn Transition Time TPHL4 VDD = 10V VDD = 15V TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Minimum Set Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Reset Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Set Recovery Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Reset Recovery Time TREM VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. CIN Any Input 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, -55oC +25 C, +125 C, -55 C +25 C +25oC +25 C +25oC +25 C +25 C +25oC +25oC +25 C +25oC +25 C +25oC +25 C +25 C +25oC +25 C +25 C +25oC +25oC +25 C +25oC +25 C +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC o o o o o o o o o o o o o o o o o o MIN +7 1.5 2.5 - MAX -2.4 -4.2 3 1000 700 1600 1200 3000 2000 300 150 100 600 250 160 2000 1500 100 80 400 150 100 400 200 120 6 2 1.5 5 2 1.6 7 3 2 7.5 UNITS mA mA V V ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns µs µs µs µs µs µs µs µs µs pF Maximum Clock Input Frequency. Unlimited Input Rise or Fall Time Minimum Clock Pulse Width 7-1239 Specifications CD4536BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH ∆VTN VTP ∆VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 7-1240 Specifications CD4536BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 4, 5, 13 4, 5, 13 4, 5, 13 GROUND 1-3, 6-12, 14, 15 8 1, 2, 6-8, 14, 15 8 VDD 16 1-3, 6, 7, 9-12, 14-16 9-12, 16 1-3, 6, 7, 9-12, 14-16 9V ± -0.5V 50kHz 25kHz 4, 5, 13 3 Logic Diagram 6* 8-BYPASS VDD RESET * 2 SET * 1 VSS *INPUTS PROTECTED BY CMOS PROTECTION NETWORK S Q CLDIS CL R FF25 p n CLOCK * INH 7 p n A B C D E F R Q CLEN CL Q FF1 R D Q φ φ CL R Q Q φ φ R Q Q CL Q FF2 FF3 FF8 OSC * INH 14 IN 1 * 3 CT OUT 1 * 4 OUT 2 * 5 RS RT NOTE: f ≈ 1 3RT CT , RS ≈ (5 → 10) x RT G FIGURE 1. 7-1241 CD4536BMS Logic Diagram A B p n (Continued) C D E F R Q CLDIS CL Q FF9 R D Q p n φ φ R Q Q φ φ R Q Q φ φ R Q Q φ φ R Q Q φ φ R Q Q CL Q FF10 FF11 FF16 FF17 FF18 FF24 1 OF 16 DECODER (TRANSMISSION-GATE TREE LOGIC) VSS P N DECODE 13 OUT 9 A * 10 B * 11 C * 12 D * 15 * MONO IN G DETAIL FOR FF3-8, 11-16, 17-24 CLEN (CLDIS FOR FF9 AND FF25) DETAIL FOR FF1, FF2, FF10, FF9, FF25 φ φ VDD R Q Q Q p e n D f Q φ p a n R φ p b c n S R d c Q N P P Q P p f n φ p b n a φ p d n P N φ φ φ p n P Q N N pn R φ φ CL e φ φ φ R φ N φ N P N φ φ φ R CLEN CL Q FF1 Q R D CL Q Q R CLDIS Q CL FF9 Q R CLDIS Q CL S FF25 Q R N FF2, 10 φ FF1: AS SHOWN EXCEPT Q NOT BROUGHT OUT FF9: SAME AS FF1 EXCEPT Q IS BROUGHT OUT AND Q, Q GO TO TGf AND TGe RESP. VSS FF2, FF10: DELETE TGe, TGf, AND INVf; FEED Q TO D; DELETE CLEN, CLDIS FF25: INVa AND INVd BECOME 2-INPUT NAND GATES, WITH ADDED INPUTS S; FEED Q TO TGf VSS TO TGe PREVIOUS Q INPUT; DELETE Q OUTPUT FIGURE 1. (Continued) 7-1242 CD4536BMS TRUTH TABLE IN SET 0 0 X X X 0 1 1 0 0 0 0 RESET 0 0 0 1 0 0 0 X = Don’t Care CLOCK INH 0 0 0 0 1 0 0 OSC INH 0 0 0 0 0 X 0 1 0 0 1 1 OUT1 OUT2 DECODE OUT No Change Advance to Next State 1 0 No Change No Change Advance to Next State 0 = Low Level 1 = High Level Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-1243 CD4536BMS Typical Performance Characteristics PROPAGATION DELAY TIME (tPHL, tPLH) (µs) 2 AMBIENT TEMPERATURE (TA) = +25oC (Continued) PROPAGATION DELAY TIME (tPHL, tPLH) (µs) 4 AMBIENT TEMPERATURE (TA) = +25oC 1.5 SUPPLY VOLTAGE (VDD) = 5V 1 3 SUPPLY VOLTAGE (VDD) = 5V 2 10V 0.5 15V 0 10V 1 15V 0 0 20 40 60 80 100 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q1, 8-BYPASS HIGH) PROPAGATION DELAY TIME (tPHL, tPLH) (µs) 2 AMBIENT TEMPERATURE (TA) = +25oC FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q1, 8-BYPASS LOW) PROPAGATION DELAY TIME (tPHL, tPLH) (µs) 200 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 150 1.5 SUPPLY VOLTAGE (VDD) = 5V 1 100 10V 15V 0.5 10V 50 15V 0 0 20 40 60 80 100 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q16, 8-BYPASS HIGH) 60 50 40 30 20 10 0 -10 -20 5 RS = 0, f = 7900Hz AMBIENT TEMPERATURE (TA) = EXTERNAL RESISTANCE (RE) = 56kΩ EXTERNAL CAPACITANCE (CX) = 1000pF +25oC FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (QN TO QN + 1) 103 8 OSCILLATOR FREQUENCY (F) (KHz) 6 4 2 6 4 2 6 4 2 6 4 2 6 4 2 2 FREQUENCY DEVIATION (∆f) (%) 102 8 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 10V 1 f= 3Rtc CT f vs Rtc CT = 1000pF RS = 2Rtc f vs CT Rtc = 56kΩ RS = 120kΩ 10 8 08 10-1 8 10-2 102 RS = 120kΩ, f = 5900Hz 103 104 105 EXTERNAL CAPACITANCE (CT) (pF) 103 10 102 EXTERNAL RESISTANCE (Rtc) (kΩ) 4 68 2 4 68 2 4 68 2 4 68 106 104 6 7 9 11 13 8 10 12 SUPPLY VOLTAGE (VDD) (V) 14 15 1 FIGURE 10. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 11. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF TIME CONSTANT RESISTANCE AND CAPACITANCE 7-1244 CD4536BMS Typical Performance Characteristics 10.0 7.5 5.0 2.5 0 -2.5 -5.0 -7.5 15V 10V 5V Rtc = 56kΩ RS = 0 CX = 1000pF SUPPLY VOLTAGE (VDD) = 5V 10V 15V (Continued) 10.0 7.5 5.0 SUPPLY VOLTAGE (VDD) = 5V 2.5 0 -2.5 -5.0 -7.5 5V 15V 10V 15V 10V Rtc = 56kΩ RE = 120kΩ CX = 1000pF FREQUENCY DEVIATION (∆f) (%) -10.0 -50 0 50 100 o 150 FREQUENCY DEVIATION (∆f) (%) -10.0 -50 0 50 100 150 AMBIENT TEMPERATURE (TA) C AMBIENT TEMPERATURE (TA) oC FIGURE 12. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF AMBIENT TEMPERATURE (RS = 0) 103 8 6 4 2 FIGURE 13. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF AMBIENT TEMPERATURE (RS = 120kΩ) 103 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 10V 102 8 PULSE WIDTH (µs) 2 PULSE WIDTH (µs) 6 4 102 8 6 4 2 RX = 1mΩ 10 8 6 4 2 10 8 RX = 1mΩ 6 4 2 18 6 4 2 100K 50K 10K 2 4 68 18 6 4 2 100kΩ 50kΩ 10kΩ 2 4 68 0.1 1 10 102 103 104 EXTERNAL CAPACITANCE (CX) (pF) 2 4 68 2 4 68 2 4 68 2 4 68 0.1 1 105 10 102 103 104 EXTERNAL CAPACITANCE (CX) (pF) 2 4 68 2 4 68 2 4 68 2 4 68 105 FIGURE 14. TYPICAL PULSE WIDTH AS A FUNCTION OF EXTERNAL CAPACITANCE (VDD = 5V) 103 8 6 4 2 FIGURE 15. TYPICAL PULSE WIDTH AS A FUNCTION OF EXTERNAL CAPACITANCE (VDD = 10V) 102 8 PULSE WIDTH (µs) 6 4 2 TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V AMBIENT TEMPERATURE (TA) = +25oC 200 SUPPLY VOLTAGE (VDD) = 5V 10 8 RX = 1mΩ 6 4 2 150 100 10V 50 15V 18 6 4 2 100kΩ 50kΩ 10kΩ 2 4 68 0.1 1 10 102 103 104 EXTERNAL CAPACITANCE (CX) (pF) 2 4 68 2 4 68 2 4 68 2 4 68 105 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 16. TYPICAL PULSE WIDTH AS A FUNCTION OF EXTERNAL CAPACITANCE (VDD = 15V) FIGURE 17. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1245 CD4536BMS Typical Performance Characteristics 105 8 6 4 2 (Continued) AMBIENT TEMPERATURE (TA) = +25oC POWER DISSIPATION (PD) (µW) 104 8 6 4 2 SUPPLY VOLTAGE (VDD) = 15V 10V 5V 103 8 6 4 2 102 8 6 4 2 CL = 50pF CL = 15pF 2 4 68 10 0.1 1 10 102 PULSE INPUT FREQUENCY (kHz) 2 4 68 2 4 68 2 4 68 103 FIGURE 18. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT PULSE FREQUENCY Applications 9 10 11 12 1 2 6 15 >10K 14 A B C D SET RESET 8-BYPASS C INH MONO IN OSC INH DECODE OUT IN 1 8 VSS OUT 2 VDD 16 OUT 1 4 5 3 12 11 13 VDD CX RX 16 Q1 CD4098BMS R CL CODE OUT (CL ÷ 8) 8 Q1 OUTPUT CD4098BMS 1 2 +TR -TR R +TR -TR R 15 14 FIGURE 19. APPLICATION SHOWING USE OF CD4098BMS AND CD4536BMS TO GET DECODE PULSE 8 CLOCK PULSES AFTER RESET PULSE VDD A B C D SET RESET 8-BYPASS C INH ≥10kΩ CLOCK MONO IN OSC INH DECODE OUT IN 1 VSS CL t CLOCK R OUT 2 OUT 1 A B C D SET RESET 8-BYPASS C INH MONO IN VDD OUT 1 OUT 2 t OSC INH DECODE OUT IN 1 VSS FIGURE 20. TIME INTERVAL CONFIGURATION USING EXTERNAL CLOCK; SET AND CLOCK INHIBIT FUNCTIONS FIGURE 21. TIME INTERVAL CONFIGURATION USING EXTERNAL CLOCK; RESET AND OUTPUT MONOSTABLE TO ACHIEVE A PULSE OUTPUT 7-1246 CD4536BMS Applications (Continued) VDD A B C D SET START RESET 8-BYPASS C INH MONO IN OSC INH DECODE OUT IN 1 VSS OUT 2 OUT 1 C RS R Rtc CLOCK DCBA 0000 (÷2) 0001 (÷4) 0010 (÷8) 1 Rtc C f≅ 2.3 RS ≥ 2Rtc f IN Hz, R IN Ω, C IN F 3µs MIN t FIGURE 22. TIME INTERVAL CONFIGURATION USING ONCHIP RC OSCILLATOR AND RESET INPUT TO INITIATE TIME INTERVAL FIGURE 23. TIMING DIAGRAM NOTE: SHADED PULSE REPRESENTS DECODE OUTPUT IN MONOSTABLE MODE. IF AN OUTPUT PULSE IS REQUIRED 1 FULL COUNTDOWN AFTER REMOVAL OF RESET PULSE, SEE FIGURE 19 FOR USE OF CD4098BMS DECODE OUT SELECTION TABLE NUMBER OF STAGES IN DIVIDER CHAIN D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8-BYPASS = 0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 = High Level 8-BYPASS = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 = Low Level Functional Block Diagram SET RESET 1 2 OSC INHIBIT LOGIC CLOCK INHIBIT LOGIC STAGES 1-8 8-BYPASS LOGIC STAGES 9-24 Q9 - - - Q24 8-BYPASS 6 OSC 14 INHIBIT 3 4 5 IN OUT 1 OUT 2 A BINARY SELECT VSS = 8 VDD = 16 B C D MONO IN 9 10 11 12 15 DECODER 13 DECODE OUT CLOCK 7 INHIBIT FIGURE 24. 7-1247 CD4536BMS FUNCTIONAL TEST SEQUENCE INPUTS IN 1 1 1 0 1 0 0 0 SET 0 1 1 RESET 1 1 1 8-BYPASS 1 1 1 OUTPUTS DECODE OUT Q1 THRU 24 0 0 0 ALL 24 STEPS ARE IN RESET MODE Counter is in three 8-stage section in parallel mode First “1” to “0” transition of clock 255 “1” to “0” transitions are clocked in the counter 1 1 1 COMMENTS 1 0 1 0 1 0 1 1 The 255 “1” to “0” transition Counter converted back to 24 stages in series mode. Set and Reset must be connected together and simultaneously go from “1” to “0” In1 Switches to a “1” Counter Ripples from an all “1” state to an all “0” state 1 0 0 0 0 0 0 0 1 0 Functional Test Sequence Test Function has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections and 255 counts are loaded in each of the 8-stage sections in parallel. All flip-flops are now at a “1”. The counter is now returned to the normal 24 steps in series configuration. One more pulse is entered into In1 which will cause the counter to ripple from an all “1” state to an all “0” state. Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). IN R TE SI L METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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