CDP1802ACEX

CDP1802A, CDP1802AC, CDP1802BC March 1997 CMOS 8-Bit Microprocessors Description The CDP1802 family of CMOS microprocessors are 8-bit register oriented central processing units (CPUs) designed for use as general purpose computing or control elements in a wide range of stored program systems or products. The CDP1802 types include all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design. The 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt driven, or direct memory access modes. The CDP1802A and CDP1802AC have a maximum input clock frequency of 3.2MHz at VDD = 5V. The CDP1802A and CDP1802AC are functionally identical. They differ in that the CDP1802A has a recommended operating voltage range of 4V to 10.5V, and the CDP1802AC a recommended operating voltage range of 4V to 6.5V. The CDP1802BC is a higher speed version of the CDP1802AC, having a maximum input clock frequency of 5.0MHz at VDD = 5V, and a recommended operating voltage range of 4V to 6.5V. Features • Maximum Input Clock Maximum Frequency Options At VDD = 5V - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 3.2MHz - CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0MHz • Maximum Input Clock Maximum Frequency Options At VDD = 10V - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 6.4MHz • Minimum Instruction Fetch-Execute Times At VDD = 5V - CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs - CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs • Any Combination of Standard RAM and ROM Up to 65,536 Bytes • 8-Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus • 16 x 16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers • On-Chip DMA, Interrupt, and Flag Inputs • Programmable Single-Bit Output Port • 91 Easy-to-Use Instructions [ /Title (CDP1 802A, CDP18 02AC, CDP18 02BC) /Subject CMO 8it icrorocesors) /Autho () /Keyords Interil orpoation, -bit icrorocesors, 8 it icrorocesors, eriphrals) /Cretor () /DOCI FO dfark Ordering Information PART NUMBER 5V - 3.2MHz CDP1802ACE CDP1802ACEX CDP1802ACQ CDP1802ACD CDP1802ACDX 5V - 5MHz CDP1802BCE CDP1802BCEX CDP1802BCQ CDP1802BCDX -40oC to +85oC -40oC to +85oC TEMPERATURE RANGE -40oC to +85oC PACKAGE PDIP Burn-In PLCC SBDIP Burn-In PKG. NO. E40.6 E40.6 N44.65 D40.6 D40.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 1305.2 3-3 CDP1802A, CDP1802AC, CDP1802BC Pinouts 40 LEAD PDIP (PACKAGE SUFFIX E) 40 LEAD SBDIP (PACKAGE SUFFIX D) TOP VIEW 44 LEAD PLCC (PACKAGE TYPE Q) TOP VIEW CLOCK WAIT CLEAR Q SC1 SC0 MRD BUS 7 BUS 6 1 2 3 4 5 6 7 8 9 40 VDD 38 DMA IN WAIT SC1 37 DMA OUT 36 INTERRUPT 35 MWR 34 TPA 33 TPB 32 MA7 31 MA6 30 MA5 29 MA4 28 MA3 27 MA2 26 MA1 25 MA0 24 EF1 23 EF2 22 EF3 21 EF4 SC0 MRD BUS 7 BUS 6 BUS 5 NC BUS 4 BUS 3 BUS 2 BUS 1 BUS 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS NC EF4 EF3 EF2 EF1 MA0 VCC N2 N1 N0 39 38 37 36 35 34 33 32 31 30 29 MWR TPA TPB MA7 MA6 NC MA5 MA4 MA3 MA2 MA1 CLEAR INTERRUPT MA0-4 39 XTAL CLOCK DMA-OUT MRD CDP1824 32 BYTE RAM MWR TPA DATA CEO CS DMA-IN 6 5 4 3 2 1 44 43 42 41 40 BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS 1 14 BUS 0 15 VCC 16 N2 17 N1 18 N0 19 VSS 20 ADDRESS BUS CDP1852 INPUT PORT CS2 CS1 N0 MA0-7 MA0-7 MRD CDP1802 8-BIT CPU MWR DATA CS1 N1 TPA MRD CDP1833 1K-ROM CDP1852 CS2 OUTPUT PORT CLOCK TPB DATA FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM 3-4 VDD NC XTAL Q CDP1802A, CDP1802AC, CDP1802BC Block Diagram I/O REQUESTS MEMORY ADDRESS LINES I/O FLAGS DMA OUT DMA IN INT CONTROL CLEAR WAIT MA7 MA5 MA3 MA1 MUX MA6 MA4 MA2 MA0 EF1 EF3 EF2 EF4 CLOCK LOGIC CLOCK XTAL SCO SCI Q LOGIC TPA TPB MWR MRD STATE CODES CONTROL AND TIMING LOGIC SYSTEM TIMING TO INSTRUCTION DECODE A REGISTER R(0).1 R(0).0 ARRAY R(1).1 R(1).0 R R(2).1 R(2).0 R(9).1 R(9).0 R(A).1 R(A).0 R(E).1 R(E).0 R(F).1 R(F).0 8-BIT BIDIRECTIONAL DATA BUS LATCH AND DECODE B ALU DF INCR/ DECR N0 X T P I N N1 N2 BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 I/O COMMANDS D FIGURE 2. 3-5 CDP1802A, CDP1802AC, CDP1802BC Absolute Maximum Ratings DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1802A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1802AC, CDP1802BC . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Information Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 50 N/A PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 46 N/A SBDIP . . . . . . . . . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E and Q . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ± 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Lead Tips Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions TA = -40oC to +85oC. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CDP1802A CDP1802AC CDP1802BC TEST CONDITIONS (NOTE 2) VCC (V) 4 to 6.5 4 to 10.5 Minimum Instruction Time (Note 3) 5 5 10 Maximum DMA Transfer Rate 5 5 10 Maximum Clock Input Frequency, fCL, Load Capacitance (CL) = 50pF 5 5 10 NOTES: PARAMETER DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time VDD (V) 4 to 6.5 4 to 10.5 5 10 10 5 10 10 5 10 10 MIN 4 VSS 5 4 2.5 DC DC DC MAX 10.5 VDD 1 400 500 800 3.2 4 6.4 MIN 4 VSS 5 DC - MAX 6.5 VDD 1 400 3.2 - MIN 4 VSS 3.2 DC - MAX 6.5 VDD 1 667 5 - UNITS V V µs µs µs µs µs KBytes/s MHz MHz MHz 1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent. 2. VCC must never exceed VDD. 3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. 4. θJA is measured with component mounted on an evaluation board in free air. 3-6 CDP1802A, CDP1802AC, CDP1802BC Static Electrical Specifications at TA = -40oC to +85oC, Except as Noted TEST CONDITIONS VCC, VDD (V) 5 10 CDP1802A CDP1802AC, CDP1802BC PARAMETER Quiescent Device Current SYMBOL IDD VOUT (V) - VIN (V) - MIN - (NOTE 1) TYP 0.1 1 MAX 50 200 MIN - (NOTE 1) TYP 1 - MAX 200 - UNITS µA µA Output Low Drive (Sink) Current (Except XTAL) XTAL Output High Drive (Source) Current (Except XTAL) XTAL Output Voltage Low Level Output Voltage High Level Input Low Voltage VOH VIL VOL IOH 4.6 9.5 4.6 0.5, 4.5 0.5, 4.5 1, 9 Input High Voltage VIH 0.5, 4.5 0.5, 4.5 1, 9 CLEAR Input Voltage Schmitt Hysteresis VH Input Leakage Current IIN Any Input 0, 5 0, 10 0, 5 0, 10 0 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 Three-State Output Leakage Current Operating Current CDP1802A, AC at f = 3.2MHz CDP1802BC at f = 5.0MHz Minimum Data Retention Voltage Data Retention Current VDR IDR IDDI (Note 2) 5 2 4 2 4 mA IOUT 0, 5 0, 10 5 10 5 5 10 5 10 5 5, 10 10 5 5, 10 10 5 5, 10 10 5 10 5 10 -0.27 -0.55 -125 4.9 9.9 3.5 4 7 0.4 0.3 1.5 -0.55 -1.1 -250 0 0 5 10 0.5 0.4 2 ±10-4 ±10-4 ±10-4 ±10-4 0.1 0.1 1.5 1 3 ±1 ±1 ±1 ±1 -0.27 -125 4.9 3.5 0.4 -0.55 -250 0 5 0.5 ±10-4 ±10-4 0.1 1.5 ±1 ±1 mA mA µA V V V V V V V V V V V V V µA µA µA µA IOL 0.4 0.5 0.4 0, 5 0, 10 5 5 10 5 1.1 2.2 170 2.2 4.4 350 1.1 170 2.2 350 mA mA µA - - 5 - - - - 3 6 mA VDD = VDR VDD = 2.4V - 2 2.4 - 2 2.4 V µA - 0.05 - - 0.5 - 3-7 CDP1802A, CDP1802AC, CDP1802BC Static Electrical Specifications at TA = -40oC to +85oC, Except as Noted (Continued) TEST CONDITIONS VCC, VDD (V) CDP1802A CDP1802AC, CDP1802BC PARAMETER Input Capacitance Output Capacitance NOTES: SYMBOL CIN COUT VOUT (V) VIN (V) MIN - (NOTE 1) TYP 5 10 MAX 7.5 15 MIN - (NOTE 1) TYP 5 10 MAX 7.5 15 UNITS pF pF 1. Typical values are for TA = +25oC and nominal VDD. 2. Idle “00” at M(0000), CL = 50pF. Dynamic Electrical Specifications TA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted TEST CONDITIONS CDP1802A, CDP1802AC (NOTE 1) TYP CDP1802BC (NOTE 1) TYP PARAMETER PROPAGATION DELAY TIMES Clock to TPA, TPB SYMBOL VCC (V) VDD (V) MAX MAX UNITS tPLH, tPHL 5 5 10 5 10 10 5 10 10 5 10 10 5 10 10 5 10 10 5 10 10 5 10 10 200 150 100 600 400 300 250 150 100 200 150 100 200 150 100 200 150 100 300 250 100 300 250 150 850 600 400 350 250 150 300 250 150 350 290 175 300 250 150 450 350 200 200 475 175 175 175 175 250 - 300 525 250 275 275 225 375 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock-to-Memory High-Address Byte tPLH, tPHL 5 5 10 Clock-to-Memory Low-Address Byte Valid tPLH, tPHL 5 5 10 Clock to MRD tPHL 5 5 10 Clock to MRD tPLH 5 5 10 Clock to MWR tPLH, tPHL 5 5 10 Clock to (CPU DATA to BUS) Valid tPLH, tPHL 5 5 10 3-8 CDP1802A, CDP1802AC, CDP1802BC Dynamic Electrical Specifications TA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted (Continued) TEST CONDITIONS CDP1802A, CDP1802AC (NOTE 1) TYP 300 250 150 250 150 100 300 200 150 CDP1802BC (NOTE 1) TYP 250 200 275 - PARAMETER Clock to State Code SYMBOL tPLH, tPHL VCC (V) 5 5 10 VDD (V) 5 10 10 5 10 10 5 10 10 MAX 450 350 250 400 250 150 550 350 250 MAX 400 300 350 - UNITS ns ns ns ns ns ns ns ns ns Clock to Q tPLH, tPHL 5 5 10 Clock to N (0 - 2) tPLH, tPHL 5 5 10 MINIMUM SET UP AND HOLD TIMES Data Bus Input Set Up tSU 5 5 10 Data Bus Input Hold tH (Note 2) 5 5 10 DMA Set Up tSU 5 5 10 DMA Hold tH (Note 2) 5 5 10 Interrupt Set Up tSU 5 5 10 Interrupt Hold tH (Note 2) 5 5 10 WAIT Set Up tSU 5 5 10 5 10 10 5 10 10 5 10 10 5 10 10 5 10 10 5 10 10 5 10 10 -20 0 -10 150 100 75 0 0 0 150 100 75 -75 -50 -25 100 75 50 10 -10 0 25 50 40 200 125 100 30 20 10 250 200 125 0 0 0 150 100 75 50 15 25 -20 125 0 100 -75 75 20 0 150 30 150 0 125 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-9 CDP1802A, CDP1802AC, CDP1802BC Dynamic Electrical Specifications TA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted (Continued) TEST CONDITIONS CDP1802A, CDP1802AC (NOTE 1) TYP -30 -20 -10 150 100 75 CDP1802BC (NOTE 1) TYP -30 100 - PARAMETER EF1-4 Set Up SYMBOL tSU VCC (V) 5 5 10 VDD (V) 5 10 10 5 10 10 MAX 20 30 40 200 150 100 MAX 0 150 - UNITS ns ns ns ns ns ns EF1-4 Hold tH (Note 2) 5 5 10 Minimum Pulse Width Times CLEAR Pulse Width tWL (Note 2) 5 5 10 CLOCK Pulse Width tWL 5 5 10 NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. Maximum limits of minimum characteristics are the values above which all devices function. 5 10 10 5 10 10 150 100 75 125 100 60 300 200 150 150 125 75 100 90 150 100 ns ns ns ns ns ns Timing Specifications as a function of T(T = 1/fCLOCK) at TA = -40 to +85oC, Except as Noted TEST CONDITIONS CDP1802A, CDP1802AC (NOTE 1) TYP 2T-400 2T250 2T-200 T/2-15 T/2-25 T/2-+0 T+0 T+0 T+0 T-150 T-100 T-50 CDP1802BC (NOTE 1) TYP 2T-275 T/2-15 T+0 T-125 - PARAMETERS High-Order Memory-Address Byte Set Up to TPA Time SYMBOL tSU VCC (V) 5 5 10 VDD (V) 5 10 10 5 10 10 5 10 10 5 10 10 MIN 2T-550 2T-350 2T-250 t/2-25 T/2-35 T/2-10 T-30 T-20 T-10 T-200 T-150 T-100 MIN 2T-325 T/2-25 T-30 T-175 - UNITS ns ns ns ns ns ns ns ns ns ns ns ns High-Order Memory-Address Byte Hold After TPA Time tH 5 5 10 Low-Order Memory-Address Byte Hold After WR Time tH 5 5 10 CPU Data to Bus Hold After WR Time tH 5 5 10 3-10 CDP1802A, CDP1802AC, CDP1802BC Timing Specifications as a function of T(T = 1/fCLOCK) at TA = -40 to +85oC, Except as Noted TEST CONDITIONS CDP1802A, CDP1802AC (NOTE 1) TYP 5T-250 5T-150 5T-100 T/2-18 T/2-15 T/2-10 CDP1802BC (NOTE 1) TYP 5T-175 T/2-15 - PARAMETERS Required Memory Access Time Address to Data SYMBOL tACC VCC (V) 5 5 10 VDD (V) 5 10 10 5 10 10 MIN 5T-375 5T-250 5T-190 T/2-25 T/2-20 T/2-15 MIN 5T-225 T/2-20 - UNITS ns ns ns ns ns ns MRD to TPA tSU 5 5 10 NOTE: 1. Typical values are for TA = +25oC and nominal VDD. Timing Waveforms FETCH (READ) CLOCK EXECUTE (WRITE) 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 ADDRESS HI BYTE LOW BYTE HI BYTE LOW BYTE TPA TPB MRD MWR DATA VALID INPUT DATA VALID OUTPUT DATA FIGURE 3. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE 3-11 CDP1802A, CDP1802AC, CDP1802BC Timing Waveforms tW CLOCK 00 0 01 10 (Continued) 1 11 20 2 21 30 3 31 4 40 41 50 5 51 6 60 61 7 70 71 0 00 01 TPA tPLH tPHL TPB tSU MEMORY ADDRESS MRD (MEMORY READ CYCLE) MWR (MEMORY WRITE CYCLE) DATA FROM CPU TO BUS tPLH, tPHL HIGH ORDER ADDRESS BYTE tPHL tSU tH tPLH, tPHL LOW ORDER ADDRESS BYTE tPLH tPHL tPLH, tPHL tPLH tH tPLH tPLH tPHL tPHL tPLH tH tPLH, tPHL STATE CODES tPLH tPHL tPLH, tPHL tPLH, tPHL Q N0, N1, N2 (I/O EXECUTION CYCLE) tPLH tPLH DATA LATCHED IN CPU tH DATA FROM BUS TO CPU tSU DMA SAMPLED (S1, S2, S3) tSU DMA REQUEST INTERRUPT SAMPLED (S1, S2) tSU INTERRUPT REQUEST tSU FLAG LINES SAMPLED (IN S1) tH tH tH EF 1-4 tSU WAIT ANY NEGATIVE TRANSITION tW CLEAR NOTES: 1. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle. 2. All measurements are referenced to 50% point of the waveforms. 3. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period. FIGURE 4. TIMING WAVEFORM 3-12 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms 0 CLOCK 1 2 3 4 5 6 7 0 (Propagation Delays Not Shown) 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 TPA TPB MACHINE CYCLE CYCLE n CYCLE (n + 1) CYCLE (n + 2) MA HIGH ADD LOW ADDRESS HIGH ADD LOW ADDRESS HIGH ADD LOW ADDRESS FIGURE 5. GENERAL TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) NON MEMORY CYCLE FETCH (S0) MEMORY READ CYCLE EXECUTE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT HIGH IMPEDANCE STATE VALID OUTPUT “DON’T CARE” OR INTERNAL DELAYS FIGURE 6. NON-MEMORY CYCLE TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) MEMORY WRITE CYCLE FETCH (S0) MEMORY READ CYCLE EXECUTE MRD MWR MEMORY OUTPUT ALLOWABLE MEMORY ACCESS CPU OUTPUT TO MEMORY OFF VALID OUTPUT VALID DATA OFF HIGH IMPEDANCE STATE VALID OUTPUT VALID “DON’T CARE” OR INTERNAL DELAYS FIGURE 7. MEMORY WRITE CYCLE TIMING WAVEFORMS 3-13 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued) INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) MEMORY READ CYCLE FETCH (S0) MEMORY READ CYCLE EXECUTE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID OUTPUT HIGH IMPEDANCE STATE VALID OUTPUT “DON’T CARE” OR INTERNAL DELAYS FIGURE 8. MEMORY READ CYCLE TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) MEMORY READ CYCLE EXECUTE (S1) MEMORY READ CYCLE FETCH (S0) MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID OUTPUT HIGH IMPEDANCE STATE VALID OUTPUT “DON’T CARE” OR INTERNAL DELAYS FIGURE 9. LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS 3-14 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms 0 CLOCK TPA 1 2 3 4 (Propagation Delays Not Shown) 5 6 7 0 1 (Continued) 2 3 4 5 6 7 0 TPB MACHINE CYCLE INSTRUCTION CYCLE n CYCLE (n + 1) FETCH (S0) EXECUTE (S1) MRD N0 - N2 MWR MEMORY OUTPUT ALLOWABLE MEMORY ACCESS DATA BUS (NOTE 1) VALID OUTPUT VALID DATA FROM INPUT DEVICE MEMORY READ CYCLE NOTE 1 USER GENERATED SIGNAL MEMORY WRITE CYCLE “DON’T CARE” OR INTERNAL DELAYS HIGH IMPEDANCE STATE N=9-F FIGURE 10. INPUT CYCLE TIMING WAVEFORMS 0 CLOCK TPA 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 TPB MACHINE CYCLE INSTRUCTION MRD CYCLE n CYCLE (n + 1) FETCH (S0) EXECUTE (S1) N0 - N2 N=1-9 ALLOWABLE MEMORY ACCESS DATA BUS ALLOWABLE MEMORY ACCESS DATA STROBE (MRD • TPB • N) (NOTE 1) MEMORY READ CYCLE NOTE 1 USER GENERATED SIGNAL MEMORY READ CYCLE HIGH IMPEDANCE STATE VALID OUTPUT VALID DATA FROM MEMORY “DON’T CARE” OR INTERNAL DELAYS FIGURE 11. OUTPUT CYCLE TIMING WAVEFORMS 3-15 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms 0 CLOCK TPA TPB MACHINE CYCLE INSTRUCTION DMA-IN MRD MWR MEMORY OUTPUT VALID OUTPUT DATA BUS (NOTE 1) VALID DATA FROM INPUT DEVICE MEMORY READ CYCLE MEMORY READ, WRITE OR NON-MEMORY CYCLE “DON’T CARE” OR INTERNAL DELAYS MEMORY WRITE CYCLE CYCLE n FETCH (S0) CYCLE (n+1) EXECUTE (S1) CYCLE (n+2) DMA (S2) 1 2 3 4 5 6 7 (Propagation Delays Not Shown) 0 1 2 3 4 5 6 (Continued) 7 0 1 2 3 4 5 6 7 NOTE 1 USER GENERATED SIGNAL HIGH IMPEDANCE STATE FIGURE 12. DMA IN CYCLE TIMING WAVEFORMS 0 CLOCK TPA TPB MACHINE CYCLE INSTRUCTION DMA OUT (NOTE 1) MRD MWR MEMORY OUTPUT DATA STROBE (S2 • TPB) (NOTE 1) 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 CYCLE n FETCH (S0) CYCLE (n + 1) EXECUTE (S1) CYCLE (n + 2) DMA (S2) VALID OUTPUT VALID DATA FROM MEMORY MEMORY READ CYCLE NOTE 1 USER GENERATED SIGNAL MEMORY READ, WRITE OR NON-MEMORY CYCLE “DON’T CARE” OR INTERNAL DELAYS MEMORY READ CYCLE HIGH IMPEDANCE STATE FIGURE 13. DMA OUT CYCLE TIMING WAVEFORMS 3-16 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms 0 CLOCK TPA TPB MACHINE CYCLE CYCLE n CYCLE (n + 1) CYCLE (n + 2) 1 2 3 4 5 6 7 (Propagation Delays Not Shown) (Continued) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 INSTRUCTION FETCH (S0) EXECUTE (S1) INTERRUPT (S3) MRD MWR INTERRUPT (NOTE 1) (INTERNAL) IE MEMORY OUTPUT VALID OUTPUT MEMORY READ, WRITE OR NON-MEMORY CYCLE MEMORY READ CYCLE NOTE 1 USER GENERATED SIGNAL NON-MEMORY CYCLE “DON’T CARE” OR INTERNAL DELAYS HIGH IMPEDANCE STATE FIGURE 14. INTERRUPT CYCLE TIMING WAVEFORMS Performance Curves 8 CL, LOAD CAPACITANCE = 50pF 7 fCL, SYSTEM MAXIMUM CLOCK FREQUENCY (MHz) 6 5 VCC = 5V, VDD = 10V 4 3 2 1 0 25 35 45 55 65 75 85 95 105 TA, AMBIENT TEMPERATURE (oC) 115 125 VCC = VDD = 5V fCL, SYSTEM MAXIMUM CLOCK FREQUENCY (MHz) VCC = VDD = 10V 8 CL, LOAD CAPACITANCE = 50pF 7 6 5 VCC = VDD = 5V 4 3 2 1 0 25 35 45 55 65 75 85 95 105 TA, AMBIENT TEMPERATURE (oC) 115 125 FIGURE 15. CDP1802A, AC TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE FIGURE 16. CDP1802BC TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE 3-17 CDP1802A, CDP1802AC, CDP1802BC Performance Curves 400 tTHL, tTLH, TRANSITION TIME (ns) 350 300 2 250 200 150 100 tTHL 50 VCC = VDD = 10V 0 0 25 50 75 100 125 150 175 200 CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE = -40oC TO +85oC tTLH VCC = VDD = 5V VCC = VDD = 10V -10V 3 4 5 6 7 TA = 25oC (Continued) -10 -9 VDS, DRAIN-TO-SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 VGS, GATE-TO-VOLTAGE = -5V -1 0 1 IOH, OUTPUT HIGH (SOURCE) CURRENT (mA) IOH, OUTPUT HIGH (SOURCE) CURRENT (mA) VCC = VDD = 5V FIGURE 17. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE FOR ALL TYPES TA = -40oC TO +85oC 35 30 25 VGS, GATE-TO-SOURCE = 10V 20 15 10 5 5V FIGURE 18. CDP1802A, AC MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS VDS, DRAIN-TO-SOURCE VOLTAGE (V) -4 -3 -2 -1 IOL, OUTPUT LOW (SINK) CURRENT (mA) -5 0 1 VGS, GATE-TO-VOLTAGE = -5V 2 3 0 1 2 3 4 5 6 7 8 9 10 4 VDS, DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 19. CDP1802A, AC MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS IOL, OUTPUT LOW (SINK) CURRENT (mA) TA = -40oC TO +85oC FIGURE 20. CDP1802BC MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS ∆tPLH, ∆tPHL, ∆ PROPAGATION DELAY TIME (ns) 150 TA = 25oC VCC = VDD = 5V 125 100 75 50 25 VCC = VDD = 10V 0 25 50 100 150 ∆CL, ∆ LOAD CAPACITANCE (pF) 200 ∆tPLH ∆tPHL VCC = VDD = 10V VCC = VDD = 5V 20 10 VGS, GATE-TO-SOURCE = 5V 5 0 1 2 3 4 5 VDS, DRAIN-TO-SOURCE VOLTAGE (V) NOTE: ANY OUTPUT EXCEPT XTAL FIGURE 21. CDP1802BC MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 22. TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE FOR ALL TYPES 3-18 CDP1802A, CDP1802AC, CDP1802BC Performance Curves (Continued) 1000 PD, TYPICAL POWER DISSIPATION FOR CDP1802D (mW) TA = 25oC VCC = VDD = 10V 100 10 BRANCH IDLE 1 VCC = VDD = 5V 0.1 0.01 0.1 1 fCL, CLOCK INPUT FREQUENCY (MHz) 10 NOTE: IDLE = “00” AT M(0000), BRANCH = “3707” AT M(8107), CL = 50pF FIGURE 23. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE INSTRUCTION FOR ALL TYPES Signal Descriptions Bus 0 to Bus 7 (Data Bus) 8-bit bidirectional DATA BUS lines. These lines are used for transferring data between the memory, the microprocessor, and I/O devices. N0 to N2 (I/O Control Lines) Activated by an I/O instruction to signal the I/O control logic of a data transfer between memory and I/O interface. These lines can be used to issue command codes or device selection codes to the I/O devices (independently or combined with the memory byte on the data bus when an I/O instruction is being executed). The N bits are low at all times except when an I/O instruction is being executed. During this time their state is the same as the corresponding bits in the N register. The direction of data flow is defined in the I/O instruction by bit N3 (internally) and is indicated by the level of the MRD signal. MRD = VCC: Data from I/O to CPU and Memory MRD = VSS: Data from Memory to I/O EF1 to EF4 (4 Flags) These inputs enable the I/O controllers to transfer status information to the processor. The levels can be tested by the conditional branch instructions. They can be used in conjunction with the INTERRUPT request line to establish interrupt priorities. These flags can also be used by I/O devices to “call the attention” of the processor, in which case the program must routinely test the status of these flag(s). The flag(s) are sampled at the beginning of every S1 cycle. INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests) These inputs are sampled by the CPU during the interval between the leading edge of TPB and the leading edge of TPA. STATE TYPE S0 (Fetch) S1 (Execute) S2 (DMA) S3 (Interrupt) Interrupt Action - X and P are stored in T after executing current instruction; designator X is set to 2; designator P is set to 1; interrupt enable is reset to 0 (inhibit); and instruction execution is resumed. The interrupt action requires one machine cycle (S3). DMA Action - Finish executing current instruction; R(0) points to memory area for data transfer; data is loaded into or read out of memory; and increment R(0). NOTE: In the event of concurrent DMA and Interrupt requests, DMA-lN has priority followed by DMA-OUT and then Interrupt. SC0, SC1, (2 State Code Lines) These outputs indicate that the CPU is: 1) fetching an instruction, or 2) executing an instruction, or 3) processing a DMA request, or 4) acknowledging an interrupt request. The levels of state code are tabulated below. All states are valid at TPA. H = VCC, L = VSS. STATE CODE LINES SC1 L L H H SC0 L H L H TPA, TPB (2 Timing Pulses) Positive pulses that occur once in each machine cycle (TPB follows TPA). They are used by I/O controllers to interpret codes and to time interaction with the data bus. The trailing edge of TPA is used by the memory system to latch the higher-order byte of the 16-bit memory address. TPA is suppressed in IDLE when the CPU is in the load mode. 3-19 CDP1802A, CDP1802AC, CDP1802BC MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit CPU memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches by timing pulse TPA. The low order byte of the 16-bit address appears on the address lines after the termination of TPA. Latching of all 8 higher-order address bits would permit a memory system of 64K bytes. MWR (Write Pulse) A negative pulse appearing in a memory-write cycle, after the address lines have stabilized. MRD (Read Level) A low level on MRD indicates a memory read cycle. It can be used to control three-state outputs from the addressed memory which may have a common data input and output bus. If a memory does not have a three-state high-impedance output, MRD is useful for driving memory/bus separator gates. It is also used to indicate the direction of data transfer during an I/O instruction. For additional information see Table 1. Q Single bit output from the CPU which can be set or reset under program control. During SEQ or REQ instruction execution, Q is set or reset between the trailing edge of TPA and the leading edge of TPB. CLOCK Input for externally generated single-phase clock. The clock is counted down internally to 8 clock pulses per machine cycle. XTAL Connection to be used with clock input terminal, for an external crystal, if the on-chip oscillator is utilized. The crystal is connected between terminals 1 and 39 (CLOCK and XTAL) in parallel with a resistance (10MΩ typ). Frequency trimming capacitors may be required at terminals 1 and 39. For additional information, see Application Note AN6565. WAIT, CLEAR (2 Control Lines) Provide four control modes as listed in the following truth table: CLEAR L L H H WAIT L H L H MODE LOAD RESET PAUSE RUN Architecture The CPU block diagram is shown in Figure 2. The principal feature of this system is a register array (R) consisting of sixteen 16-bit scratchpad registers. Individual registers in the array (R) are designated (selected) by a 4-bit binary code from one of the 4-bit registers labeled N, P and X. The contents of any register can be directed to any one of the following three paths: 1. The external memory (multiplexed, higher-order byte first, on to 8 memory address lines). 2. The D register (either of the two bytes can be gated to D). 3. The increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit register. The three paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. With two exceptions, CPU instruction consists of two 8clock-pulse machine cycles. The first cycle is the fetch cycle, and the second - and third if necessary - are execute cycles. During the fetch cycle the four bits in the P designator select one of the 16 registers R(P) as the current program counter. The selected register R(P) contains the address of the memory location from which the instruction is to be fetched. When the instruction is read out from the memory, the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the N register. The content of the program counter is automatically incremented by one so that R(P) is now “pointing” to the next byte in the memory. The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of instruction fetched: 1. Designate one of the 16 registers in R to be acted upon during register operations. 2. Indicate to the I/O devices a command code or device selection code for peripherals. 3. Indicate the specific operation to be executed during the ALU instructions, types of test to be performed during the Branch instruction, or the specific operation required in a class of miscellaneous instructions (70 - 73 and 78 - 7B). 4. Indicate the value to be loaded into P to designate a new register to be used as the program counter R(P). 5. Indicate the value to be loaded into X to designate a new register to be used as data pointer R(X). The registers in R can be assigned by a programmer in three different ways: as program counters, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data. Program Counters Any register can be the main program counter; the address of the selected register is held in the P designator. Other reg- VDD, VSS, VCC (Power Levels) The internal voltage supply VDD is isolated from the Input/Output voltage supply VCC so that the processor may operate at maximum speed while interfacing with peripheral devices operating at lower voltage. VCC must be less than or equal to VDD. All outputs swing from VSS to VCC. The recommended input voltage swing is VSS to VCC. 3-20 CDP1802A, CDP1802AC, CDP1802BC isters in R can be used as subroutine program counters. By single instruction the contents of the P register can be changed to effect a “call” to a subroutine. When interrupts are being serviced, register R(1) is used as the program counter for the user's interrupt servicing routine. After reset, and during a DMA operation, R(0) is used as the program counter. At all other times the register designated as program counter is at the discretion of the user. Data Pointers The registers in R may be used as data pointers to indicate a location in memory. The register designated by X (i.e., R(X)) points to memory for the following instructions (see Table 1). 1. ALU operations F1 - F5, F7, 74, 75, 77 2. Output instructions 61 through 67 3. Input instructions 69 through 6F 4. Certain miscellaneous instructions - 70 - 73, 78, 60, F0 The register designated by N (i.e., R(N)) points to memory for the “load D from memory” instructions 0N and 4N and the “Store D” instruction 5N. The register designated by P (i.e., the program counter) is used as the data pointer for ALU instructions F8 - FD, FF, 7C, 7D, 7F. During these instruction executions, the operation is referred to as “data immediate”. Another important use of R as a data pointer supports the built-in Direct-Memory-Access (DMA) function. When a DMA-ln or DMA-Out request is received, one machine cycle is “stolen”. This operation occurs at the end of the execute machine cycle in the current instruction. Register R(0) is always used as the data pointer during the DMA operation. The data is read from (DMA-Out) or written into (DMA-ln) the memory location pointed to by the R(0) register. At the end of the transfer, R(0) is incremented by one so that the processor is ready to act upon the next DMA byte transfer request. This feature in the 1800-series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during CRT-display-refresh cycles. Data Registers When registers in R are used to store bytes of data, four instructions are provided which allow D to receive from or write into either the higher-order or lower-order byte portions of the register designated by N. By this mechanism (together with loading by data immediate) program pointer and data pointer designations are initialized. Also, this technique allows scratchpad registers in R to be used to hold general data. By employing increment or decrement instructions, such registers may be used as loop counters. The Q Flip-Flop An internal flip-flop, Q, can be set or reset by instruction and can be sensed by conditional branch instructions. The output of Q is also available as a microprocessor output. Interrupt Servicing Register R(1) is always used as the program counter whenever interrupt servicing is initiated. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the current instruction), the contents of the X and P registers are stored in the temporary register T, and X and P are set to new values; hex digit 2 in X and hex digit 1 in P. Interrupt Enable is automatically deactivated to inhibit further interrupts. The user's interrupt routine is now in control; the contents of T may be saved by means of a single instruction (78) in the memory location pointed to by R(X). At the conclusion of the interrupt, the user's routine may restore the pre-interrupted value of X and P with a single instruction (70 or 71). The Interrupt Enable flip-flop can be activated to permit further interrupts or can be disabled to prevent them. CPU Register Summary D DF B R P X N I T lE Q 8 Bits 1-Bit 8 Bits 16 Bits 4 Bits 4 Bits 4 Bits 4 Bits 8 Bits 1-Bit 1-Bit Data Register (Accumulator) Data Flag (ALU Carry) Auxiliary Holding Register 1 of 16 Scratchpad Registers Designates which register is Program Counter Designates which register is Data Pointer Holds Low-Order Instruction Digit Holds High-Order Instruction Digit Holds old X, P after Interrupt (X is high nibble) Interrupt Enable Output Flip-Flop CDP1802 Control Modes The WAIT and CLEAR lines provide four control modes as listed in the following truth table: CLEAR L L H H WAIT L H L H MODE LOAD RESET PAUSE RUN The function of the modes are defined as follows: Load Holds the CPU in the IDLE execution state and allows an I/O device to load the memory without the need for a “bootstrap” loader. It modifies the IDLE condition so that DMA-lN operation does not force execution of the next instruction. Reset Registers l, N, Q are reset, lE is set and 0’s (VSS) are placed on the data bus. TPA and TPB are suppressed while reset is held and the CPU is placed in S1. The first machine cycle after termination of reset is an initialization cycle which requires 9 clock pulses. During this cycle the CPU remains in S1 and register X, P, and R(0) are reset. Interrupt and DMA servicing are 3-21 CDP1802A, CDP1802AC, CDP1802BC suppressed during the initialization cycle. The next cycle is an S0, S1, or an S2 but never an S3. With the use of a 71 instruction followed by 00 at memory locations 0000 and 0001, this feature may be used to reset IE, so as to preclude interrupts until ready for them. Power-up reset can be realized by connecting an RC network directly to the CLEAR pin, since it has a Schmitt triggered input, see Figure 24. VCC RS CLEAR 3 C CDP1802 THE RC TIME CONSTANT SHOULD BE GREATER THAN THE OSCILLATOR START-UP TIME (TYPICALLY 20ms) Run-Mode State Transitions The CPU state transitions when in the RUN and RESET modes are shown in Figure 25. Each machine cycle requires the same period of time, 8 clock pulses, except the initialization cycle, which requires 9 clock pulses. The execution of an instruction requires either two or three machine cycles, S0 followed by a single S1 cycle or two S1 cycles. S2 is the response to a DMA request and S3 is the interrupt response. Table 2 shows the conditions on Data Bus and Memory Address lines during all machine states. Instruction Set The CPU instruction summary is given in Table 1. Hexadecimal notation is used to refer to the 4-bit binary codes. FIGURE 24. RESET DIAGRAM In all registers bits are numbered from the least significant bit (LSB) to the most significant bit (MSB) starting with 0. R(W): Register designated by W, where W = N or X, or P R(W).0: Lower order byte of R(W) R(W).1: Higher order byte of R(W) Operation Notation M(R(N)) → D; R(N) + 1 → R(N) This notation means: The memory byte pointed to by R(N) is loaded into D, and R(N) is incremented by 1. Pause Stops the internal CPU timing generator on the first negative high-to-low transition of the input clock. The oscillator continues to operate, but subsequent clock transitions are ignored. Run May be initiated from the Pause or Reset mode functions. If initiated from Pause, the CPU resumes operation on the first negative high-to-low transition of the input clock. When initiated from the Reset operation, the first machine cycle following Reset is always the initialization cycle. The initialization cycle is then followed by a DMA (S2) cycle or fetch (S0) from location 0000 in memory. IDLE • DMA • INT FORCE S1 S1 RESET (LONG BRANCH, LONG SKIP, NOP, ETC.) DMA S1 EXECUTE S1 INIT DMA DMA DMA DMA • IDLE • INT INT • DMA S2 DMA DMA • INT S0 FETCH DMA S3 INT DMA PRIORITY: FORCE S0, S1 DMA IN DMA OUT INT INT • DMA FIGURE 25. STATE TRANSITION DIAGRAM 3-22 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) OP CODE INSTRUCTION MEMORY REFERENCE LOAD VIA N LOAD ADVANCE LOAD VIA X LOAD VIA X AND ADVANCE LOAD IMMEDIATE STORE VIA N STORE VIA X AND DECREMENT REGISTER OPERATIONS INCREMENT REG N DECREMENT REG N INCREMENT REG X GET LOW REG N PUT LOW REG N GET HIGH REG N PUT HIGH REG N LOGIC OPERATIONS (Note 1) OR OR IMMEDIATE EXCLUSIVE OR EXCLUSIVE OR IMMEDIATE AND AND IMMEDIATE SHIFT RIGHT SHIFT RIGHT WITH CARRY RING SHIFT RIGHT SHIFT LEFT SHIFT LEFT WITH CARRY RING SHIFT LEFT ARITHMETIC OPERATIONS (Note 1) ADD ADD IMMEDIATE ADD WITH CARRY ADD WITH CARRY, IMMEDIATE SUBTRACT D SUBTRACT D IMMEDIATE SUBTRACT D WITH BORROW MNEMONIC OPERATION LDN LDA LDX LDXA LDl STR STXD 0N 4N F0 72 F8 5N 73 M(R(N)) → D; FOR N not 0 M(R(N)) → D; R(N) + 1 → R(N) M(R(X)) → D M(R(X)) → D; R(X) + 1 → R(X) M(R(P)) → D; R(P) + 1 → R(P) D → M(R(N)) D → M(R(X)); R(X) - 1 → R(X) INC DEC IRX GLO PLO GHl PHI 1N 2N 60 8N AN 9N BN R(N) + 1 → R(N) R(N) - 1 → R(N) R(X) + 1 → R(X) R(N).0 → D D → R(N).0 R(N).1 → D D → R(N).1 OR ORl XOR XRI AND ANl SHR SHRC RSHR SHL SHLC RSHL F1 F9 F3 FB F2 FA F6 76 (Note 2) 76 (Note 2) FE 7E (Note 2) 7E (Note 2) M(R(X)) OR D → D M(R(P)) OR D → D; R(P) + 1 → R(P) M(R(X)) XOR D → D M(R(P)) XOR D → D; R(P) + 1 → R(P) M(R(X)) AND D → D M(R(P)) AND D → D; R(P) + 1 → R(P) SHIFT D RIGHT, LSB(D) → DF, 0 → MSB(D) SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D) SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D) SHIFT D LEFT, MSB(D) → DF, 0 → LSB(D) SHIFT D LEFT, MSB(D) → DF, DF → LSB(D) SHIFT D LEFT, MSB(D) → DF, DF → LSB(D) ADD ADl ADC ADCl SD SDl SDB F4 FC 74 7C F5 FD 75 M(R(X)) + D → DF, D M(R(P)) + D → DF, D; R(P) + 1 → R(P) M(R(X)) + D + DF → DF, D M(R(P)) + D + DF → DF, D; R(P) + 1 → R(P) M(R(X)) - D → DF, D M(R(P)) - D → DF, D; R(P) + 1 → R(P) M(R(X)) - D - (NOT DF) → DF, D 3-23 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) OP CODE 7D F7 FF 77 7F INSTRUCTION SUBTRACT D WITH BORROW, IMMEDIATE SUBTRACT MEMORY SUBTRACT MEMORY IMMEDIATE SUBTRACT MEMORY WITH BORROW SUBTRACT MEMORY WITH BORROW, IMMEDIATE BRANCH INSTRUCTIONS - SHORT BRANCH SHORT BRANCH NO SHORT BRANCH (See SKP) SHORT BRANCH IF D = 0 SHORT BRANCH IF D NOT 0 SHORT BRANCH IF DF = 1 SHORT BRANCH IF POS OR ZERO SHORT BRANCH IF EQUAL OR GREATER SHORT BRANCH IF DF = 0 SHORT BRANCH IF MINUS SHORT BRANCH IF LESS SHORT BRANCH IF Q = 1 SHORT BRANCH IF Q = 0 SHORT BRANCH IF EF1 = 1 (EF1 = VSS) SHORT BRANCH IF EF1 = 0 (EF1 = VCC) SHORT BRANCH IF EF2 = 1 (EF2 = VSS) SHORT BRANCH IF EF2 = 0 (EF2 = VCC) SHORT BRANCH IF EF3 = 1 (EF3 = VSS) SHORT BRANCH IF EF3 = 0 (EF3 = VCC) SHORT BRANCH IF EF4 = 1 (EF4 = VSS) SHORT BRANCH IF EF4 = 0 (EF4 = VCC) BRANCH INSTRUCTIONS - LONG BRANCH LONG BRANCH NO LONG BRANCH (See LSKP) LONG BRANCH IF D = 0 LONG BRANCH IF D NOT 0 LONG BRANCH IF DF = 1 LONG BRANCH IF DF = 0 LONG BRANCH IF Q = 1 MNEMONIC SDBl SM SMl SMB SMBl OPERATION M(R(P)) - D - (Not DF) → DF, D; R(P) + 1 → R(P) D-M(R(X)) → DF, D D-M(R(P)) → DF, D; R(P) + 1 → R(P) D-M(R(X))-(NOT DF) → DF, D D-M(R(P))-(NOT DF) → DF, D; R(P) + 1 → R(P) BR NBR BZ BNZ BDF BPZ BGE BNF BM BL BQ BNQ B1 BN1 B2 BN2 B3 BN3 B4 BN4 30 38 (Note 2) 32 3A 33 (Note 2) M(R(P)) → R(P).0 R(P) + 1 → R(P) IF D = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF D NOT 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF DF = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) 3B (Note 2) IF DF = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) 31 39 34 3C 35 3D 36 3E 37 3F IF Q = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF Q = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF1 =1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF1 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF2 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF2 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF3 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF3 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF4 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) IF EF4 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) LBR NLBR LBZ LBNZ LBDF LBNF LBQ C0 C8 (Note 2) C2 CA C3 CB C1 M(R(P)) → R(P). 1, M(R(P) + 1) → R(P).0 R(P) = 2 → R(P) lF D = 0, M(R(P)) → R(P).1, M(R(P) +1) → R(P).0, ELSE R(P) + 2 → R(P) IF D Not 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) lF DF = 1, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) IF DF = 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) IF Q = 1, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) 3-24 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) OP CODE C9 INSTRUCTION LONG BRANCH lF Q = 0 SKIP INSTRUCTIONS SHORT SKIP (See NBR) LONG SKIP (See NLBR) LONG SKIP IF D = 0 LONG SKIP IF D NOT 0 LONG SKIP IF DF = 1 LONG SKIP IF DF = 0 LONG SKIP lF Q = 1 LONG SKIP IF Q = 0 LONG SKIP IF lE = 1 CONTROL INSTRUCTIONS IDLE NO OPERATION SET P SET X SET Q RESET Q SAVE PUSH X, P TO STACK RETURN DISABLE INPUT - OUTPUT BYTE TRANSFER OUTPUT 1 OUTPUT 2 OUTPUT 3 OUTPUT 4 OUTPUT 5 OUTPUT 6 OUTPUT 7 INPUT 1 INPUT 2 INPUT 3 INPUT 4 INPUT 5 INPUT 6 INPUT 7 MNEMONIC LBNQ OPERATION lF Q = 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0 EISE R(P) + 2 → R(P) SKP LSKP LSZ LSNZ LSDF LSNF LSQ LSNQ LSlE 38 (Note 2) C8 (Note 2) CE C6 CF C7 CD C5 CC R(P) + 1 → R(P) R(P) + 2 → R(P) IF D = 0, R(P) + 2 → R(P), ELSE CONTINUE IF D Not 0, R(P) + 2 → R(P), ELSE CONTINUE IF DF = 1, R(P) + 2 → R(P), ELSE CONTINUE IF DF = 0, R(P) + 2 → R(P), ELSE CONTINUE IF Q = 1, R(P) + 2 → R(P), ELSE CONTINUE IF Q = 0, R(P) + 2 → R(P), ELSE CONTINUE IF IE = 1, R(P) + 2 → R(P), ELSE CONTINUE lDL NOP SEP SEX SEQ REQ SAV MARK RET DlS 00 (Note 3) C4 DN EN 7B 7A 78 79 70 71 WAIT FOR DMA OR INTERRUPT; M(R(0)) → BUS CONTINUE N→P N→X 1→Q 0→Q T → M(R(X)) (X, P) → T; (X, P) → M(R(2)), THEN P → X; R(2) - 1 → R(2) M(R(X)) → (X, P); R(X) + 1 → R(X), 1 → lE M(R(X)) → (X, P); R(X) + 1 → R(X), 0 → lE OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 INP 1 INP 2 INP 3 INP 4 INP 5 INP 6 INP 7 61 62 63 64 65 66 67 69 6A 6B 6C 6D 6E 6F M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 1 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 2 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 3 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 4 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 5 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 6 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 7 BUS → M(R(X)); BUS → D; N LINES = 1 BUS → M(R(X)); BUS → D; N LINES = 2 BUS → M(R(X)); BUS → D; N LINES = 3 BUS → M(R(X)); BUS → D; N LINES = 4 BUS → M(R(X)); BUS → D; N LINES = 5 BUS → M(R(X)); BUS → D; N LINES = 6 BUS → M(R(X)); BUS → D; N LINES = 7 3-25 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) OP CODE INSTRUCTION NOTES: (For Table 1) MNEMONIC OPERATION 1. The arithmetic operations and the shift instructions are the only instructions that can alter the DF. After an add instruction: DF = 1 denotes a carry has occurred DF = 0 Denotes a carry has not occurred After a subtract instruction: DF = 1 denotes no borrow. D is a true positive number DF = 0 denotes a borrow. D is two’s complement The syntax “-(not DF)” denotes the subtraction of the borrow. 2. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed. 3. An idle instruction initiates a repeating S1 cycle. The processor will continue to idle until an I/O request (INTERRUPT, DMA-lN, or DMA- OUT) is activated. When the request is acknowledged, the idle cycle is terminated and the I/O request is serviced, and then normal operation is resumed. 4. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute). Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, the branching address. The long-branch instructions can: a. Branch unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Effect an unconditional no branch If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low order bytes of the current program counter, respectively. This operation effects a branch to any memory location. If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and executed. This operation is taken for the case of unconditional no branch (NLBR). 5. The short-branch instructions are two bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address. The short branch instruction can: a. Branch unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Test the status (1 or 0) of the four EF flags f. Effect an unconditional no branch If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched and executed. This same action is taken in the case of unconditional no branch (NBR). 6. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions. The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it. Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional no-branch instruction (NBR) except that the skipped-over byte is not considered part of the program. The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute). They can: a. Skip unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Test for IE = 1 If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus two bytes are skipped over, and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken. Execution is continued by fetching the next instruction in sequence. 3-26 CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES DATA BUS 00 00 MRP MR0 MRN Float Float MRP MRN D MRX MRX MEMORY ADDRESS XXXX XXXX RP RO RN RN RN RP RN RN RX RX N LINES 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 BUS → MRX, D Data from I/O Device RX 1 0 1 2 3 4 5 6 7 MRX → (X, P); RX + 1 → RX; 1 → lE MRX → (X, P); RX + 1 → RX; 0 → lE MRX → D; RX + 1 → RX D → MRX; RX - 1 → RX MRX + D + DF → DF, D MRX - D - DFN → DF, D LSB(D) → DF; DF → MSB(D) D - MRX - DFN → DF, D T → MRX MRX MRX MRX D MRX MRX Float MRX T RX RX RX RX RX RX RX RX RX 0 0 0 1 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 STATE S1 I N SYMBOL RESET OPERATION 0 → I, N, Q, X, P; 1 → lE MRD 1 1 0 0 0 1 1 0 0 1 0 0 MWR 1 1 1 1 1 1 1 1 1 0 1 1 NOTES 1 2 3 4, Fig. 8 Fig. 8 Fig. 6 Fig. 6 Fig. 8 Fig. 8 Fig. 7 Fig. 7 Fig. 11 Fig. 11 Fig. 11 Fig. 11 Fig. 11 Fig. 11 Fig. 11 Fig. 10 Fig. 10 Fig. 10 Fig. 10 Fig. 10 Fig. 10 Fig. 10 Fig. 8 Fig. 8 Fig. 8 Fig. 7 Fig. 8 Fig. 8 Fig. 6 Fig. 8 Fig. 7 Initialize, Not Programmer 0000 → R Accessible S0 S1 0 0 1 2 3 4 5 6 6 0 1-F 0-F 0-F 0-F 0-F 0-F 0 1 2 3 4 5 6 7 9 A B C D E F 7 0 1 2 3 4 5 6 7 8 FETCH lDL LDN INC DEC Short Branch LDA STR IRX OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 INP 1 INP 2 INP 3 INP 4 INP5 INP6 INP7 RET DlS LDXA STXD ADC SDB SHRC SMB SAV MRP → l, N; RP + 1 → RP IDLE MRN → D RN + 1 → RN RN - 1 → RN Taken: MRP → RP.0 Not Taken; RP + 1 → RP MRN → D; RN + 1 → RN D → MRN RX + 1 → RX MRX → BUS; RX + 1 → RX 3-27 CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS T Float Float MRP MRP Float MRP RN.0 RN.1 D D MRP M(RP + 1) MRP M(RP + 1) MRP M(RP + 1) MRP MRP MRP MRP NN NN MRX MRX MEMORY ADDRESS R2 RP RP RP RP RP RP RN RN RN RN RP RP + 1 RP RP + 1 RP RP + 1 RP RP RP RP RN RN RX RX N LINES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATE S1 I 7 N 9 A B C D E F SYMBOL MARK REQ SEQ ADCl SDBl SHLC SMBl GLO GHl PLO PHI Long Branch OPERATION (X, P) → T, MR2; P → X; R2 - 1 → R2 0→Q 1→Q MRP + D + DF → DF, D; RP + 1 MRP - D - DFN → DF, D; RP + 1 MSB(D) → DF; DF → LSB(D) D - MRP - DFN → DF, D; RP + 1 RN.0 → D RN.1 → D D → RN.0 D → RN.1 Taken: MRP → B; RP + 1 → RP Taken: B → RP.1; MRP → RP.0 Not Taken: RP + 1 → RP Not Taken: RP + 1 → RP MRD 1 1 1 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 MWR 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES Fig. 7 Fig. 6 Fig. 6 Fig. 8 Fig. 8 Fig. 6 Fig. 8 Fig. 6 Fig. 6 Fig. 6 Fig. 6 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 9 Fig. 6 Fig. 6 Fig. 8 Fig. 8 8 9 A B S1#1 #2 S1#1 #2 S1#1 #2 S1#1 #2 S1#1 #2 S1 D E S1 F C 0-F 0-F 0-F 0-F 0 - 3, 8-B 5 6 7 C D E F 4 Long Skip Taken: RP + 1 → RP Taken: RP + 1 → RP Not Taken: No Operation Not Taken: No Operation NOP No Operation No Operation 0-F 0-F 0 1 2 3 4 5 7 6 SEP SEX LDX OR AND XOR ADD SD SM SHR N→P N→X MRX → D MRX OR D → D MRX AND D → D MRX XOR D → D MRX + D → DF, D MRX - D → DF, D D - MRX → DF, D LSB(D) → DF; 0 → MSB(D) Float RX 1 1 0 Fig. 6 3-28 CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS MRP MEMORY ADDRESS RP N LINES 0 STATE S1 I F N 8 9 A B C D F E SYMBOL LDl ORl ANl XRl ADl SDl SMl SHL DMA IN DMAOUT OPERATION MRP → D; RP + 1 → RP MRP OR D → D; RP + 1 → RP MRP AND D → D; RP + 1 → RP MRP XOR D → D; RP + 1 → RP MRP + D → DF, D; RP + 1 → RP MRP - D → DF, D; RP + 1 → RP D - MRP → DF, D; RP +1 → RP MSB(D) → DF; 0 → LSB(D) BUS → MR0; R0 + 1 → R0 MR0 → BUS; R0 + 1 → R0 X, P → T; 0 → lE, 1 → P; 2→X IDLE (CLEAR, WAlT = 0) MRD 0 MWR 1 NOTES Fig. 8 Float Data from I/O Device MR0 Float M(R0 - 1) RP R0 R0 RN R0 - 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 Fig. 6 6, Fig. 12 6, Fig. 13 Fig. 14 5, Fig. 8 S2 S3 S1 NOTES: INTERRUPT LOAD 1. lE = 1, TPA, TPB suppressed, state = S1. 2. BUS = 0 for entire cycle. 3. Next state always S1. 4. Wait for DMA or INTERRUPT. 5. Suppress TPA, wait for DMA. 6. IN REQUEST has priority over OUT REQUEST. 7. See Timing Waveforms, Figure 5 through Figure 14 for machine cycles. Operating and Handling Considerations Handling All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. Operating Operating Voltage - During operation near the maximum supply voltage limit care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. Input Signals - To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 10mA even when the power supply is off. Unused Inputs - A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS, whichever is appropriate. Output Short Circuits - Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-29