CP82C82

TM 82C82 CMOS Octal Latching Bus Driver Description The Intersil 82C82 is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C82 provides an eight-bit parallel latch/buffer in a 20 pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to state-of-the-art microprocessor systems. March 1997 Features • Full Eight-Bit Parallel Latching Buffer • Bipolar 8282 Compatible • Three-State Noninverting Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. • Gated Inputs: - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors • Single 5V Power Supply • Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA • Operating Temperature Ranges - C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC - I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Ordering Information PART NUMBER CP82C82 IP82C82 CS82C82 IS82C82 CD82C82 ID82C82 MD82C82/B 8406701RA MR82C82/B 84067012A TEMP. RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC SMD # -55oC to +125oC 20 Pad CLCC SMD # J20.A 20 Ld PLCC N20.35 PACKAGE 20 Ld PDIP PKG. NO. E20.3 20 Ld CERDIP F20.3 Pinouts 82C82 (PDIP, CERDIP) TOP VIEW 82C82 (PLCC, CLCC) TOP VIEW DO0 DI2 DI1 DI0 VCC STB X H H DI3 4 DI4 5 DI5 6 DI6 7 DI7 8 18 DO1 17 DO2 16 DO3 15 DO4 14 DO5 H L X † ↓ TRUTH TABLE OE H L L L DI X L H X DO Hi-Z L H † 3 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 OE 1 2 3 4 5 6 7 8 9 20 VCC 19 DO0 18 DO1 17 DO2 16 DO3 15 DO4 14 DO5 13 DO6 12 DO7 11 STB 2 1 20 19 = Logic One = Logic Zero = Don’t Care = Latched to Value of Last Data Hi-Z = High Impedance ↓ = Neg. Transition PIN NAMES 9 OE 10 GND 11 STB 12 DO7 13 DO6 GND 10 PIN DI0-DI7 DO0-DO7 STB OE DESCRIPTION Data Input Pins Data Output Pins Active High Strobe Active Low Output Enable CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved FN2975.1 274 82C82 Functional Diagram DIO DQ CLK DO0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO1 DO2 DO3 DO4 DO5 DO6 DO7 STB OE Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the input and cause a disruption in device operation. The Intersil 82C8X Series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower Nchannel (see Figures 1, 2). No new current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. DC input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the trans parent mode (STB = logic one). ICC remains below the maximum ICC standby specification of l0mA during the time inputs are disabled, thereby, greatly reducing the average power dissipation of the 82C8X series devices Typical 82C82 System Example In a typical 80C86/88 system, the 82C82 is used to latch multiplexed addresses and the STB input is driven by ALE (Address Latch Enable) (see Figure 3). The high pulse width of ALE is approximately 100ns with a bus cycle time of 800ns (80C86/88 at 5MHz). The 82C82 inputs are active only 12.5% of the bus cycle time. Average power dissipation VCC VCC P P OE STB DATA IN N N N N N P INTERNAL DATA DATA IN VCC N P P INTERNAL DATA VCC P FIGURE 16. 82C82/83H FIGURE 17. 82C86H/87H GATED INPUTS 275 82C82 Application Information Decoupling Capacitors The transient current required to charge and discharge the 300pF load capacitance specified in the 82C82 data sheet is determined by: I = C L (dv/dt) (EQ. 1) that dv/dt is constant; I = CL ( V C C x 80% ) ---------------------------------tR/tF (EQ. 2) (EQ. 3) Assuming that all outputs change state at the same time and where tR = 20ns, V CC = 5.0V, CL = 300pF on each of eight outputs. I = ( 8 x 300 x 10 -12 ) x (5.0V x 0.8)/ ( 20 x 10 VCC P –9 ) = 480mA VCC (EQ. 4) P ALE MULTIPLEXED BUS ICC STB ADDRESS ADDRESS DATA IN N N P INTERNAL DATA N FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS Absolute Maximum Ratings Thermal Information 276 82C82 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) θJA θJC CERDIP . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W 18oC/W CLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W 22oC/W PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 75 N/A PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC (PLCC Lead Tips Only) Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C82C82); TA = -40oC to +85oC (I82C82); TA = -55oC to +125oC (M82C82) MAX 0.8 0.4 1.0 10.0 UNITS V V V V V V µA µA µA IOH = -8mA, OE = GND IOH = -100µA, OE = GND IOL = 8mA, OE = GND VIN = GND or V CC, DIP Pins 1-9, 11 VO = GND or VCC, OE ≥ VCC -0.5V DIP Pins 12-19 VIN = VCC or GND, VCC = 5.5V, Outputs Open TA = +25oC, VCC = 5V, Typical (See Note 2) TEST CONDITIONS C82C82, I82C82 (Note 1) M82C82 (Note 1) SYMBOL VIH PARAMETER Logical One Input Voltage MIN 2.0 2.2 V IL VOH Logical Zero Input Voltage Logical One Output Voltage 2.9 VCC -0.4V VOL II IO Logical Zero Output Voltage Input Leakage Current Output Leakage Current -1.0 -10.0 ICCSB Standby Power Supply Current Operating Power Supply Current - 10 ICCOP - 1 mA/MHz NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH min to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at VCC -0.4. 2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz µ P, ALE = 1.25MHz, ICCOP = 1.25mA). Capacitance SYMBOL CIN COUT TA = +25oC PARAMETER Input Capacitance Output Capacitance TYPICAL 13 20 UNITS pF pF TEST CONDITIONS Freq = 1MHz, all measurements are referenced to device GND 277 82C82 AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C82C82); CL = 300pF (Note 1), Freq = 1MHz TA = -40oC to +85oC (I82C82); TA = -55oC to +125oC (M82C82) MIN 0 25 25 MAX 35 55 35 50 20 UNITS ns ns ns ns ns ns ns ns TEST CONDITIONS Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 SYMBOL (1) (2) (3) (4) (5) (6) (7) (8) TIVOV TSHOV TEHOZ TELOV TIVSL TSLIX TSHSL TR, TF PARAMETER Propagation Delay Input to Output Propagation Delay STB to Output Output Disable Time Output Enable Time Input to STB Setup Time Input to STB Hold Time STB High Time Input Rise/Fall Times NOTES: 1. Output load capacitance is rated at 300pF for ceramic and plastic packages. 2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V. 3. Input test signals must switch between VIL - 0.4V and VIH +0.4V. Timing Waveforms TR, TF (8) INPUTS 2.0V 0.8V TIVSL (5) STB TSHSL (7) OE TIVOV (1) OUTPUTS TSHOV (2) TSLIX (6) TEHOZ (3) VOH -0.1V VOL +0.1V TELOV (4) 2.4V 0.8V Test Load Circuits 1.7V 0.6V 3.3V 150Ω OUTPUT TEST POINT 300Ω OUTPUT TEST POINT 300 Ω OUTPUT TEST POINT 300pF (NOTE) 50pF (NOTE) 50pF (NOTE) TIVOV, TSHOV, TELOV TEHOZ OUTPUT HIGH DISABLE TEHOZ OUTPUT LOW DISABLE NOTE: Includes stray and jig capacitance. 278 82C82 Burn-In Circuits MD82C82 CERDIP VCC F2 F2 F2 F2 F2 F2 F2 F2 F0 R1 R1 R1 R1 R1 R1 R1 R1 R1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 R1 A A A A A A A A F1 R2 A R2 VCC C1 MR82C82 CLCC VCC F2 F2 R3 R3 F2 R3 VCC/2 R3 C1 3 F2 F2 F2 F2 F2 R3 R3 R3 R3 R3 4 5 6 7 8 9 R3 2 1 20 19 18 17 16 15 14 R3 R3 R3 R3 R3 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 10 11 R3 12 R3 13 R3 F0 F1 VCC/2 VCC/2 NOTES: 1. VCC = 5.5 ± 0.5V, GND = 0V. 2. VIH = 4.5V ±10%. 3. V IL = -0.2V to 0.4V. 4. R1 = 47kΩ ±5%. 5. R2 = 2.0kΩ ±5%. 6. R3 = 4.2kΩ ±5%. 7. R4 = 470kΩ ±5%. 8. C1 = 0.01µF minimum. 9. F0 = 100kHz ±10%. 10. F1 = F0/2, F2 = F1/2. 279 82C82 Die Characteristics DIE DIMENSIONS: 118.1 x 92.1 x 19 ±1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: 2.00 x 105 A/cm 2 Metallization Mask Layout 82C82 D11 D10 VCC DO0 D01 2 1 20 19 18 D12 3 17 DO2 16 D13 D14 4 5 15 DO3 DO4 14 DO5 D15 6 13 DO6 D16 7 8 9 10 11 12 D17 OE GND STB DO7 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 280