DATASHEET
EL4340, EL4342
FN7421
Rev.4.00
Oct 4, 2017
500MHz Triple Multiplexing Amplifiers
The EL4340, EL4342 are fixed unity gain mux amps featuring
high slew rates and excellent bandwidth for video switching.
These devices feature a high impedance output state (HIZ) that
enables the outputs of multiple devices to be wired together. A
power-down mode (ENABLE) is included to turn off un-needed
circuitry in power sensitive applications. The ENABLE pin, when
pulled high, sets the EL4340, EL4342 into standby power
mode - consuming just 18mW. An added feature in the
EL4340 is a latch enable function (LE) that allows independent
logic control using a common logic bus.
Features
Ordering Information
• ±870 V/µs slew rate
PART
NUMBER
( Notes 1, 2, 3)
• Triple 2:1 and 4:1 multiplexers for RGB
• Internally set gain-of-1
• High speed three-state outputs (HIZ)
• Power-down mode (ENABLE)
• Latch enable (EL4340)
• ±5V operation
• 500MHz bandwidth
PART
MARKING
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
• Typical supply currents 10mA/ch (EL4340) and 15.3mA/ch
(EL4342)
EL4340IUZ
EL4340IUZ
24 Ld QSOP
MDP0040
• Pb-free (RoHS compliant)
EL4342ILZA
4342ILZ
32 Ld 5x6 QFN
L32.5x6A
EL4340IUZ-EVAL
Evaluation Board
Applications
EL4342ILZA-EVAL
Evaluation Board
NOTES:
1. Add “-T13” suffix for 2.5k unit or “-T7” suffix for 1k unit tape and reel
options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see product information page
for EL4340, EL4342. For more information on MSL, refer to TB363.
Related Literature
• For a full list of related documents, visit our website
- EL4340, EL4342 product pages
• HDTV/DTV analog inputs
• Video projectors
• Computer monitors
• Set-top boxes
• Security video
• Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE EL4340
S0
ENABLE
HIZ
LE
OUTPUT
0
0
0
0
INO (A, B, C)
1
0
0
0
IN1 (A, B, C)
X
1
X
X
Power-down
X
0
1
X
High Z
X
0
0
1
Last S0 State
Preserved
TABLE 2. CHANNEL SELECT LOGIC TABLE EL4342
FN7421 Rev.4.00
Oct 4, 2017
S1
S0
ENABLE
HIZ
OUTPUT
0
0
0
0
IN0 (A, B, C)
0
1
0
0
IN1 (A, B, C)
1
0
0
0
IN2 (A, B, C)
1
1
0
0
IN3 (A, B, C)
X
X
1
X
Power-down
X
X
0
1
High Z
Page 1 of 14
EL4340, EL4342
Pin Configurations
EL4340
(24 LD QSOP)
EL4342
(32 LD QFN)
23 LE
IN0B
3
22 ENABLE
NIC
4
21 HIZ
GND B
5
IN0C
6
19 V+
NIC
7
18 OUTB
IN1A
8
NIC
9
26 HIZ
2
27 IN0C
GND A
28 NIC
24 NIC
29 IN0B
1
30 NIC
IN0A
31 IN0A
TOP VIEW
32 GND A
TOP VIEW
IN1A 1
25 ENABLE
NIC 2
24 NIC
IN1B 3
AV=1
AV=1
20 OUTA
22 OUTA
NIC 4
21 V-
IN1C 5
AV=1
23 V+
GND B 6
THERMAL
PAD
17 OUTC
IN2A 7
AV=1
20 OUTB
19 OUTC
16 VAV=1
IN1B 10
NIC 8
AV=1
15 NIC
LATCHED ON HIGH LE
IN3C 16
NIC 15
IN3B 14
NIC 13
13 NIC
IN3A 12
IN1C 12
17 S1
IN2C 10
14 S0
GND C 11
IN2B 9
GND C 11
18 S0
THERMAL PAD INTERNALLY CONNECTED TO V-.
PAD MUST BE TIED TO VNIC = NO INTERNAL CONNECTION
NIC = NO INTERNAL CONNECTION
EN0
S0
EN0
DECODE
EN1
DL Q
C
IN0(A, B, C)
DL Q IN1(A, B, C)
C
S0
S1
AMPLIFIER BIAS
LE
EN1 IN0(A, B, C)
OUT
DECODE
EN3
HIZ
OUT
IN1(A, B, C)
EN2
IN2(A, B, C)
IN3(A, B, C)
AMPLIFIER BIAS
ENABLE
HIZ
A LOGIC HIGH ON LE WILL LATCH THE LAST S0 STATE.
THIS LOGIC STATE IS PRESERVED WHEN CYCLING HIZ
OR ENABLE FUNCTIONS.
FIGURE 1. FUNCTIONAL DIAGRAM EL4340
FN7421 Rev.4.00
Oct 4, 2017
ENABLE
FIGURE 2. FUNCTIONAL DIAGRAM EL4342
Page 2 of 14
EL4340, EL4342
Pin Descriptions
EL4342
(32 Ld QFN)
EL4340
(24 Ld QSOP)
PIN NAME
EQUIVALENT
CIRCUIT
Circuit 1
DESCRIPTION
1
8
IN1A
2, 4, 8, 13, 15,
24, 28, 30
4, 7, 9, 13, 15,
24
NIC
Channel 1 input for output amplifier “A”
3
10
IN1B
5
12
IN1C
Circuit 1
Channel 1 input for output amplifier “C”
6
5
GNDB
Circuit 4
Ground pin for output amplifier “B”
7
NA
IN2A
Circuit 1
Channel 2 input for output amplifier “A”
9
NA
IN2B
Circuit 1
Channel 2 input for output amplifier “B”
Not Internally Connected; it is recommended these pins be tied to ground to minimize
crosstalk.
Circuit 1
Channel 1 input for output amplifier “B”
10
NA
IN2C
Circuit 1
Channel 2 input for output amplifier “C”
11
11
GNDC
Circuit 4
Ground pin for output amplifier “C”
12
NA
IN3A
Circuit 1
Channel 3 input for output amplifier “A”
14
NA
IN3B
Circuit 1
Channel 3 input for output amplifier “B”
16
NA
IN3C
Circuit 1
Channel 3 input for output amplifier “C”
17
NA
S1
Circuit 2
Channel selection pin MSB (binary logic code)
18
14
S0
Circuit 2
Channel selection pin. LSB (binary logic code)
19
17
OUTC
Circuit 3
Output of amplifier “C”
20
18
OUTB
Circuit 3
Output of amplifier “B”
21
16
V-
Circuit 4
Negative power supply
22
20
OUTA
Circuit 3
Output of amplifier “A”
23
19
V+
Circuit 4
Positive power supply
25
22
ENABLE
Circuit 2
Device enable (active low). Internal pull-down resistor ensures the device will be active with
no connection to this pin. A logic High on this pin puts device into power-down mode. In
power-down mode only logic circuitry is active. All logic states are preserved post
power-down. This state is not recommended for logic control where more than one
MUX-amp share the same video output line.
-
23
LE
Circuit 2
Device latch enable on the EL4340. A logic high on LE will latch the last (S0, S1) logic state.
HIZ and ENABLE functions are not latched with the LE pin.
26
21
HIZ
Circuit 2
Output disable (active high). Internal pull-down resistor ensures the device will be active
with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use
this state to control logic when more than one MUX-amp share the same video output line.
27
6
IN0C
Circuit 1
Channel 0 for output amplifier “C”
29
3
IN0B
Circuit 1
Channel 0 for output amplifier “B”
31
1
IN0A
Circuit 1
Channel 0 for output amplifier “A”
32
2
GNDA
Circuit 4
Ground pin for output amplifier “A”
V+
V+
IN
LOGIC PIN
21k
1.2V
33k
-
V-
GNDC
VCIRCUIT 3
CIRCUIT 2
V+
GNDB
OUT
GND
V-
CIRCUIT 1
GNDA
V+
+
THERMAL HEAT SINK PAD
CAPACITIVELY
COUPLED
~1MΩ
VSUBSTRATE
VCIRCUIT 4
FN7421 Rev.4.00
Oct 4, 2017
Page 3 of 14
EL4340, EL4342
Absolute Maximum Ratings
Thermal Information
(TA = +25°C)
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-On Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital & Analog Input Current (Note 6). . . . . . . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . 2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
32 Ld QFN Package (Notes 4, 5) . . . . . . . .
35
1.3 to 8
24 Ld QSOP Package (Note 4) . . . . . . . . . .
88
N/A
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. Refer to
TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND, CL = 5pF unless
otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
30
34
mA
GENERAL
Enabled Supply Current (EL4340)
+IS Enabled
No load, VIN = 0V, Enable Low
21.5
39
46
50
mA
-IS Enabled
No load, VIN = 0V, Enable Low
-32
-30
-21
mA
-48
-46
-36.5
mA
+IS Disabled
No load, VIN = 0V, Enable High
1.75
2.8
4.2
mA
No load, VIN = 0V, Enable High
3
3.5
4
mA
-IS Disabled
No load, VIN = 0V, Enable High
10
100
µA
Enabled Supply Current (EL4342)
Enabled Supply Current (EL4340)
Enabled Supply Current (EL4342)
Disabled Supply Current (EL4340)
Disabled Supply Current (EL4342)
Disabled Supply Current
Positive and Negative Output Swing
VOUT
VIN = ±3.5V, RL = 500Ω
±3.1
±3.4
V
Output Current
IOUT
RL = 10Ω to GND
±80
±135
mA
7
Output Offset Voltage (EL4340)
VOS
-15
Output Offset Voltage (EL4342)
VOS
-10
Input Bias Current
Ib
VIN = 0V
-0.5
-2
+15
mV
+10
mV
-3
µA
HIZ Output Resistance
ROUT
HIZ = Logic High
1.4
Enabled Output Resistance
ROUT
HIZ = Logic Low
0.2
Ω
VIN = ±3.5V
10
MΩ
Input Resistance
Voltage Gain
Output Current in Three-State
RIN
ACL or AV
ITRI
VIN = ±1.5V, RL= 500Ω
VOUT = 0V
MΩ
0.98
0.99
1.02
V/V
8
15
22
µA
LOGIC
Input High Voltage (Logic Inputs)
VIH
2
Input Low Voltage (Logic Inputs)
VIL
Input High Current (Logic Inputs)
IIH
VH = 5V
Input Low Current (Logic Inputs)
IIL
VL = 0V
tS
Step = 1V
215
V
0.8
V
270
340
µA
2
3
µA
AC GENERAL
10
ns
Power Supply Rejection Ratio
PSRR (EL4340) DC, PSRR V+ and V- combined
52
72
dB
Power Supply Rejection Ratio
PSRR (EL4342) DC, PSRR V+ and V- combined
52
56
dB
0.1% Settling Time
FN7421 Rev.4.00
Oct 4, 2017
Page 4 of 14
EL4340, EL4342
Electrical Specifications
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, Input Video = 1VP-P and RL = 500Ω to GND, CL = 5pF unless
otherwise specified. (Continued)
PARAMETER
SYMBOL
Channel Isolation
ISO
Differential Gain Error
dG
Differential Phase Error
dP
CONDITIONS
MIN
f = 10MHz, Ch-Ch X-Talk and Off-Isolation,
CL = 1.5pF
TYP
MAX
UNIT
75
dB
NTC-7, RL = 150, CL = 1.5pF
0.02
%
NTC-7, RL = 150, CL = 1.5pF
0.02
°
-3dB Bandwidth
BW
CL = 1.5pF
500
MHz
0.1dB Bandwidth
FBW
CL = 1.5pF
60
MHz
CL = 4.7pF
120
MHz
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF
±870
V/µs
VIN = 0V, CL = 1.5pF
40
mVP-P
VIN = 0V CL = 1.5pF
300
mVP-P
VIN = 0V CL = 1.5pF
200
mVP-P
VIN = 0V CL = 1.5pF
20
mVP-P
VIN = 0V CL = 1.5pF
200
mVP-P
0.1dB Bandwidth
Slew Rate
SR
SWITCHING CHARACTERISTICS
Channel-to-Channel Switching Glitch
VGLITCH
Enable Switching Glitch
EL4340
HIZ Switching Glitch
Channel-to-Channel Switching Glitch
VGLITCH
Enable Switching Glitch
EL4342
HIZ Switching Glitch
VIN = 0V CL = 1.5pF
200
mVP-P
Channel Switching Time Low to High
tSW-L-H
1.2V logic threshold to 10% movement of
analog output
18
ns
Channel Switching Time High to Low
tSW-H-L
1.2V logic threshold to 10% movement of
analog output
20
ns
10% to 90%
1.1
ns
Rise and Fall Time
tr, tf
Propagation Delay
tpd
10% to 10%
0.9
ns
Latch Enable Hold time (EL4340 only)
tLH
LE = 0
10
ns
Typical Performance Curves
SOURCE POWER = -20dBm
NORMALIZED GAIN (dB)
8
5
4
CL = 16.5pF
6
CL = 11.5pF
4
CL = 7.3pF
CL = 6.2pF
2
0
-2
CL = 4.7pF
-4
CL = 2.2pF
-6
CL INCLUDES 1.5pF
BOARD CAPACITANCE
-8
-10
1
10
CL = 1.5pF
100
SOURCE POWER = -20dBm
3
NORMALIZED GAIN (dB)
10
VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
1k
2
1
0
-1
RL = 100Ω
RL = 150Ω
-2
-3
RL = 500Ω
-4
-5
RL = 1kΩ
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 3. GAIN vs FREQUENCY vs CL
FIGURE 4. GAIN vs FREQUENCY vs RL
FN7421 Rev.4.00
Oct 4, 2017
Page 5 of 14
1k
EL4340, EL4342
Typical Performance Curves
NORMALIZED GAIN (dB)
0.1
100
SOURCE POWER = -20dBm
CL = 4.7pF
0.0
OUTPUT RESISTANCE ()
0.2
VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
-0.1
-0.2
CL = 1.5pF
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
1
1
0.1
0.1
1k
10
100
FREQUENCY (MHz)
10
0.2
0
-0.2
-0.4
OUTPUT VOLTAGE (V)
0.4
RL = 500Ω
CL = 1.5pF
0.6
-0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 8. EL4342 TRANSIENT RESPONSE
FIGURE 7. EL4340 TRANSIENT RESPONSE
0
0
-10
-10
INPUT X TO OUTPUT Y
CROSSTALK
-20
INPUT X TO OUTPUT Y
CROSSTALK
-20
-30
-30
-40
(dB)
(dB)
1k
0.8
RL = 500Ω
CL = 1.5pF
0.6
OFF ISOLATION
INPUT X TO OUTPUT X
-60
-40
-50
-60
-70
-70
-80
-80
-90
-100
0.1
100
FIGURE 6. ROUT vs FREQUENCY
0.8
-50
10
FREQUENCY (MHz)
FIGURE 5. 0.1dB GAIN vs FREQUENCY
OUTPUT VOLTAGE (V)
1
OFF ISOLATION
INPUT X TO OUTPUT X
-90
1
10
100
FREQUENCY (MHz)
FIGURE 9. EL4340 CROSSTALK AND OFF-ISOLATION
FN7421 Rev.4.00
Oct 4, 2017
1k
-100
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 10. EL4342 CROSSTALK AND OFF-ISOLATION
Page 6 of 14
1k
EL4340, EL4342
Typical Performance Curves
VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
20
20
10
PSRR (V+)
0
-10
-10
-20
-20
PSRR (dB)
0
PSRR (V-)
-30
-40
-50
-50
-60
-70
-70
1
10
-80
0.3
1k
1k
FIGURE 12. EL4342 PSRR CHANNELS A, B, C
VIN = 0V
VIN = 1V
S0, S1
50Ω
TERM.
0
0.5V/DIV
0
VOUT A, B, C
0
VOUT A, B, C
20ns/DIV
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
ENABLE
50Ω
TERM.
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V
VIN = 0V
ENABLE
0
VIN = 1V
50Ω
TERM.
1V/DIV
1V/DIV
100
FIGURE 11. EL4340 PSRR CHANNELS A, B, C
20ns/DIV
0
VOUT A, B, C
1V/DIV
100mV/DIV
10
FREQUENCY (MHz)
0
20mV/DIV
1
FREQUENCY (MHz)
S0, S1
50Ω
TERM.
1V/DIV
100
PSRR (V-)
-40
-60
-80
0.3
PSRR (V+)
-30
1V/DIV
PSRR (dB)
10
0
20ns/DIV
FIGURE 15. ENABLE SWITCHING GLITCH VIN = 0V
FN7421 Rev.4.00
Oct 4, 2017
0
VOUT A, B, C
20ns/DIV
FIGURE 16. ENABLE TRANSIENT RESPONSE VIN = 1V
Page 7 of 14
EL4340, EL4342
Typical Performance Curves
HIZ
VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
HIZ
VIN = 0V
0
1V/DIV
0
200mv/DIV
VIN = 1V
50Ω
TERM.
1V/DIV
1V/DIV
50Ω
TERM.
0
VOUT A, B, C
VOUT A, B, C
0
10ns/DIV
10ns/DIV
FIGURE 17. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 18. HIZ TRANSIENT RESPONSE VIN = 1V
60
3.0
50
2.5
POWER DISSIPATION (W)
VOLTAGE NOISE (nV/HZ)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD-QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
40
30
20
10
0
100
10k
QFN32
JA = 35°C/W
2.0
1.5
1.136W
1.0
QSOP24
JA = 88°C/W
0.5
0
1k
2.857W
100k
0
FREQUENCY (Hz)
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C)
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
1.2
1.0
870mW
0.8
QSOP24
JA = 115°C/W
758mW
0.6
QFN32
JA = 125°C/W
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7421 Rev.4.00
Oct 4, 2017
Page 8 of 14
EL4340, EL4342
video cable-driving. The unity-gain current feedback output
amplifiers are stable operating into capacitive loads and
bandwidth is optimized with a load of 5pF in parallel with a
500Ω. Total output capacitance can be split between the PCB
capacitance and an external load capacitor.
AC Test Circuits
EL4340, EL4342
VIN
CL
5PF
50Ω
OR
75Ω
RL
500Ω
Ground Connections
For the best isolation and crosstalk rejection, all GND pins and
NIC pins must connect to the GND plane.
FIGURE 22A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
Control Signals
RS
VIN
50Ω
OR
75Ω
CL
5PF
475Ω
S0, S1, ENABLE, LE, HIZ - These are binary coded, TTL/CMOS
compatible control inputs. The S0, S1 pins select the inputs. All
three amplifiers are switched simultaneously from their respective
inputs. The ENABLE, LE, HIZ pins are used to disable the part to
save power, latch in the last logic state and three-state the output
amplifiers, respectively. For control signal rise and fall times less
than 10ns the use of termination resistors close to the part will
minimize transients coupled to the output.
TEST
EQUIPMENT
EL4340, EL4342
50Ω
OR
75Ω
50Ω
OR
75Ω
FIGURE 22B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR 75Ω
INPUT TERMINATED EQUIPMENT
RS
CL
5pF
50Ω
OR
75Ω
The ESD protection circuits use internal diodes from all pins the
V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for power
supply rates-of-rise in excess of 1V/µs, such as during hot
plugging. Under these conditions, additional methods should be
employed to ensure the rate of rise is not exceeded.
TEST
EQUIPMENT
EL4340, EL4342
VIN
Power-UP Considerations
50Ω OR 75Ω
50Ω
OR
75Ω
FIGURE 22C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE
APPLICATION. BANDWIDTH AND LINEARITY FOR RL
LESS THAN 500Ω WILL BE DEGRADED.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 23) will
shunt damaging currents away from the internal V+ and V- ESD
diodes in the event that the V+ supply is applied to the device
before the V- supply.
FIGURE 22. TEST CIRCUITS
Figure 22A illustrates the optimum output load for testing AC
performance. Figure 22B illustrates the optimun output load
when connecting to 50Ω input terminated equipment.
If positive voltages are applied to the logic or analog video input
pins before V+ is applied, current will flow through the internal
ESD diodes to the V+ pin. The presence of large decoupling
capacitors and the loading effect of other circuits connected to
V+, can result in damaging currents through the ESD diodes and
other active circuits within the device. Therefore, adequate
current limiting on the digital and analog inputs is needed to
prevent damage during the time the voltages on these inputs are
more positive than V+.
Application Information
General
The EL4340, EL4342 triple 2:1 and 4:1 MUX amps are ideal as
the matrix element of high performance switchers and routers.
Key features include buffered high impedance analog inputs and
excellent AC performance at output loads down to 150Ω for
V+ SUPPLY
LOGIC
POWER
GND
SIGNAL
DE-COUPLING
CAPS
SCHOTTKY
PROTECTION
V+
LOGIC
CONTROL
S0
GND
IN0
EXTERNAL
CIRCUITS
V+
V-
V+
V+
OUT
V+
V-
IN1
VV-
V-
V- SUPPLY
FIGURE 23. SCHOTTKY PROTECTION CIRCUIT
FN7421 Rev.4.00
Oct 4, 2017
Page 9 of 14
EL4340, EL4342
HIZ State
An internal pull-down resistor ensures the device will be active
with no connection to the HIZ pin. The HIZ state is established
within approximately 15ns (Figure 18 on page 8) by placing a
logic high (>2V) on the HIZ pin. If the HIZ state is selected, the
output is a high impedance 1.4MΩwithapproximately1.5pF in
parallel with a 10µA bias current from the output. Use this state
when more than one mux shares a common output.
frequency performance may be degraded for traces greater
than one inch, unless strip line are used.
• Match channel-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (for example,
no split planes or PCB gaps under these lines). Avoid vias in the
signal I/O lines.
In the HIZ state the output is three-stated, and maintains its high
Z even in the presence of high slew rates. The supply current
during this state is same as the active state.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
ENABLE and Power-Down States
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The Power-down state is established within
approximately 80ns (Figure 16 on page 7), if a logic high (>2V) is
placed on the ENABLE pin. In the Power-down state, the output
has no leakage but has a large variable capacitance (on the
order of 15pF), and is capable of being back-driven. Under this
condition, large incoming slew rates can cause fault currents of
tens of mA. Do not use this state as a high impedance output
when several MUX amps share the same output line.
LE State
The EL4340 is equipped with a Latch Enable pin. A logic high (>2V)
on the LE pin latches the last logic state. This logic state is
preserved when cycling HIZ or ENABLE functions.
Limiting the Output Current
No output short-circuit current limit exists on these parts. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
Application Example
Figure 24 on page 11 illustrates the use of the EL4342, two
ISL84517 SPST switches, and one NC7ST00P5X NAND gate to
mux 3 different component video signals and one RGB video
signal. The SPDT switches provide the sync signal for the RGB
video and disconnects the sync signal for the component signal.
PC Board Layout
The AC performance of this circuit depends greatly on the care
taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• Minimum of two power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices as
possible - Avoid vias between the cap and the device because
vias add unwanted inductance. Larger caps can be farther
away. When vias are required in a layout, they should be routed
as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins. These
pins are not internally connected to the die. It is recommended
these pins be tied to ground to minimize crosstalk.
The QFN Package Requires Additional PCB
Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the
high resistance IC substrate. Its primary function is to provide
heat sinking for the IC. However, because of the connection to
the V- supply through the substrate, the thermal pad must be tied
to the V- supply to prevent unwanted current flow to the thermal
pad. Do not tie this pin to GND as this could result in large back
biased currents flowing between GND and V-. The EL4342 uses
the package with pad dimensions of D2 = 2.48mm and
E2 = 3.4mm.
Maximum AC performance is achieved if the thermal pad is
attached to a dedicated de-coupled layer in a multi-layered PC
board. In cases where a dedicated layer is not possible, AC
performance may be reduced at upper frequencies.
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible a 1” x 1” pad area is sufficient for
the EL4342 that is dissipating 0.5W in +50°C ambient. Pad area
requirements should be evaluated on a case by case basis.
• The use of low inductance components such as chip resistors
and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners, use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
FN7421 Rev.4.00
Oct 4, 2017
Page 10 of 14
Y1
Y2
31
1
Y3
7
R
12
Pb1
29
Pb2
3
Pb3
G
9
14
Pr1
27
Pr2
5
Pr3
10
B
16
R1
75
R3
75
R2
75
R5
75
R4
75
R7
75
R9
75
R6
75
V+
IN2A
IN3A
23
1nF
1nF
21
VOUTA
22
OUTB
20
IN1B
GNDA
32
IN2B
GNDB
6
IN3B
GNDC
11
NIC
2
NIC
NIC
4
8
NIC
13
NIC
15
NIC
24
NIC
28
NIC
30
HIZ
26
ENABLE
25
S0
18
INOC
IN1C
IN2C
IN3C
R12
75
QFN
R16
500
S1 17
5V 0.1µF
ISL84517IH-T
H SYNC
1
V+
COM
V5V 0.1µF
ISL84517IH-T
V SYNC
1
COM
Page 11 of 14
SOT-23
IN
4
V+
0.1µF
-5V
SOT-23
IN
4
5
1nF
1nF
NC
5
1nF
0.1µF
-5V
1nF
3
2
5V
0.1µF
NC7ST00P5X
V- 3
5V 5
NC 2
1
INPUT
4
OUT
3
GND
-5V
OUTC 19
INOB
R11
75
R10
75
R8
75
EL4342IL
INOA
IN1A
0.1µF 0.1µF
EL4340, EL4342
FN7421 Rev.4.00
Oct 4, 2017
5V
OPTIONAL SCHOTTKY PROTECTION
1nF
INPUT 2
SC70
LOGIC INPUTS
FIGURE 24. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL
R18
500
R17
500
EL4340, EL4342
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
Oct 4, 2017
FN7421.4
CHANGE
Applied new header/footer and formatting.
Updated Related Literature section
Moved Pin descriptions after Pin Configurations.
Updated the following specifications in the EC table:
+IS Enabled: changed min spec from 26mA to 21.5mA
-IS Enabled: changed max spec from -24mA to -21mA
+IS Disable Current: changed min spec from 2.3mA to 1.75mA and max spec from 3.3mA to 4.2mA
Input Hi Current (IIH): changed max spec from 320µA to 340µA
Input Bias Currents: changed min spec from -1µA to -0.5µA
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2005-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7421 Rev.4.00
Oct 4, 2017
Page 12 of 14
EL4340, EL4342
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x6A (One of 10 Packages in MDP0046)
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
0.00
0.02
0.05
-
D
PIN #1
I.D. MARK
E
5.00 BSC
-
D2
2.48 REF
-
E
6.00 BSC
-
E2
(N/2)
2X
0.075 C
2X
0.075 C
0.45
b
0.17
-
0.50
0.55
-
0.22
0.27
-
c
0.20 REF
-
e
0.50 BSC
-
N
32 REF
4
ND
7 REF
6
NE
9 REF
5
0.10 M C A B
b
Rev 1 2/09
NOTES:
(N-2)
(N-1)
N
N LEADS
TOP VIEW
3.40 REF
L
L
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
PIN #1 I.D.
2. Tiebar view shown is a non-functional feature.
3
1
2
3
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(E2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
(N/2)
NE 5
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
7
(D2)
BOTTOM VIEW
0.10 C
e
C
(c)
SEATING
PLANE
0.08 C
N LEADS
& EXPOSED PAD
C
2
A
(L)
SEE DETAIL "X"
A1
SIDE VIEW
N LEADS
DETAIL X
For the most recent package outline drawing, see L32.5x6A.
FN7421 Rev.4.00
Oct 4, 2017
Page 13 of 14
EL4340, EL4342
Quarter Size Outline Plastic Packages
Family (QSOP)
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
INCHES
A
D
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
(N/2)+1
N
E
PIN #1
I.D. MARK
E1
1
(N/2)
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
L1
A
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
For the most recent package outline drawing, see MDP0040.
FN7421 Rev.4.00
Oct 4, 2017
Page 14 of 14