DATASHEET
EL5171, EL5371
FN7307
Rev 9.00
August 14, 2015
250MHz Differential Twisted-Pair Drivers
The EL5171 and EL5371 are single and triple bandwidth
amplifiers with an output in differential form. They are primarily
targeted for applications such as driving twisted-pair lines in
component video applications. The input signal is single-ended
and the outputs are always differential.
Features
On the EL5171 and EL5371, two feedback inputs provide the
user with the ability to set the gain of each device (stable at
minimum gain of one). For a fixed gain of two, please see
EL5170 and EL5370.
• 800V/µs slew rate
The output common mode level for each channel is set by the
associated VREF pin, which have a -3dB bandwidth of over
50MHz. Generally, these pins are grounded but can be tied to
any voltage reference.
• 90mA maximum output current
All outputs are short circuit protected to withstand temporary
overload condition.
The EL5171 and EL5371 are specified for operation over the
full -40°C to +85°C temperature range.
• Fully differential outputs and feedback
• Input range ±2.3V typ.
• 250MHz 3dB bandwidth
• Low distortion at 5MHz
• Single 5V or dual ±5V supplies
• Low power - 8mA per channel
• Pb-free available (RoHS compliant)
Applications
• Twisted-pair driver
• Differential line driver
• VGA over twisted-pair
• ADSL/HDSL driver
• Single-ended to differential amplification
• Transmission of analog signals in a noisy environment
Pinouts
EL5371
(28 LD QSOP)
TOP VIEW
EL5171
(8 LD SOIC)
TOP VIEW
FBP 1
IN+ 2
REF 3
FBN 4
8 OUT+
+
-
NC 1
7 VS-
INP1 2
6 VS+
INN1 3
5 OUT-
REF1 4
+
-
27 FBP1
26 FBN1
25 OUT1B
NC 5
24 VSP
INP2 6
23 VSN
INN2 7
22 OUT2
REF2 8
NC 9
+
-
21 FBP2
20 FBN2
INP3 10
19 OUT2B
INN3 11
18 OUT3
REF3 12
NC 13
EN 14
FN7307 Rev 9.00
August 14, 2015
28 OUT1
+
-
17 FBP3
16 FBN3
15 OUT3B
Page 1 of 15
EL5171, EL5371
Pin Descriptions
EL5171
EL5371
PIN NAME
PIN FUNCTION
1
FBP
Feedback from non-inverting output
2
IN+
Non-inverting input
3
REF
Reference input, sets common-mode output voltage
4
FBN
Feedback from inverting output
5
OUT-
Inverting output
6
VS+
Positive supply
7
VS-
Negative supply
8
OUT+
Non-inverting output
17, 21, 27
FBP3, FBP2, FBP1
Feedback from non-inverting output
2, 6, 10
INP1, INP2, INP3
Non-inverting inputs
4, 8, 12
REF1, REF2, REF3
Reference input, sets common-mode output voltage
3, 7, 11
INN1, INN2, INN3
Inverting inputs, note that on EL5171, this pin is also the REF pin
16, 20, 26
FBN3, FBN2, FBN1
Feedback from inverting output
15, 19, 25
OUT3B, OUT2B, OUT1B
24
VSP
Positive supply
23
VSN
Negative supply
18, 22, 28
OUT3, OUT2, OUT1
1, 5, 9, 13
NC
No connects, grounded for best crosstalk performance
14
EN
ENABLE
Inverting outputs
Non-inverting outputs
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
EL5171ISZ
5171ISZ
8 Ld SOIC
M8.15E
EL5371IUZ (No longer available,
recommended replacement: EL5373IUZ)
EL5371IUZ
28 Ld QSOP
M28.15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5171, EL5371. For more information on MSL please see tech brief
TB363.
FN7307 Rev 9.00
August 14, 2015
Page 2 of 15
EL5171, EL5371
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Input Voltage (IN+, IN- to VS+, VS-) . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V
Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
Specified.
PARAMETER
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise
DESCRIPTION
CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNIT
AC PERFORMANCE
BW
BW
SR
-3dB Bandwidth
±0.1dB Bandwidth
AV = 1, CLD = 2.7pF
250
MHz
AV = 2, RF = 500, CLD = 2.7pF
60
MHz
AV = 10, RF = 500, CLD = 2.7pF
10
MHz
AV = 1, CLD = 2.7pF
50
MHz
Slew Rate (EL5171)
VOUT = 3VP-P, 20% to 80%
600
800
1000
V/µs
Slew Rate (EL5371)
VOUT = 3VP-P, 20% to 80%
540
700
1000
V/µs
tSTL
Settling Time to 0.1%
VOUT = 2VP-P
tOVR
10
ns
Output Overdrive Recovery Time
20
ns
GBWP
Gain Bandwidth Product
100
MHz
VREFBW (-3dB)
VREF -3dB Bandwidth
AV =1, CLD = 2.7pF
50
MHz
VREFSR+
VREF Slew Rate - Rise
VOUT = 2VP-P, 20% to 80%
90
V/µs
VREFSR-
VREF Slew Rate - Fall
VOUT = 2VP-P, 20% to 80%
50
V/µs
VN
Input Voltage Noise
at 10kHz
26
nV/Hz
IN
Input Current Noise
at 10kHz
2
pA/Hz
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 5MHz
-94
dBc
VOUT = 2VP-P, 20MHz
-94
dBc
VOUT = 2VP-P, 5MHz
-77
dBc
VOUT = 2VP-P, 20MHz
-75
dBc
HD3
Third Harmonic Distortion
dG
Differential Gain at 3.58MHz
RL = 300, AV = 2
0.1
%
d
Differential Phase at 3.58MHz
RL = 300, AV = 2
0.5
°
eS
Channel Separation
at f = 1MHz
90
dB
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN+, VIN-)
IREF
Input Bias Current (VREF)
RIN
Differential Input Resistance
CIN
Differential Input Capacitance
DMIR
Differential Mode Input Range
CMIR+
Common Mode Positive Input Range at VIN+, VIN-
FN7307 Rev 9.00
August 14, 2015
Tested only for EL5371
±1.5
±25
mV
-14
-6
-3
µA
0.5
1.3
4
µA
300
k
1
pF
±2.1
±2.3
3.1
3.4
±2.5
V
V
Page 3 of 15
EL5171, EL5371
Electrical Specifications
Specified. (Continued)
PARAMETER
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise
DESCRIPTION
CONDITIONS
CMIR-
Common Mode Negative Input Range at VIN+, VIN-
Tested only for EL5371
VREFIN +
Positive Reference Input Voltage Range (EL5371)
VIN+ = VIN- = 0V
VREFIN -
Negative Reference Input Voltage Range (EL5371)
VIN+ = VIN- = 0V
VREFOS
Output Offset Relative to VREF (EL5371)
CMRR
Input Common Mode Rejection Ratio (EL5371)
VIN = ±2.5V
Gain
Gain Accuracy
MIN
(Note 4)
3.5
TYP
MAX
(Note 4)
UNIT
-4.5
-4.2
V
±3.8
V
-3.3
-3
V
±60
±100
mV
70
82
dB
VIN = 1 (EL5171)
0.981
0.996
1.011
V
VIN = 1 (EL5371)
0.978
0.993
1.008
V
OUTPUT CHARACTERISTICS
VOUT
IOUT(Max)
ROUT
Output Voltage Swing
Maximum Output Current
RL = 500 to GND (EL5171)
±3.4
V
V
RL = 500 to GND (EL5371)
±3.6
±3.9
RL = 10, VIN = ±3.24 (EL5171)
±70
±90
±120
mA
RL = 10, VIN = ±3.24 (EL5371)
±50
±70
±90
mA
Output Impedance
130
m
SUPPLY
VSUPPLY
Supply Operating Range
IS(ON)
Power Supply Current - Per Channel
IS(OFF)+
Positive Power Supply Current - Disabled (EL5371)
IS(OFF)-
Negative Power Supply Current - Disabled (EL5371)
PSRR
Power Supply Rejection Ratio
VS+ to VS-
4.75
11
V
mA
6.8
7.5
8.2
1.7
10
-200
-120
µA
VS from ±4.5V to ±5.5V (EL5171)
70
84
dB
VS from ±4.5V to ±5.5V (EL5371)
65
83
dB
EN pin tied to 4.8V
µA
ENABLE (EL5371 ONLY)
tEN
Enable Time
215
ns
tDS
Disable Time
0.95
µs
VIH
EN Pin Voltage for Power-Up
VIL
EN Pin Voltage for Shutdown
IIH-EN
EN Pin Input Current High
At VEN = 5V
IIL-EN
EN Pin Input Current Low
At VEN = 0V
VS+ -1.5
V
130
µA
VS+ -0.5
V
122
-10
-8
µA
NOTE:
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7307 Rev 9.00
August 14, 2015
Page 4 of 15
RF1
CL1
5pF
-5V
INP
RG
REF
RS1
50
RS1
50
1 FBP
OUT 8
2 INP
VSN 7
3 REF
VSP 6
4 FBN
OUTB 5
RF3
EL5171, EL5371
FN7307 Rev 9.00
August 14, 2015
Connection Diagrams
OUT
RLD
1k
OUTB
+5V
CL2
5pF
FIGURE 1. EL5171
+5V
INP1
INN1
REF1
INP2
INN2
REF2
INP3
INN3
REF3
Page 5 of 15
RSP1
50
RSN1
50
RSR1
50
RSP2
50
RSN2
50
RSR2
50
RSP3
50
RSN3
50
RSR3
50
1 NC
OUT1 28
2 INP1
FBP1 27
3 INN1
FBN1 26
4 REF1
OUT1B 25
5 NC
VSP 24
6 INP2
VSN 23
7 INN2
OUT2 22
8 REF2
FBP2 21
9 NC
FBN2 20
10 INP3
OUT2B 19
11 INN3
OUT3 18
12 REF3
FBP3 17
13 NC
FBn3 16
14 EN
OUT3B 15
RF
RG
RF
RG
FIGURE 2. EL5371
RLD2
1k
RF
RF
RG
-5V
ENABLE
RLD1
1k
RF
RLD3
1k
RF
CL1
5pF
CL1B
5pF
CL2
5pF
CL2B
5pF
CL3
5pF
CL3B
5pF
EL5171, EL5371
Typical Performance Curves
RLD = 1k, CLD = 2.7pF
AV = 1, RLD = 1k, CLD = 2.7pF
4
4
NORMALIZED MAGNITUDE (dB)
3
MAGNITUDE (dB)
2
1
0
VOP-P = 200mV
-1
-2
-3
VOP-P = 1VP-P
-4
-5
-6
1M
10M
100M
3
2
1
0
-1
AV = 1
-2
AV = 5
-3
-4
AV = 10
-5
-6
1M
1G
FREQUENCY (Hz)
1G
AV = 1, RLD = 1k
5
3
4
2
3
1
RLD = 1k
0
RLD = 500
-1
-2
RLD = 200
MAGNITUDE (dB)
NORMALIZED GAIN (dB)
AV = 1, CLD = 2.7pF
CLD = 56pF
CLD = 34pF
2
CLD = 23pF
1
0
-1
CLD = 9pF
-2
CLD = 2.7pF
-3
-5
-4
-6
1M
10M
100M
-5
1M
1G
FREQUENCY (Hz)
10
9
9
NORMALIZED GAIN (dB)
8
RF = 1k
RF = 500
5
4
3
RF = 200
2
1G
AV = 2, RF = 1k, CLD = 2.7pF
AV = 2, RLD = 1k, CLD = 2.7pF
6
100M
FIGURE 6. FREQUENCY RESPONSE vs CLD
10
7
10M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE vs RLD
NORMALIZED GAIN (dB)
100M
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS GAIN
4
-4
10M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE
-3
AV = 2
1
8
7
6
RLD = 1k
5
4
RLD = 500
3
2
RLD = 200
1
0
1M
10M
100M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE
FN7307 Rev 9.00
August 14, 2015
400M
0
1M
10M
100M
400M
FREQUENCY (Hz)
FIGURE 8. FREQUENCY RESPONSE vs RLD
Page 6 of 15
EL5171, EL5371
Typical Performance Curves
(Continued)
5
100
4
2
IMPEDANCE ()
MAGNITUDE (dB)
3
1
0
-1
-2
10
1
-3
-4
-5
100k
1M
10M
0.1
10k
100M
100k
FREQUENCY (Hz)
0
100
-10
90
-20
80
100M
70
-30
-40
PSRR-
-50
PSRR+
-60
60
50
40
30
-70
20
-80
10
100k
10k
1M
10M
0
100k
100M
1M
FREQUENCY (Hz)
10M
100M
1G
FREQUENCY (Hz)
FIGURE 11. PSRR vs FREQUENCY
FIGURE 12. CMRR vs FREQUENCY
-30
1k
-40
-50
100
GAIN (dB)
VOLTAGE NOISE (nV/Hz),
CURRENT NOISE (pA/Hz)
10M
FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY
CMRR (dB)
PSRR (dB)
FIGURE 9. FREQUENCY RESPONSE - VREF
-90
1k
1M
FREQUENCY (Hz)
EN
10
CH1 CH2, CH2 CH3
-70
-80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 13. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FN7307 Rev 9.00
August 14, 2015
CH1 CH3
-90
IN
1
10
-60
-100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 14. CHANNEL ISOLATION vs FREQUENCY
Page 7 of 15
EL5171, EL5371
Typical Performance Curves
(Continued)
VS = ±5V, AV = 1, RLD = 1k
VS = ±5V, AV = 1, RLD = 1k
-50
-50
-55
-55
-60
DISTORTION (dB)
DISTORTION (dB)
-60
-65
-70
HD3 (f = 20MHz)
-75
HD3 (f = 5MHz)
-80
-85
= 20M
HD2 (f
-90
H z)
(f
HD2
-95
-100
1.0
1.5
2.0
2.5
3.0
4.0
HD3 (f = 20MH
-70
-80
HD2 (f = 5M
-95
1
5.0
Hz)
HD2 (f = 20MHz)
-90
4.5
2
3
4
VOP-P, DM (V)
5
6
7
8
10
9
VOP-P, DM (V)
FIGURE 15. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE
FIGURE 16. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT
VOLTAGE
VS = ±5V, AV = 2, VOP-P, DM = 2V
VS = ±5V, AV = 1, VOP-P, DM = 1V
-40
-50
-55
HD
3
-65
-70
-75
(f
HD
3
=
HD
-80
-85
20
M
2 (f
HD2
(f =
-90
(f
=
5M
Hz
)
=2
0M
HD3 (f = 20MHz)
-50
Hz
DISTORTION (dB)
-60
DISTORTION (dB)
z)
-75
-85
H z)
= 5M
3.5
HD3 (f = 5MHz)
-65
Hz
)
)
5MH
z)
HD3 (f = 5MHz)
-60
-70
HD2 (f
-80
-90
= 20MH
z)
HD2 (f = 5MHz)
-95
-100
100
200
300
400
600
500
700
800
900 1000
-100
200
FIGURE 17. HARMONIC DISTORTION vs RLD
500
600
700
800
900
1000
FIGURE 18. HARMONIC DISTORTION vs RLD
VS = ±5V, RLD = 1k, VOP-P, DM = 1V for AV = 1,
VOP-P, DM = 2V for AV = 2
HD3 (AV = 1)
-50
DISTORTION (dB)
400
RLD ()
RLD ()
-40
300
-60
3
HD
-70
(A V
=2
)
2)
HD2 (AV =
HD2 (AV
50mV/DIV
= 1)
-80
-90
-100
0
10
20
30
40
50
60
10ns/DIV
FREQUENCY (MHz)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
FN7307 Rev 9.00
August 14, 2015
FIGURE 20. SMALL SIGNAL TRANSIENT RESPONSE
Page 8 of 15
EL5171, EL5371
Typical Performance Curves
(Continued)
M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
0.5V/DIV
CH2
100ns/DIV
10ns/DIV
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 22. ENABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
POWER DISSIPATION (W)
1.2
CH1
CH2
1.010W
1.0
QSOP28
JA =+99°C/W
0.8
625mW
0.6
0.4
SO8
JA = +160°C/W
0.2
0
200ns/DIV
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 23. DISABLED RESPONSE
POWER DISSIPATION (W)
1.4
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.266W
1.0
909mW
QSOP28
JA = +79°C/W
0.8
0.6
SO8
JA = +110°C/W
0.4
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7307 Rev 9.00
August 14, 2015
Page 9 of 15
EL5171, EL5371
Simplified Schematic
VS+
R1
IN+
IN-
R3
R2
FBP
R4
R7
R8
FBN
VB1
OUT+
RCD
REF
RCD
VB2
CC
OUT-
R9
R10
CC
R5
R6
VS-
Description of Operation and
Application Information
Product Description
The EL5171 and EL5371 are wide bandwidth, low power and
single-ended to differential output amplifiers. The EL5171 is a
single channel differential amplifier. Since the IN- pin and REF
pin are tied together internally, the EL5171 can be used as a
single-ended to differential converter. The EL5371 is a triple
channel differential amplifier. The EL5371 has a separate INpin and REF pin for each channel. It can be used as a
single/differential ended to differential converter. The EL5171
and EL5371 are internally compensated for closed loop gain of
+1 or greater. Connected in gain of 1 and driving a 1k
differential load, the EL5171 and EL5371 have a -3dB
bandwidth of 250MHz. Driving a 200 differential load at gain
of 2, the bandwidth is about 30MHz. The EL5371 is available
with a power-down feature to reduce the power while the
amplifier is disabled.
Input, Output, and Supply Voltage Range
The EL5171 and EL5371 have been designed to operate with a
single supply voltage of 5V to 10V or split supplies with its total
voltage from 5V to 10V. The amplifiers have an input common
mode voltage range from -4.5V to 3.4V for ±5V supply. The
differential mode input range (DMIR) between the two inputs is
from -2.3V to +2.3V. The input voltage range at the REF pin is
from -3.3V to 3.8V. If the input common mode or differential
mode signal is outside the above-specified ranges, it will cause
the output signal to become distorted.
The output of the EL5171 and EL5371 can swing from -3.9V to
+3.9V at 1k differential load at ±5V supply. As the load
resistance becomes lower, the output swing is reduced.
Differential and Common Mode Gain
Settings
For EL5171, since the IN- pin and REF pin are bound together as
the REF pin in an 8 Ld package, the signal at the REF pin is part of
FN7307 Rev 9.00
August 14, 2015
the common mode signal and also part of the differential mode
signal. For the true balance differential outputs, the REF pin must
be tied to the same bias level as the IN+ pin. For a ±5V supply, just
tie the REF pin to GND if the IN+ pin is biased at 0V with a 50 or
75 termination resistor. For a single supply application, if the
IN+ is biased to half of the rail, the REF pin should be biased to
half of the rail also.
The gain setting for EL5171 is expressed in Equation 1:
R F1 + R F2
V ODM = V IN + 1 + ----------------------------
RG
2R F
V ODM = V IN + 1 + -----------
RG
(EQ. 1)
V OCM = V REF = 0V
Where:
• VREF = 0V
• RF1 = RF2 = RF
The EL5371 has a separate IN- pin and REF pin. It can be used
as a single/differential ended to differential converter. The
voltage applied at REF pin can set the output common mode
voltage and the gain is one.
The gain setting for EL5371 is expressed in Equation 2:
2R F
V ODM = V IN + – V IN - 1 + -----------
RG
(EQ. 2)
V OCM = V REF
R F1 + R F2
V ODM = V IN + – V IN - 1 + ----------------------------
RG
Where:
• RF1 = RF2 = RF
Page 10 of 15
EL5171, EL5371
resistor. Again, a small series resistor at the output can help to
reduce peaking.
RF1
Disable/Power-Down (for EL5371 only)
FBP
VIN+
VINVREF
The EL5371 can be disabled and its outputs placed in a high
impedance state. The turn-off time is about 0.95µs and the
turn-on time is about 215ns. When disabled, the amplifier's
supply current is reduced to 1.7µA for IS+ and 120µA for IStypically, thereby effectively eliminating the power
consumption. The amplifier's power-down can be controlled by
standard CMOS signal levels at the ENABLE pin. The applied
logic signal is relative to the VS+ pin. Letting the EN pin float or
applying a signal that is less than 1.5V below VS+ will enable
the amplifier. The amplifier will be disabled when the signal at
the EN pin is above VS+ - 0.5V.
V O+
IN+
RG
INREF
V O-
FBN
RF2
FIGURE 26.
Choice of Feedback Resistor and Gain
Bandwidth Product
For applications that require a gain of +1, no feedback resistor
is required. Just short the OUT+ pin to the FBP pin and the OUTpin to the FBN pin. For gains greater than +1, the feedback
resistor forms a pole with the parasitic capacitance at the
inverting input. As this pole becomes smaller, the amplifier's
phase margin is reduced. This causes ringing in the time
domain and peaking in the frequency domain. Therefore, RF has
some maximum value that should not be exceeded for optimum
performance. If a large value of RF must be used, a small
capacitor in the few Pico farad range in parallel with RF can help
to reduce the ringing and peaking at the expense of reducing
the bandwidth.
The bandwidth of the EL5171 and EL5371 depends on the load
and the feedback network. RF and RG appear in parallel with
the load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, RF also has a
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, RF = 0 is optimum. For
the gains other than +1, optimum response is obtained with RF
between 500 to 1k.
The EL5171 and EL5371 have a gain bandwidth product of
100MHz for RLD = 1k. For gains 5, their bandwidth can be
predicted by Equation 3:
Gain BW = 100MHz
(EQ. 3)
Driving Capacitive Loads and Cables
The EL5171 and EL5371 can drive 50pF differential capacitor
in parallel with 1k differential load with less than 5dB of
peaking at gain of +1. If less peaking is desired in applications,
a small series resistor (usually between 5 to 50) can be
placed in series with each output to eliminate most peaking.
However, this will reduce the gain slightly. If the gain setting is
greater than 1, the gain resistor RG can then be chosen to
make up for any gain loss, which may be created by the
additional series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
Output Drive Capability
The EL5171 and EL5371 have internal short circuit protection.
Its typical short circuit current is ±90mA for EL5171 and ±70mA
for EL5371. If the output is shorted indefinitely, the power
dissipation could easily increase such that the part will be
destroyed. Maximum reliability is maintained if the output
current never exceeds ±60mA. This limit is set by the design of
the internal metal interconnections.
Power Dissipation
With the high output drive capability of the EL5171 and EL5371,
it is possible to exceed the +135°C absolute maximum junction
temperature under certain load current conditions. Therefore, it
is important to calculate the maximum junction temperature for
the application to determine if the load conditions or package
types need to be modified for the amplifier to remain in the safe
operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 4:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
(EQ. 4)
Where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the load, or as
represented in Equation 5:
V O
PD = i V STOT I SMAX + V STOT – V O ------------
R LD
(EQ. 5)
Where:
VSTOT = Total supply voltage = VS+ - VSISMAX = Maximum quiescent supply current per channel
VO = Maximum differential output voltage of the
application
RLD = Differential load resistance
FN7307 Rev 9.00
August 14, 2015
Page 11 of 15
EL5171, EL5371
ILOAD = Load current
i = Number of channels
By setting the two PDMAX equations equal to each other, we can
solve the output current and RLOAD to avoid the device overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit board
layout is necessary for optimum performance. Lead lengths
should be as sort as possible. The power supply pin must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to the ground
plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF
ceramic capacitor from VS+ to GND will suffice. This same
capacitor combination should be placed at each supply pin to
ground if split supplies are to be used. In this case, the VS- pin
becomes the negative supply rail.
For good AC performance, parasitic capacitance should be kept
to a minimum. Use of wire wound resistors should be avoided
because of their additional series inductance. Use of sockets
should also be avoided, if possible. Sockets add parasitic
inductance and capacitance that can result in compromised
performance. Minimizing parasitic capacitance at the amplifier's
inverting input pin is very important. The feedback resistor
should be placed very close to the inverting input pin. Strip line
design techniques are recommended for the signal traces.
As the signal is transmitted through a cable, the high frequency
signal will be attenuated. One way to compensate this loss is to
boost the high frequency gain at the receiver side.
Typical Applications
RF
FBP
50
TWISTED PAIR
IN+
IN+
RT
RG
INREF
EL5171/
EL5371
50
IN-
ZO = 100
FBN
EL5172/
EL5372
VO
REF
RF
RFR
RGR
FIGURE 27. TWISTED PAIR CABLE RECEIVER
RF
GAIN
(dB)
FBP
RT
75
RGC
RG
CL
VO+
IN+
INREF
VO-
FBN
fL
RF
2R F
DC Gain = 1 + ----------RG
1
f L ------------------------2R G C C
2R F
HF Gain = 1 + -------------------------R G R GC
1
f H ----------------------------2R GC C C
fH
FREQUENCY
FIGURE 28. TRANSMIT EQUALIZER
FN7307 Rev 9.00
August 14, 2015
Page 12 of 15
EL5171, EL5371
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
August 14, 2015
FN7307.9
CHANGE
Updated the Ordering Information table on page 2.
Added Revision History and About Intersil Sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN7307 Rev 9.00
August 14, 2015
Page 13 of 15
EL5171, EL5371
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN7307 Rev 9.00
August 14, 2015
Page 14 of 15
EL5171, EL5371
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
INDEX
AREA
H
0.25(0.010) M
E
2
SYMBOL
3
0.25
0.010
SEATING PLANE
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
A
D
h x 45°
-C-
e
0.17(0.007) M
A2
A1
B
L
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.386
0.394
9.81
10.00
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
28
0°
28
8°
0°
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
7
8°
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
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All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7307 Rev 9.00
August 14, 2015
Page 15 of 15
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