DATASHEET
EL8302
FN7348
Rev 2.00
May 6, 2005
500MHz Rail-to-Rail Amplifier
The EL8302 represents a triple rail-to-rail amplifier with a 3dB bandwidth of 500MHz and slew rate of 600V/µs.
Running off a very low supply current of 5.6mA per channel,
the EL8302 also features inputs that go to 0.15V below the
VS- rail.
The EL8302 includes a fast-acting disable/power-down
circuit. With a 25ns disable and a 200ns enable, the EL8302
is ideal for multiplexing applications.
The EL8302 is designed for a number of general purpose
video, communication, instrumentation, and industrial
applications. The EL8302 is available in an 16-pin SO and
16-pin QSOP packages and is specified for operation over
the -40°C to +85°C temperature range.
Features
• 500MHz -3dB bandwidth
• 600V/µs slew rate
• Low supply current = 5.6mA per amplifier
• Supplies from 3V to 5.5V
• Rail-to-rail output
• Input to 0.15V below VS• Fast 25ns disable
• Low cost
• Pb-Free available (RoHS compliant)
Applications
Pinout
EL8302
(16-PIN SO, QSOP)
TOP VIEW
INA+ 1
CEA 2
16 INA+
VS- 3
CEB 4
14 VS+
+
-
INB+ 5
NC 6
CEC 7
INC+ 8
15 OUTA
+
-
13 OUTB
• Video amplifiers
• Portable/hand-held products
• Communications devices
Ordering Information
PART
NUMBER
PACKAGE
TAPE & REEL PKG. DWG. #
EL8302IS
16-Pin SO
-
MDP0027
12 INB-
EL8302IS-T7
16-Pin SO
7”
MDP0027
11 NC
EL8302IS-T13
16-Pin SO
13”
MDP0027
10 OUTC
EL8302ISZ
(See Note)
16-Pin SO
(Pb-free)
-
MDP0027
EL8302ISZ-T7
(See Note)
16-Pin SO
(Pb-free)
7”
MDP0027
EL8302ISZ-T13
(See Note)
16-Pin SO
(Pb-free)
13”
MDP0027
EL8302IU
16-Pin QSOP
-
MDP0040
EL8302IU-T7
16-Pin QSOP
7”
MDP0040
EL8302IU-T13
16-Pin QSOP
13”
MDP0040
EL8302IUZ
(See Note)
16-Pin QSOP
(Pb-free)
-
MDP0040
EL8302IUZ-T7
(See Note)
16-Pin QSOP
(Pb-free)
7”
MDP0040
EL8302IUZ-T13
(See Note)
16-Pin QSOP
(Pb-free)
13”
MDP0040
9 INC-
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7348 Rev 2.00
May 6, 2005
Page 1 of 14
EL8302
Absolute Maximum Ratings (TA = 25°C)
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ + 0.3V to VS- -0.3V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
-7
-0.8
+7
mV
INPUT CHARACTERISTICS
VOS
Offset Voltage
TCVOS
Offset Voltage Temperature Coefficient Measured from TMIN to TMAX
IB
Input Bias Current
VIN = 0V
IOS
Input Offset Current
VIN = 0V
TCIOS
Input Bias Current Temperature
Coefficient
Measured from TMIN to TMAX
CMRR
Common Mode Rejection Ratio
VCM = -0.15V to +3.5V
CMIR
Common Mode Input Range
RIN
Input Resistance
CIN
Input Capacitance
AVOL
Open Loop Gain
-10
3
µV/°C
-6
µA
0.1
70
µA
2
nA/°C
95
dB
VS- -0.15
Common Mode
0.6
VS+ - 1.5
V
7
M
0.5
pF
100
dB
VOUT = +1.5V to +3.5V, RL = 150 to
GND
80
dB
30
m
VOUT = +1.5V to +3.5V, RL = 1k to GND
75
OUTPUT CHARACTERISTICS
ROUT
Output Resistance
AV = +1
VOP
Positive Output Voltage Swing
RL = 1k
4.85
4.9
V
RL = 150
4.65
4.7
V
VON
Negative Output Voltage Swing
RL = 150
150
200
mV
RL = 1k
50
70
mV
IOUT
Linear Output Current
ISC (source)
Short Circuit Current
RL = 10
ISC (sink)
Short Circuit Current
65
mA
50
80
mA
RL = 10
90
150
mA
VS+ = 4.5V to 5.5V
70
95
dB
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
IS-ON
Supply Current - Enabled per Amplifier
5.6
6.2
mA
IS-OFF
Supply Current - Disabled per Amplifier
40
90
µA
tEN
Enable Time
200
ns
tDS
Disable Time
25
ns
VIH-ENB
ENABLE Pin Voltage for Power-up
0.8
V
VIL-ENB
ENABLE Pin Voltage for Shut-down
2
V
ENABLE
FN7348 Rev 2.00
May 6, 2005
Page 2 of 14
EL8302
Electrical Specifications
PARAMETER
VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
IIH-ENB
ENABLE Pin Input Current High
8.6
µA
IIL-ENB
ENABLE Pin Input for Current Low
0.01
µA
AV = +1, RF = 0, CL = 1.5pF
500
MHz
AV = -1, RF = 1k, CL = 1.5pF
140
MHz
AV = +2, RF = 1k, CL = 1.5pF
165
MHz
AV = +10, RF = 1k, CL = 1.5pF
18
MHz
AC PERFORMANCE
BW
-3dB Bandwidth
BW
±0.1dB Bandwidth
AV = +1, RF = 0, CL = 1.5pF
36
MHz
Peak
Peaking
AV = +1, RL = 1k, CL = 1.5pF
1
dB
GBWP
Gain Bandwidth Product
200
MHz
PM
Phase Margin
RL = 1k, CL = 1.5pF
55
°
SR
Slew Rate
AV = 2, RL = 100, VOUT = 0.5V to 4.5V
600
V/µs
tR
Rise Time
2.5VSTEP, 20% - 80%
4
ns
tF
Fall Time
2.5VSTEP, 20% - 80%
2
ns
OS
Overshoot
200mV step
10
%
tPD
Propagation Delay
200mV step
1
ns
tS
0.1% Settling Time
200mV step
15
ns
dG
Differential Gain
AV = +2, RF = 1k, RL = 150
0.01
%
dP
Differential Phase
AV = +2, RF = 1k, RL = 150
0.01
°
eN
Input Noise Voltage
f = 10kHz
12
nV/Hz
iN+
Positive Input Noise Current
f = 10kHz
1.7
pA/Hz
iN-
Negative Input Noise Current
f = 10kHz
1.3
pA/Hz
eS
Channel Separation
f = 100kHz
95
dB
500
Pin Descriptions
PIN
NAME
1, 5, 8
INA+, INB+, INC+
Non-inverting input for each channel
2, 4, 7
CEA, CEB, CEC
Enable and disable input for each channel
3
VS-
Negative power supply
6, 11
NC
Not connected
9, 12, 16
INC-, INB-, INA-
10, 13, 15
OUTC, OUTB, OUTA
14
VS+
FN7348 Rev 2.00
May 6, 2005
FUNCTION
Inverting input for each channel
Amplifier output for each channel
Positive power supply
Page 3 of 14
EL8302
Typical Performance Curves
3
2
GAIN (dB)
5
VS=5V
AV=1
RL=1k
CL=1.5pF
NORMALIZED GAIN (dB)
5
4
VOP-P=200mV
1
0
-1
VOP-P=1V
-2
-3
VOP-P=2V
-4
-5
1M
10M
RF=RG=1k
-1
-3
RF=RG=500
VS=5V
AV=2
RL=1k
CL=1.5pF
1M
FREQUENCY (Hz)
5
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
2
AV=2
1
AV=1
0
-1
AV=5
-2
-3
AV=10
-4
-5
1M
10M
100M
2
VS=5V
CL=1.5pF
RL=1k
RF=1k
AV=-1
AV=-5
-2
-4
AV=-10
-6
100K
1G
1M
GAIN (dB)
9
RL=100
RL=1k
GAIN (dB)
3
2
1
0
-1
RL=500
7
5
RL=1k,
150
3
-3
-4
RL=500
10M
100M
1G
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RLOAD
FN7348 Rev 2.00
May 6, 2005
1G
VS=5V
AV=2
CL=1.5pF
RF=RG=1k
-2
-5
1M
100M
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS INVERTING GAINS
11
VS=5V
AV=1
CL=1.5pF
VOP-P=200mV
10M
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS NON-INVERTING GAINS
5
1G
0
FREQUENCY (Hz)
4
100M
FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE
vs RF AND RG
4
VS=5V
CL=1.5pF
RL=1k
3
10M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGE LEVELS
4
RF=RG=2k
1
-5
100K
1G
100M
3
1
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs
VARIOUS RLOAD
Page 4 of 14
EL8302
Typical Performance Curves (Continued)
16
VS=5V
AV=1
RL=1k
VOP-P=200mV
4
3
GAIN (dB)
2
12
CL=3.7pF
10
1
0
-1
CL=1.5pF
-2
4
CL=10pF
2
-3
-2
100M
CL=1.5pF
-4
1M
1G
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs CL
70 R =150
L
315
-30
30
225
RL=150
-10
135
RL=1k
-90
1K
GAIN (dB)
-10
RL=1k
PHASE (°)
GAIN (dB)
FIGURE 8. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
405
-50
100K
1M
10M
100M
VS=5V
AV=1
RL=1k
-50
-70
-90
45
10K
1G
100M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
110
CL=13.5pF
6
-4
10M
CL=28.5pF
CL=20pF
8
0
-5
1M
VS=5V
AV=2
RL=1k
RF=RG=1k
14
CL=4.8pF
GAIN (dB)
5
-110
1K
-45
1G
10K
1M
100K
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 10. DISABLED OUTPUT ISOLATION FREQUENCY
RESPONSE
-10
550
-30
450
BANDWIDTH (MHz)
PSRR (dB)
500
PSRR-
-50
-70
PSRR+
-90
RL=1k
CL=1.5pF
400
AV=1
350
300
250
200
AV=2
150
-110
1K
100
10K
100K
1M
FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION
RATIO vs FREQUENCY
FN7348 Rev 2.00
May 6, 2005
10M
100M
3
3.5
4.5
4
5
5.5
VS (V)
FIGURE 12. SMALL SIGNAL BANDWIDTH vs
SUPPLY VOLTAGE
Page 5 of 14
EL8302
Typical Performance Curves (Continued)
2.5
100
RL=1k
CL=1.5pF
PEAKING (dB)
IMPEDANCE ()
2
10
1
0.1
AV=1
1.5
1
0.5
0
0.01
10K
100K
1M
10M
100M
AV=2
3
4
3.5
4.5
10
-35
8
-55
6
IS (mA)
CMRR (dB)
-15
-75
4
2
-95
-115
100K
1M
10M
0
100M
0.5
0
1
1.5
2
2.5
3
3.5
4.5
4
5
5.5
VS (V)
FREQUENCY (Hz)
FIGURE 15. COMMON-MODE REJECTION RATIO vs
FREQUENCY
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE (PER
AMPLIFIER)
-70
V
VS
=5V
S=5V
R
=1k
RLL=1k
C
=1.5pF
CLL=1.5p
F
AV=2
-70
-80
HD2
-90
HD2@5MHz
Hz
@ 1M
MHz
HD3@ 5
1
-75
HD2@10MHz
DISTORTION (dBc)
-60
DISTORTION (dBc)
5.5
FIGURE 14. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE
FIGURE 13. OUPUT IMPEDANCE vs FREQUENCY
-100
5
VS (V)
FREQUENCY (Hz)
2
H
HD3@10M
z
3
4
5
VOP-P (V)
FIGURE 17. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FN7348 Rev 2.00
May 6, 2005
-80
H D 2@
AV =2
AV =1
-85
VS=5V
f=5MHz
-90
-95
HD3@1MHz
HD2@
H D 3@
VO=1VP-P for AV=1
VO=2VP-P for AV=2
-100
100
H D 3@
AV =2
AV =1
1K
2K
RLOAD ()
FIGURE 18. HARMONIC DISTORTION vs LOAD RESISTANCE
Page 6 of 14
EL8302
Typical Performance Curves (Continued)
1K
-50
DISTORTION (dBc)
-60
-70
HD2@
-80
-90
-100
AV=2
HD3@AV=2
VOLTAGE NOISE (nV/Hz)
CURRENT NOISE (pA/Hz),
VS=5V
RL=1k
CL=1.5pF
VO=1VP-P for AV=1
VO=2VP-P for AV=2
HD2@AV=1
=1
@A V
HD 3
10
1
100
eN
10
IN+
1
10
40
100
IN-
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (MHz)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
FIGURE 20. VOLTAGE AND CURRENT NOISE vs FREQUENCY
VS=5V, AV=1, RL=1k TO 2.5V, CL=1.5pF
CHANNEL SEPARATION (dB)
0
-10
-20
-30
3.5
-40
-50
2.5
-60
CH2-->CH1
CH2-->CH1
CH2-->CH3
-70
-80
-90
-100
1.00E+05 1.00E+06
1.00E+07
CH3-->CH2
CH1-->CH2
CH1CH3
1.00E+08
1.5
1.00E+09
2ns/DIV
FREQUENCY (Hz)
FIGURE 21. CHANNEL SEPARATION vs FREQUENCY
FIGURE 22. LARGE SIGNAL TRANSIENT
RESPONSE - RISING
VS=5V, AV=1, RL=1k to 2.5V, CL=1.5pF
VS=5V, AV=1, RL=1k TO 2.5V, CL= 1.5pF
2.6
VIN
2.5
3.5
2.4
2.5
2.6
VOUT
2.5
1.5
2.4
2ns/DIV
FIGURE 23. LARGE SIGNAL TRANSIENT
RESPONSE - FALLING
FN7348 Rev 2.00
May 6, 2005
10ns/DIV
FIGURE 24. SMALL SIGNAL TRANSIENT REPONSE
Page 7 of 14
EL8302
Typical Performance Curves (Continued)
VS=5V, AV=5, RL=1k TO 2.5V
VS=5V, AV=5, RL=1k TO 2.5V
5
5
2.5
2.5
0
0
2µs/DIV
2µs/DIV
FIGURE 26. OUTPUT SWING
FIGURE 25. OUTPUT SWING
CH1
ENABLE
INPUT
ENABLE
INPUT
CH1
CH2
CH2
VOUT
VOUT
CH1, CH2, 1V/DIV, M=100ns
CH1, CH2, 0.5V/DIV, M=20ns
FIGURE 28. DISABLED RESPONSE
FIGURE 27. ENABLED RESPONSES
1
0.6
633mW
0.4
J
0.2
0
SO
1
JA 6 ( 0
=1
.
10 150
°C ”)
/W
909mW
0.8
1.4
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
QS
A=
OP
16
15
8°
C/
W
1.2
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7348 Rev 2.00
May 6, 2005
1.250W
SO
JA
=
1
0.8
893mW
0.6
JA =
16
80
°
(0
.
15
0”
)
C/
W
QS
OP
16
2°
C/
W
11
0.4
0.2
0
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Page 8 of 14
EL8302
Simplified Schematic Diagram
VS+
I1
I2
Q5
IN+
Q1
R8
VBIAS1
Q6
R3
R1
R7
R6
Q7
R2
Q2
DIFFERENTIAL TO
SINGLE ENDED
DRIVE
GENERATOR
IN-
VBIAS2
Q3
OUT
Q4
Q8
R4
R5
R9
VS-
Description of Operation and Application
Information
Product Description
The EL8302 is wide bandwidth, single supply, low power and
rail-to-rail output voltage feedback operational amplifiers. The
amplifiers are internally compensated for closed loop gain of
+1 of greater. Connected in voltage follower mode and driving
a 1k load, the EL8302 has a -3dB bandwidth of 500MHz.
Driving a 150 load, the bandwidth is about 350MHz while
maintaining a 600V/us slew rate. The EL8302 is available with
a power down pin for each channel to reduce power to 30µA
typically while the amplifier is disabled.
Input, Output and Supply Voltage Range
The EL8302 has been designed to operate with a single supply
voltage from 3V to 5.0V. Split supplies can also be used as
long as their total voltage is within 3V to 5.0V. The amplifiers
have an input common mode voltage range from 0.15V below
the negative supply (VS- pin) to within 1.5V of the positive
supply (VS+ pin). If the input signal is outside the above
specified range, it will cause the output signal to be distorted.
The output of the EL8302 can swing rail to rail. As the load
resistance becomes lower, the ability to drive close to each rail
is reduced. For the load resistor 1k, the output swing is about
4.9V at a 5V supply. For the load resistor 150, the output
swing is about 4.6V.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback resistor
is required. Just short the output pin to the inverting input pin.
For gains greater than +1, the feedback resistor forms a pole
with the parasitic capacitance at the inverting input. As this
pole becomes smaller, the amplifier’s phase margin is reduced.
This causes ringing in the time domain and peaking in the
FN7348 Rev 2.00
May 6, 2005
frequency domain. Therefore, RF has some maximum value
that should not be exceeded for optimum performance. If a
large value of RF must be used, a small capacitor in the few pF
range in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
As far as the output stage of the amplifier is concerned, the
output stage is also a gain stage with the load. RF and RG
appear in parallel with RL for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, RF also has a minimum value that should not be
exceeded for optimum performance. For gain of +1, RF=0 is
optimum. For the gains other than +1, optimum response is
obtained with RF between 300 to 1k.
The EL8302 has a gain bandwidth product of 200MHz. For
gains 5, its bandwidth can be predicted by the following
equation:
Gain BW = 200MHz
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same frequency
response as DC levels are changed at the output. This is
especially difficult when driving a standard video load of 150,
because the change in output current with DC level. Special
circuitry has been incorporated in the EL8302 to reduce the
variation of the output impedance with the current output. This
results in dG and dP specifications of 0.01% and 0.01, while
driving 150 at a gain of 2. Driving high impedance loads
would give a similar or better dG and dP performance.
Driving Capacitive Loads and Cables
The EL8302 can drive 5pF loads in parallel with 1k with less
than 5dB of peaking at gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5 to
50) can be placed in series with the output to eliminate most
Page 9 of 14
EL8302
peaking. However, this will reduce the gain slightly. If the gain
setting is greater than 1, the gain resistor RG can then be
chosen to make up for any gain loss which may be created by
the additional series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help to
reduce peaking.
Disable/Power-Down
The EL8302 can be disabled and placed its output in a high
impedance state. The turn off time is about 25ns and the turn
on time is about 200ns. When disabled, the amplifier’s supply
current is reduced to 30µA typically, thereby effectively
eliminating the power consumption. The amplifier’s power
down can be controlled by standard TTL or CMOS signal
levels at the ENABLE pin. The applied logic signal is relative to
VS- pin. Letting the ENABLE pin float or applying a signal that
is less than 0.8V above VS- will enable the amplifier. The
amplifier will be disabled when the signal at ENABLE pin is 2V
above VS-.
Output Drive Capability
The EL8302 does not have internal short circuit protection
circuitry. They have a typical short circuit current of 80mA
sourcing and 150mA sinking for the output is connected to half
way between the rails with a 10 resistor. If the output is
shorted indefinitely, the power dissipation could easily increase
such that the part will be destroyed. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnections.
Power Dissipation
With the high output drive capability of the EL8302, It is
possible to exceed the 125C absolute maximum junction
temperature under certain load current conditions. Therefore, it
is important to calculate the maximum junction temperature for
the application to determine if the load conditions or package
types need to be modified for the amplifier to remain in the safe
operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
Where:
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the load, or:
For sourcing:
3
PD MAX = V S I SMAX +
V OUTi
VS – VOUTi ---------------R Li
i=1
For sinking:
3
PD MAX = V S I SMAX +
VOUTi – VS - ILOADi
i=1
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current
VOUTi = Maximum output voltage of the application for each
channel
RLOADi = Load resistance tied to ground for each channel
ILOADi = Load current for eachh channel
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit board
layout is necessary for optimum performance. Lead lengths
should be as short as possible. The power supply pin must be
well bypassed to reduce the risk of oscillation. For normal
single supply operation, where the VS- pin is connected to the
ground plane, a single 4.7µF tantalum capacitor in parallel with
a 0.1µF ceramic capacitor from VS+ to GND will suffice. This
same capacitor combination should be placed at each supply
pin to ground if split supplies are to be used. In this case, the
VS- pin becomes the negative supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use of
sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the inverting
input pin. Strip line design techniques are recommended for
the signal traces.
Typical Applications
TJMAX = Maximum junction temperature
VIDEO SYNC PULSE REMOVER
TAMAX = Maximum ambient temperature
Many CMOS analog to digital converters have a parasitic latch
up problem when subjected to negative input voltage levels.
Since the sync tip contains no useful video information and it is
JA = Thermal resistance of the package
FN7348 Rev 2.00
May 6, 2005
Page 10 of 14
EL8302
a negative going pulse, we can chop it off. Figure 31 shows a
gain of 2 connections for EL8302. Figure 32 shows the
complete input video signal applied at the input, as well as the
output signal with the negative going sync pulse removed.
+2.5V
B 2MHz
1VP-P
+
75
-2.5V
5V
VIN
VS+
+
-
75
VS-
75
VOUT
75
1K
1K
1K
1K
75
VOUT
+2.5V
A 2MHz
2VP-P
75
+
-
75
-2.5V
1K
1K
FIGURE 31. SYNC PULSE REMOVER
ENABLE
FIGURE 33. TWO TO ONE MULTIPLEXER
1V
VIN
0.5V
0V
0V
-0.5V
1V
VOUT
0.5V
ENABLE
-1.5V
0V
-2.5V
1V
0V
M = 10µs/DIV
FIGURE 32. VIDEO SIGNAL
B
A
-1V
MULTIPLEXER
Besides the normal power down usage, the ENABLE pin of the
EL8302 can be used for multiplexing applications. Figure 33
shows two channels with the outputs tied together, driving a
back terminated 75 video load. A 2VP-P 2MHz sine wave is
applied to Amp A and a 1VP-P 2MHz sine wave is applied to
Amp B. Figure 34 shows the ENABLE signal and the resulting
output waveform at VOUT. Observe the break-before-make
operation of the multiplexing. Amp A is on and VIN1 is passed
through to the output when the ENABLE signal is low and turns
off in about 25ns when the ENABLE signal is high. About
200ns later, Amp B turns on and VIN2 is passed through to the
output. The break-before-make operation ensures that more
than one amplifier isn’t trying to drive the bus at the same time.
FN7348 Rev 2.00
May 6, 2005
M = 50ns/DIV
FIGURE 34.
SINGLE SUPPLY VIDEO LINE DRIVER
The EL8302 is wideband rail-to-rail output op amplifiers with
large output current, excellent dG, dP, and low distortion that
allow them to drive video signals in low supply applications.
Figure 35 is the single supply non-inverting video line driver
configuration and Figure 36 is the inverting video ling driver
configuration. The signal is AC coupled by C1. R1 and R2 are
used to level shift the input and output to provide the largest
output swing. RF and RG set the AC gain. C2 isolates the
virtual ground potential. RT and R3 are the termination
resistors for the line. C1, C2 and C3 are selected big enough to
minimize the droop of the luminance signal.
Page 11 of 14
EL8302
5V
RF
1k
VIN
C1
47µF
R1
10K
+
RT
75
R3
C3
470µF 75
VOUT
VIN
C1
RG
47µF 500
-
R2
10K
75
RT
75
5V
5V
-
R3
C3
470µF 75
VOUT
+
R1
10K
75
RF
1k
RG
1k
R2
10K
C2
220µF
NORMALIZED GAIN (dB)
FIGURE 35. 5V SINGLE SUPPLY NON INVERTING
VIDEO LINE DRIVER
C2
220µF
FIGURE 36. SINGLE SUPPLY INVERTING VIDEO LINE DRIVER
4
3
2
1
AV = 2
0
-1
-2
AV = -2
-3
-4
-5
-6
100K
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 37. VIDEO LINE DRIVER FREQUENCY RESPONSE
FN7348 Rev 2.00
May 6, 2005
Page 12 of 14
EL8302
SO Package Outline Drawing
FN7348 Rev 2.00
May 6, 2005
Page 13 of 14
EL8302
QSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN7348 Rev 2.00
May 6, 2005
Page 14 of 14