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FSL13A0R1

FSL13A0R1

  • 厂商:

    INTERSIL(Intersil)

  • 封装:

  • 描述:

    FSL13A0R1 - 9A, 100V, 0.180 Ohm, Rad Hard, SEGR Resistant, N-Channel Power MOSFETs - Intersil Corpor...

  • 数据手册
  • 价格&库存
FSL13A0R1 数据手册
FSL13A0D, FSL13A0R Data Sheet June 1999 File Number 4480.2 9A, 100V, 0.180 Ohm, Rad Hard, SEGR Resistant, N-Channel Power MOSFETs The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Reliability screening is available as either commercial, TXV equivalent of MIL-S-19500, or Space equivalent of MIL-S-19500. Contact Intersil for any desired deviations from the data sheet. Features • 9A, 100V, rDS(ON) = 0.180Ω • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM • Photo Current - 1.5nA Per-RAD(Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2 Symbol D G S Ordering Information RAD LEVEL 10K 10K 100K 100K 100K SCREENING LEVEL Commercial TXV Commercial TXV Space PART NUMBER/BRAND FSL13A0D1 FSL13A0D3 FSL13A0R1 FSL13A0R3 FSL13A0R4 Package TO-205AF D G S Formerly available as type TA17696. 4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000 FSL13A0D, FSL13A0R Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSL13A0D, FSL13A0R Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . . .IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) 100 100 9 6 27 ±20 25 10 0.20 27 9 27 -55 to 150 300 UNITS V V A A A V W W W/ oC A A A oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS , ID = 1mA TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC MIN 100 1.5 0.5 VGS = 0V to 20V VGS = 0V to 12V VGS = 0V to 2V VDD = 50V, ID = 9A ID = 9A, VDS = 15V VDS = 25V, VGS = 0V, f = 1MHz TYP 0.130 35 6.7 19 8 760 310 110 MAX 5.0 4.0 25 250 100 200 1.70 0.180 0.290 20 80 45 30 60 41 1.9 8.2 22 5.0 175 UNITS V V V V µA µA nA nA V Ω Ω ns ns ns ns nC nC nC nC nC V pF pF pF oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current IDSS IGSS VDS(ON) rDS(ON)12 td(ON) tr td(OFF) tf Qg(TOT) Qg(12) Qg(TH) Qgs Qgd V(PLATEAU) CISS COSS CRSS RθJC RθJA VDS = 80V, VGS = 0V VGS = ±20V VGS = 12V, ID = 9A ID = 6A, VGS = 12V Gate to Source Leakage Current Drain to Source On-State Voltage Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate Charge at 12V Threshold Gate Charge Gate Charge Source Gate Charge Drain Plateau Voltage Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient VDD = 50V, ID = 9A, RL = 5.56Ω, VGS = 12V, RGS = 7.5Ω 4-2 FSL13A0D, FSL13A0R Source to Drain Diode Specifications PARAMETER Forward Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 9A ISD = 9A, dISD/dt = 100A/µs TC = 25oC, Unless Otherwise Specified SYMBOL (Note 3) (Note 3) (Notes 2, 3) (Note 3) (Notes 1, 3) (Notes 1, 3) BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON)12 TEST CONDITIONS VGS = 0, ID = 1mA VGS = VDS , ID = 1mA VGS = ±20V, VDS = 0V VGS = 0, VDS = 80V VGS = 12V, ID = 9A VGS = 12V, ID = 6A MIN 100 1.5 MAX 4.0 100 25 1.70 0.180 UNITS V V nA µA V Ω TEST CONDITIONS MIN 0.6 TYP MAX 1.8 260 UNITS V ns Electrical Specifications up to 100K RAD PARAMETER Drain to Source Breakdown Volts Gate to Source Threshold Volts Gate to Body Leakage Zero Gate Leakage Drain to Source On-State Volts Drain to Source On Resistance NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) (Note 4) ENVIRONMENT (NOTE 5) TEST Single Event Effects Safe Operating Area SYMBOL SEESOA ION SPECIES Ni Br Br Br NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). TYPICAL LET (MeV/mg/cm) 26 37 37 37 TYPICAL RANGE (µ) 43 36 36 36 APPLIED VGS BIAS (V) -20 -10 -15 -20 (NOTE 6) MAXIMUM VDS BIAS (V) 100 100 80 50 Typical Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43µ LET = 37MeV/mg/cm2, RANGE = 36µ 120 100 80 VDS (V) 60 40 20 TEMP = 25oC 0 0 -5 -10 VGS (V) -15 -20 -25 LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) 1E-3 1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6 1E-7 10 30 100 DRAIN SUPPLY (V) 300 1000 FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS 4-3 FSL13A0D, FSL13A0R Typical Performance Curves 12 Unless Otherwise Specified (Continued) 100 TC = 25oC 10 ID , DRAIN CURRENT (A) 10 100µs ID , DRAIN (A) 8 6 1ms 4 2 0 -50 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) 10ms 100ms 0 50 100 150 0.1 TC , CASE TEMPERATURE (oC) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 PULSE DURATION = 250ms, VGS = 12V, ID = 6A 2.0 12V QG NORMALIZED rDS(ON) 1.5 QGS VG QGD 1.0 0.5 CHARGE BASIC GATE CHARGE WAVEFORM 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE 10 NORMALIZED THERMAL RESPONSE (ZθJC) 1 0.5 0.2 0.1 0.05 0.02 0.01 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 SINGLE PULSE 0.1 PDM t1 t2 101 0.001 10-5 FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE 4-4 FSL13A0D, FSL13A0R Typical Performance Curves 50 IAS , AVALANCHE CURRENT (A) Unless Otherwise Specified (Continued) STARTING TJ = 25oC 10 STARTING TJ = 150oC IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 1 0.1 1 0.01 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L + CURRENT I TRANSFORMER AS BVDSS tP IAS 50Ω + VDD VDS VDD - VARY tP TO OBTAIN REQUIRED PEAK IAS VGS ≤ 20V DUT 50V-150V 50Ω tAV 0V tP FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS VDD tON td(ON) tOFF td(OFF) tr tf 90% RL VDS VGS = 12V DUT 0V RGS VDS 90% 10% 10% 90% VGS 10% 50% PULSE WIDTH 50% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS 4-5 FSL13A0D, FSL13A0R Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified PARAMETER Gate to Source Leakage Current Zero Gate Voltage Drain Current On Resistance Gate Threshold Voltage NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS VGS = ±20V VDS = 80% Rated Value TC = 25oC at Rated ID ID = 1.0mA MAX ±20 (Note 7) ±25 (Note 7) ±20% (Note 8) ±20% (Note 8) UNITS nA µA Ω V Screening Information TEST Gate Stress Pind Pre Burn-In Tests (Note 9) JANTXV EQUIVALENT VGS = 30V, t = 250µs Optional MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours 10% MIL-S-19500, Group A, Subgroup 2 JANS EQUIVALENT VGS = 30V, t = 250µs Required MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours 5% MIL-S-19500, Group A, Subgroups 2 and 3 Steady State Gate Bias (Gate Stress) Interim Electrical Tests (Note 9) Steady State Reverse Bias (Drain Stress) PDA Final Electrical Tests (Note 9) NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL SOA IAS ∆VSD ∆VSD TEST CONDITIONS VDS = 80V, t = 10ms VGS(PEAK) = 15V, L = 0.1mH tH = 10ms; VH = 25V; IH = 1A tH = 500ms; VH = 25V; IH = 1A MAX 1.4 27 60 230 UNITS A A mV mV 4-6 FSL13A0D, FSL13A0R Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A E. Group B F. Group C G. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet Class S - Equivalents 1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A G. Group B H. Group C I. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler - Pre and Post Burn-In Read and Record Data D. Group A E. Group B - Attributes Data Sheet - Group A Lot Traveler - Attributes Data Sheet - Group B Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) - Attributes Data Sheet - Group C Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) - Attributes Data Sheet - Group D Lot Traveler - Pre and Post RAD Read and Record Data 2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data F. Group C G. Group D G. Group B H. Group C I. Group D 4-7 FSL13A0D, FSL13A0R TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE ØD ØD1 A P INCHES SYMBOL A Øb MIN 0.160 0.016 0.350 0.315 0.095 0.190 0.095 0.010 0.028 0.029 0.500 0.075 MAX 0.180 0.021 0.370 0.335 0.105 0.210 0.105 0.020 0.034 0.045 0.560 - MILLIMETERS MIN 4.07 0.41 8.89 8.01 2.42 4.83 2.42 0.26 0.72 0.74 12.70 1.91 MAX 4.57 0.53 9.39 8.50 2.66 5.33 2.66 0.50 0.86 1.14 14.22 NOTES 2, 3 4 4 4 3 5 h L SEATING PLANE Øb ØD ØD1 e e1 e e1 90o 3 e2 h j k L P k 2 e2 45o j 1 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-8
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