GRM21BR60J106KE19L

3MHz Dual Step-Down Converters and Dual Low-Input LDOs with I2C Compatible Interface ISL9305 The ISL9305 is an integrated mini Power Management IC (mini-PMIC) ideal for applications of powering low-voltage microprocessor or multiple voltage rails with battery as input sources, such as a single Li-ion or Li-Polymer. ISL9305 integrates two high-efficiency 3MHz synchronous step-down converters (DCD1 and DCD2) and two low-input, low-dropout linear regulators (LDO1 and LDO2). The 3MHz PWM switching frequency allows the use of very small external inductors and capacitors. Both step-down converters can enter skip mode under light load conditions to further improve the efficiency and maximize the battery life. For noise sensitive applications, they can also be programmed through I2C interface to operate in forced PWM mode regardless of the load current condition. The I2C interface supports on-the-fly slew rate control of the output voltage from 0.825V to 3.6V at 25mV/step size for dynamic power saving. Each step-down converter can supply up to 800mA load current. The default output voltage can be set from 0.8V to VIN using external feedback resistors on the adjustable version, or the ISL9305 can be ordered in factory pre-set power-up default voltages in increments of 100mV from 0.9V to 3.6V. The ISL9305 also provides two 300mA low dropout (LDO) regulators. The input voltage range is 1.5V to 5.5V allowing them to be powered from one of the on-chip step-down converters or directly from the battery. The default LDO power-up output comes with factory pre-set fixed output voltage options between 0.9V to 3.3V. The ISL9305 is available in a 4mmx4mm 16 Ld TQFN package. Features • Dual 800mA, Synchronous Step-down Converters and Dual 300mA, General-purpose LDOs • Input Voltage Range - DCD1/DCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V - LDO1/LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V • 400kb/s I2C-bus Series Interface Transfers the Control Data Between the Host Controller and the ISL9305 • Adjustable Output Voltage - DCD1/DCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to VIN - Fixed Output I2C Programmability • At 25mV/step . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.825V to 3.6V • LDO1/LDO2 Output Voltage I2C Programmability - At 50mV/step. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 3.3V • 50μA IQ (Typ) with DCD1/DCD2 in Skip Mode; 20μA IQ (Typ) for each Enabled LDO • On-the-fly I2C Programming of DC/DC and LDO Output Voltages • DCD1/DCD2 I2C Programmable Skip Mode Under Light Load or Forced Fixed Switching Frequency PWM Mode • Small, Thin, 4mmx4mm TQFN Package Applications • Cellular Phones, Smart Phones • PDAs, Portable Media Players, Portable Instruments • Single Li-ion/Li-Polymer Battery-Powered Equipment • DSP Core Power Related Literature • FN7724, ISL9305H Data Sheet • AN1564 “ISL9305IRTZEVAL1Z and ISL9305HIRTZEVAL1Z Evaluation Boards” 2.3V TO 5.5V C10 10µF PG VINDCD1 VINDCD2 SDAT SCLK C2 1µF VINLDO1 VINLDO2 SW1 FB1 SW2 L1 = 1 .5µH R1 L2 = 1 .5µH R3 R4 * R2 * 800mA C4 4.7µF 800mA C5 4.7µF 300mA 300mA 1.5V TO 5.5V 1.5V TO 5.5V C3 1µF ISL9305 FB2 VOLDO1 VOLDO2 GNDDCD1GNDDCD2GNDLDO C6 1µF C7 1µF *Only for adjustable output version. For fixed output version, directly connect the FB pin to the output of the buck converter. FIGURE 1. TYPICAL APPLICATION DIAGRAM November 8, 2010 FN7605.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL9305 TABLE 1. TYPICAL APPLICATION PART LIST PARTS L1, L2 C1 C2, C3 C4, C5 C6, C7 R1, R2, R3, R4 DESCRIPTION Inductor Input capacitor Input capacitor Output capacitor Output capacitor Resistor MANUFACTURER Sumida Murata Murata Murata Murata Various PART NUMBER CDRH2D14NP-1R5 GRM21BR60J106KE19L GRM185R60J105KE26D GRM219R60J475KE01D GRM185R60J105KE26D SPECIFICATIONS 1.5µH/1.80A/50mΩ 10µF/6.3V 1µF/6.3V 4.7µF/6.3V 1µF/6.3V 1%, SMD, 0.1Ω SIZE 3.0mmx3.0mmx1.55mm 0805 0603 0805 0603 0603 NOTE: 1. C4 and C5 are 10µF/6.3V for VODCD less than 1V. Block Diagram SHORT CIRCUIT PROTECTION ANALOG/LOGIC CIRCUIT INPUT VINDCD1 10µF SW1 DCD1 PGOOD WITH 1~200MS DELAY TIME BUCK CONVERTER FB1 GNDDCD1 VINDCD2 SW2 DCD2 UVLO VREF OSC BUCK CONVERTER FB2 GNDDCD2 1.5µH 10µF 4.7µF 1.5µH 4.7µF DCDPG OVERCURRENT PROTECTION THERMAL SHUTDOWN LDO1 300mA SDAT SCLK I2C INTERFACE LDO2 300mA VINLDO1 1µF VOLDO1 10µF VINLDO2 1µF VOLDO2 GNDLDO 10µF 2 FN7605.0 November 8, 2010 ISL9305 Pin Configuration ISL9305 (16 LD 4X4 TQFN) TOP VIEW GNDCDC1 GNDDCD2 14 16 SW1 15 SW2 13 12 VINDCD2 11 FB2 10 DCDPG VINDCD1 1 FB1 2 E-PAD SCLK 3 SDAT 4 5 6 7 8 9 GNDLDO VOLDO1 VINLDO1 VOLDO2 Pin Descriptions PIN NUMBER (TQFN) 1 2 3 4 5 6 7 8 9 10 NAME VINDCD1 FB1 SCLK SDAT VINLDO1 VOLDO1 VOLDO2 VINLDO2 GNDLDO DCDPG DESCRIPTION Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/ analog circuits. Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For fixed output versions, connect this pin directly to the DCD1 output. I2C interface clock pin. I2C interface data pin. Input voltage for LDO1. Output voltage of LDO1. Output voltage of LDO2. Input voltage for LDO2. Power ground for LDO1 and LDO2. The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1 and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter voltages are within the power-good range. The pin will be pulled low if either DCD is outside their range. When only one DCD is enabled, the state of the enabled DCD’s output will define the state of the DCDPG pin. The DCDPG state can be programmed for a delay of up to 200ms before being released to rise high. The programming range is 1ms~200ms through the I2C interface. Feedback pin for DCD2, connect external voltage divider resistors between DCD2 output, this pin and ground. For fixed output versions, connect this pin directly to the DCD2 output. Input voltage for buck converter DCD2. Switching node for DCD2, connect to one terminal of the inductor. Power ground for DCD2. Power ground for DCD1. Switching node for DCD1, connect to one terminal of the inductor. Exposed Pad. Connect to system ground. 11 12 13 14 15 16 E-pad FB2 VINDCD2 SW2 GNDDCD2 GNDDCD1 SW1 E-pad 3 VINLDO2 FN7605.0 November 8, 2010 ISL9305 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL9305IRTAANLZ-T ISL9305IRTBCNLZ-T ISL9305IRTBFNCZ-T ISL9305IRTWBNLZ-T ISL9305IRTWCLBZ-T ISL9305IRTWCNLZ-T ISL9305IRTWCNYZ-T ISL9305IRTWLNCZ-T ISL9305IRTZEVAL1Z NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9305. For more information on MSL please see techbrief TB363. PART MARKING 9305I AANLZ 9305I BCNLZ 9305I BFNCZ 9305I WBNLZ 9305I WCLBZ 9305I WCNLZ 9305I WCNYZ 9305I WLNCZ Evaluation Board FBSEL DCD1 (V) Adj 1.5 1.5 1.2 1.2 1.2 1.2 1.2 FBSEL DCD2 (V) Adj 1.8 2.5 1.5 1.8 1.8 1.8 2.9 SLV LDO1 (V) 3.3 3.3 3.3 3.3 2.9 3.3 3.3 3.3 SLV LDO2 (V) 2.9 2.9 1.8 2.9 1.5 2.9 0.9 1.8 TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE Tape and Reel (Pb-free) 16 Ld TQFN 16 Ld TQFN 16 Ld TQFN 16 Ld TQFN 16 Ld TQFN 16 Ld TQFN 16 Ld TQFN 16 Ld TQFN PKG. DWG. # L16.4x4G L16.4x4G L16.4x4G L16.4x4G L16.4x4G L16.4x4G L16.4x4G L16.4x4G 4 FN7605.0 November 8, 2010 ISL9305 Absolute Maximum Ratings (Refer to ground) SW1, SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3.6V GNDDCD1, GNDDCD2, GNDLDO. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V ESD Ratings Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .3.5kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 2.2kV Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . 225V Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 16 Ld TQFN Package (Notes 4, 5) . . . . . . . 42 5 Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C Recommended Junction Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VINDCD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V VINDCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to VINDCD1 VINLDO1 and VINLDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to VINDCD1 DCD1 and DCD2 Output Current . . . . . . . . . . . . . . . . . . . . . 0mA to 800mA LDO1 and LDO2 Output Current . . . . . . . . . . . . . . . . . . . . . . 0mA to 300mA Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For LDO1 and LDO2, VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH, C1 = 10µF, C4 = C5 = 4.7µF, C2 = C3 = C6 = C7 = 1µF, IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see Figure 1 on page 1 for more details). PARAMETER VINDCD1, VINDCD2 Voltage Range VINDCD1, VINDCD2 Undervoltage Lockout Threshold Quiescent Supply Current on VINDCD1 VUVLO Rising Falling IVIN1 IVIN2 IVIN3 IVIN4 IVIN5 Only DCD1 enabled, no load and no switching on DCD1 Only DCD1 and LDO1 enabled, with no load and no switching on DCD1 Both DCD1 and DCD2 enabled, no load and no switching on both DCD1 and DCD2 Only LDO1 and LDO2 enabled DCD1, DCD2, LDO1 and LDO2 are enabled, with no load and no switching on both DCD1 and DCD2 Only one DCD in forced PWM mode, no load VINDCD1 = 5.5V, DCD1, DCD2, LDO1 and LDO2 are disabled through I2C interface, VINDCD1 = 4.2V SYMBOL TEST CONDITIONS MIN (Note 6) 2.3 1.9 TYP 2.2 2.1 40 65 50 75 100 MAX (Note 6) 5.5 2.3 60 95 75 100 130 UNIT V V V µA µA µA µA µA IVIN6 Shutdown Supply Current ISD - 4 0.15 7.5 5 mA µA Thermal Shutdown Thermal Shutdown Hysteresis DCD1 AND DCD2 FB1, FB2 Regulation Voltage FB1, FB2 Bias Current VFB IFB FB = 0.75V - 155 30 - °C °C 0.785 - 0.8 0.001 0.815 - V µA 5 FN7605.0 November 8, 2010 ISL9305 Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For LDO1 and LDO2, VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH, C1 = 10µF, C4 = C5 = 4.7µF, C2 = C3 = C6 = C7 = 1µF, IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see Figure 1 on page 1 for more details). (Continued) PARAMETER Output Voltage Accuracy Line Regulation Maximum Output Current P-Channel MOSFET ON-resistance VIN = 3.6V, IO = 200mA VIN = 2.3V, IO = 200mA N-Channel MOSFET ON-resistance VIN = 3.6V, IO = 200mA VIN = 2.3V, IO = 200mA P-Channel MOSFET Peak Current Limit SW Maximum Duty Cycle SW Leakage Current PWM Switching Frequency SW Minimum ON-time Bleeding Resistor fS VFB = 0.75V VIN = 5.5V IPK SYMBOL TEST CONDITIONS VIN = VO + 0.5V to 5.5V (minimal 2.3V), 1mA load VIN = VO + 0.5V to 5.5V (minimal 2.3V) MIN (Note 6) -3 800 1.075 2.6 TYP 0.1 0.14 0.24 0.11 0.18 1.3 100 0.005 3.0 70 115 MAX (Note 6) +3 0.2 0.40 0.2 0.34 1.6 1 3.4 UNIT % %/V mA Ω Ω Ω Ω A % µA MHz ns Ω PG Output Low Voltage Rising Delay Time Falling Delay Time PG Pin Leakage Current PG Low Rising Threshold PG Low Falling Threshold PG High Rising Threshold PG High Falling Threshold Sinking 1mA, FB1 = FB2 = 0.7V Based on 1ms programmed nominal delay time Based on 1ms programmed nonimal delay time PG = VINDCD1 = VINDCD2 = 3.6V Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage 0.6 1.1 30 0.005 91 87 112 109 0.25 1.8 0.1 V ms µs µA % % % % LDO1 AND LDO2 VINLDO1, VINLDO2 Supply Voltage VINLDO1, VINLDO2 Undervoltage Lock-out Threshold Internal Peak Current Limit Dropout Voltage IO = 300mA, VO ≤ 2.1V IO = 300mA, 2.1V < VO ≤ 2.8V IO = 300mA, VO > 2.8V Power Supply Rejection Ratio Output Voltage Noise IO= 300mA @ 1kHz, VIN = 3.6V, VO = 2.6V, TA = +25°C VIN = 4.2V, IO = 10mA, TA = +25°C, BW = 10Hz to 100kHz VUVLO No higher than VINDCD1 VINDCD1 = 2.3V, Rising VINDCD1 = 2.3V, Falling 1.5 1.33 350 1.41 1.37 425 125 100 80 55 45 5.5 1.46 540 250 200 170 V V V mA mV mV mV dB µVRMS NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6 FN7605.0 November 8, 2010 ISL9305 Theory of Operation DCD1 and DCD2 Introduction Both the DCD1 and DCD2 converters on ISL9305 use the peak-current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Both converters are able to supply up to 800mA load current. The default output voltage ranges from 0.8V to 3.6V depending on the factory pre-set configuration and can be programmed via the I2C interface in the range of 0.825V to 3.6V at 25mV/step with a programmable slew rate. An open-drain DCDPG (DCD Power-Good) signal is also provided to monitor the DCD1 and DCD2 output voltages. Optionally, both DCD1 and DCD2 can be programmed to be actively discharged via an on-chip bleeding resistor (typical 115Ω) when the converter is disabled. cycles, the regulator enters the skip mode. During the 16 consecutive cycles, the inductor current could be negative. The counter is reset to zero when the sensed current flowing through the SW node does not cross zero during any cycle within the 16 consecutive cycles. Once the converter enters the skip mode, the pulse modulation is controlled by an internal comparator while each pulse cycle remains synchronized to the PWM clock. The P-Channel MOSFET is turned on at the rising edge of the clock and turned off when its current reaches ~20% of the peak current limit. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle-over-cycle. When the output voltage is sensed to reach 1.5% above its nominal voltage, the P-Channel MOSFET is turned off immediately and the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-Channel MOSFET will be turned on again, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage is sensed to drop below 1.5% of its nominal voltage value as shown in Figure 3. Skip Mode (PFM Mode) for DCD1/DCD2 Under light load condition, the DCD1 and DCD2 can be programmed to automatically enter a pulse-skipping mode to minimize the switching loss by reducing the switching frequency. Figure 2 illustrates the skip mode operation. A zero-cross sensing circuit monitors the current flowing through the SW node for zero crossing. When it is detected to cross zero for 16 consecutive 16 CYCLES CLOCK 20% PEAK CURRENT LIMIT IL 0 1.015*VOUT_NOMINAL VOUT VOUT_NOMINAL FIGURE 2. SKIP MODE OPERATION WAVEFORMS vEAMP vCSA d iL vOUT F IGURE 3. PWM OPERATION WAVEFORMS 7 FN7605.0 November 8, 2010 ISL9305 Soft-Start The soft-start reduces the in-rush current during the start-up stage. The soft-start block limits the current rising speed so that the output voltage rises in a controlled fashion. Low Dropout Operation Both DCD1 and DCD2 converters feature the low dropout operation to maximize the battery life. When the input voltage drops to a level that the converter can no longer operate under switching regulation to maintain the output voltage, the P-Channel MOSFET is completely turned on (100% duty cycle). The dropout voltage under such a condition is the product of the load current and the ON-resistance of the P-Channel MOSFET. Minimum required input voltage VIN under such condition is the sum of output voltage plus the voltage drop across the inductor and the P-Channel MOSFET switch. Overcurrent Protection The overcurrent protection for DCD1 and DCD2 is provided on ISL9305 for when an overload condition occurs. When the current at P-Channel MOSFET is sensed to reach the current limit, the internal protection circuit is triggered to turn off the P-Channel MOSFET immediately. DCD Short-Circuit Protection The ISL9305 provides Short-Circuit Protection for both DCD1 and DCD2. The feedback voltage is monitored for output short-circuit protection. When the output voltage is sensed to be lower than a certain threshold, the internal circuit will change the PWM oscillator frequency to a lower frequencies in order to protect the IC from damage. The P-Channel MOSFET peak current limit remains active during this state. Active Output Voltage Discharge For DCD1/DCD2 The ISL9305 offers a feature to actively discharge the output voltage of DCD1 and DCD2 via an internal bleeding resistor (typical 115Ω) when the channel is disabled. This feature is enabled by default, thus outputs can be disabled individually through programming the control bit in DCD_PARAMETER register. Undervoltage Lock-out (UVLO) An undervoltage lock-out (UVLO) circuit is provided on ISL9305. The UVLO circuit block can prevent abnormal operation in the event that the supply voltage is too low to guarantee proper operation. The UVLO on VINDCD1 is set for a typical 2.2V with 100mV hysteresis. VINLDO1 and VINLDO2 are set for a typical 1.4V with 50mV hysteresis. When the input voltage is sensed to be lower than the UVLO threshold, the related channel is disabled. Thermal Shutdown The ISL9305 provides built-in thermal protection function with thermal shutdown threshold temperature set at +155°C with +25°C hysteresis (typical). When the die temperature is sensed to reach +155°C, the regulator is completely shut down and as the temperature is sensed to drop to +130°C (typical), the device resumes normal operation starting from the soft-start. Board Layout Recommendations The ISL9305 is a high frequency switching charger and hence the PCB layout is a very important design practice to ensure a satisfactory performance. The power loop is composed of the output inductor L, the output capacitor COUT, the SW pin and the PGND pin. It is important to make the power loop as small as possible and the connecting traces among them should be direct, short and wide; the same practice should be applied to the connection of the VIN pin, the input capacitor CIN and PGND. The switching node of the converter, the SW pin, and the traces connected to this node are very noisy, so keep the voltage feedback trace and other noise sensitive traces away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin. The ground of the input and output capacitors should be connected as close as possible as well. In addition, a solid ground plane is helpful for a good EMI performance. The ISL9305 employs a thermal enhanced TQFN package with an exposed pad. The exposed pad should be properly soldered on thermal pad of the board in order to remove heat from the IC. The thermal pad should be big enough for 9 vias as shown in Figure 4. DCDPG (DCD Power-Good) ISL9305 offers an open-drain Power-Good signal with programmable delay time for monitoring the converters DCD1 and DCD2 output voltages status. When both DCD1 and DCD2 are enabled and their output voltages are within the power-good window, an internal power-good signal is issued to turn off the open-drain MOSFET so the DCDPG pin voltage can be externally pulled high after a programmed delay time. If either DCD1 or DCD2 output voltages or both of them are not within the power-good window, the DCDPG outputs an open-drain logic low signal after the programmed delay time. When there is only one DCD converter (either DCD1 or DCD2) is enabled, then the DCDPG only indicates the status of this active DCD converter. For example, if only DCD1 converter is enabled and DCD2 converter is disabled, when DCD1 output is within the power-good window, internal power-good signal will be issued to turn off the open-drain MOSFET so the DCDPG pin voltage is externally pulled high after the programmed delay time. If output voltage of DCD1 is outside the power-good window, the DCDPG outputs an open-drain logic low signal after the programmed delay time. It is similar when only DCD2 is enabled and DCD1 is disabled. When both converters are disabled, DCDPG always outputs the open-drain logic low signal. 8 FN7605.0 November 8, 2010 ISL9305 I2C Slave Address The ISL9305 serves as a slave device and the 7-bit default chip address is 1101000, as shown in Figure 5 According to the I2C specifications, here the value of Bit 0 determines the direction of the message (“0” means “write” and “1” means “read”). MSB 1 1 BIT 6 0 BIT 5 1 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 LSB R/W BIT 0 FIGURE 4. EXPOSED THERMAL PAD BIT 7 I2C Compatible Interface The ISL9305 offers an I2C compatible interface, using two pins: SCLK for the serial clock and SDAT for serial data respectively. According to the I2C specifications, a pull-up resistor is needed for the clock and data signals to connect to a positive supply. When the ISL9305 and the host use different supply voltages, the pull-up resistors should be connected to the higher voltage rail. Signal timing specifications should satisfy the standard I2C bus specification. The maximum bit rate is 400kb/s and more details regarding the I2C specifications can be found from Philips. S SLAVE ADDRESS 0A REGISTER ADDRESS A DATA BYTE 1 FIGURE 5. I2C SLAVE ADDRESS I2C Protocol Figures 6, 7, and 8 show three typical I2C-bus transaction protocols. A SYSTEM HOST R/W OPTIONAL AUTO INCREMENT REGISTER ADDRESS ISL9305 A – ACKNOWLEDGE N – NOT ACKNOWLEDGE S – START P – STOP DATA BYTE 2 A DATA BYTE N A P AUTO INCREMENT REGISTER ADDRESS AUTO INCREMENT REGISTER ADDRESS FIGURE 6. I 2C WRITE S SLAVE ADDRESS 0A REGISTER ADDRESS A S SLAVE ADDRESS 1 A SYSTEM HOST R/W OPTIONAL R/W ISL9305 A – ACKNOWLEDGE N – NOT ACKNOWLEDGE S – START P – STOP DATA BYTE 1 A DATA BYTE 2 A DATA BYTE N N P AUTO INCREMENT REGISTER ADDRESS AUTO INCREMENT REGISTER ADDRESS AUTO INCREMENT REGISTER ADDRESS FIGURE 7. I2C READ SPECIFYING REGISTER ADDRESS 9 FN7605.0 November 8, 2010 ISL9305 OPTIONAL S SLAVE ADDRESS 1A DATA BYTE 1 A DATA BYTE 2 A DATA BYTE N N P R/W AUTO INCREMENT REGISTER ADDRESS AUTO INCREMENT REGISTER ADDRESS AUTO INCREMENT REGISTER ADDRESS SYSTEM HOST A – ACKNOWLEDGE N – NOT ACKNOWLEDGE S – START ISL9305 P – STOP FIGURE 8. I2C READ NOT SPECIFYING REGISTER ADDRESS I2C Control Registers All the registers are reset at initial start-up. TABLE 2. BUCK CONVERTERS OUTPUT VOLTAGE CONTROL REGISTER BIT B7 B6 B5 B4 B3 B2 B1 B0 NAME Reserve DCDxOUT-6 DCDxOUT-5 DCDxOUT-4 DCDxOUT-3 DCDxOUT-2 DCDxOUT-1 DCDxOUT-0 ACCESS R/W R/W R/W R/W R/W R/W R/W RESET 0 0 0 1 0 0 0 0 Refer to Table 3 DESCRIPTION Refer to Table 3 DCD OUTPUT VOLTAGE CONTROL REGISTER DCD1OUT, address 0x00h; DCD2OUT, address 0x01h 10 FN7605.0 November 8, 2010 ISL9305 TABLE 3. DCD1 AND DCD2 OUTPUT VOLTAGE SETTING DCDOUT 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DCD OUTPUT VOLTAGE (V) 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 DCDOUT 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F DCD OUTPUT VOLTAGE (V) 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.875 1.900 1.925 1.950 1.975 2.000 2.025 2.050 2.075 2.100 2.125 2.150 2.175 2.200 2.225 2.250 2.275 2.300 2.325 2.350 2.375 2.400 DCDOUT 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F DCD OUTPUT VOLTAGE (V) 2.425 2.450 2.475 2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150 3.175 3.200 DCDOUT 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F DCD OUTPUT VOLTAGE (V) 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 LDO1 AND LDO2 OUTPUT VOLTAGE CONTROL REGISTERS LDO1OUT, address 0x02h and LDO2OUT, address 0x03h. TABLE 4. LDOX OUTPUT VOLTAGE CONTROL REGISTERS BIT B7 B6 B5 B4 B3 B2 B1 B0 NAME Reserve Reserve LDOxOUT-5 LDOxOUT-4 LDOxOUT-3 LDOxOUT-2 LDOxOUT-1 LDOxOUT-0 ACCESS R/W R/W R/W R/W R/W R/W RESET 0 0 0 0 1 1 0 0 DESCRIPTION Refer to Table 5 for output voltage settings 11 FN7605.0 November 8, 2010 ISL9305 TABLE 5. LDOX OUTPUT VOLTAGE SETTINGS LDOOUT 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F LDO OUTPUT VOLTAGE (V) 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 LDOOUT 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F LDO OUTPUT VOLTAGE (V) 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 LDOOUT 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F LDO OUTPUT VOLTAGE (V) 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 LDOOUT 30 31 32 33 34 35 36 LDO OUTPUT VOLTAGE (V) 3.30 3.35 3.40 3.45 3.50 3.55 3.60 DCD1 AND DCD2 CONTROL REGISTER DCD_PARAMETER, address 0x04h TABLE 6. DCD_PARAMETER REGISTER BIT B7 B6 NAME DCD_PHASE ACCESS R/W RESET 0 0 DESCRIPTION Reserved DCD1 and DCD2 PWM switch selection. 0-in phase; 1 to 180° out-of-phase. Ultrasonic feature under PFM mode for DCD2. 0-disabled; 1-enabled. Ultrasonic feature under PFM mode for DCD1. 0-disabled; 1-enabled. Selection of DCD2 for active output voltage discharge when disabled. 0-disabled; 1enabled. Selection of DCD1 for active output voltage discharge when disabled. 0-disabled; 1enabled. Selection on DCD2 of auto PFM/PWM mode (= 1) or forced PW mode (= 0). Selection on DCD1 of auto PFM/PWM mode (= 1) or forced PW mode (= 0). SYSTEM CONTROL REGISTER SYS_PARAMETER, address 0x05h TABLE 7. SYS_PARAMETER REGISTER BIT B7 B6 B5 B4 NAME I2C_EN DCDPOR_1 DCDPOR_0 ACCESS R/W R/W R/W RESET 0 0 1 0 DESCRIPTION Reserved I2C function enable. 0-disabled; 1-enabled DCDPOR Delay Time Setting, DCDPOR[1:0]: 00 to 1ms 01 to 50ms 10 to 150ms 11 to 200m LDO2 enable selection. 0-disable, 1-enable. LDO1 enable selection. 0-disable, 1-enable DCD2 enable selection. 0-disable, 1-enable. DCD2 enable selection. 0-disable, 1-enable B5 DCD2_ULTRA R/W 0 B4 DCD1_ULTRA R/W 0 B3 B2 B1 B0 LDO2_EN LDO1_EN DCD2_EN DCD1_EN R/W R/W R/W R/W 1 1 1 1 B3 DCD2_BLD R/W 1 B2 DCD1_BLD R/W 1 B1 DCD2_MODE R/W 1 B0 DCD1_MODE R/W 1 12 FN7605.0 November 8, 2010 ISL9305 DCD OUTPUT VOLTAGE SLEW RATE CONTROL REGISTER DCD_SRCTL, address 0x06h TABLE 8. BIT B7 B6 B5 NAME DCD2SR_2 DCD2SR_1 DCD2SR_0 ACCESS R/W R/W R/W RESET 0 0 1 DESCRIPTION DCD2 Slew Rate Setting, DCD2SR[2:0]: 000 to 0.225mV/µs 001 to 0.45mV/µs 010 to 0.90mV/µs 011 to 1.8mV/µs 100 to 3.6mV/µs 101 to 7.2mV/µs 110 to 14.4mV/µs 111 to immediate Reserved DCD1 Slew Rate Setting, DCD1SR[2:0]: 000 to 0.225mV/µs 001 to 0.45mV/µs 010 to 0.90mV/µs 011 to 1.8mV/µs 100 to 3.6mV/µs 101 to 7.2mV/µs 110 to 14.4mV/µs 111 to immediate Reserved B4 B3 B2 B1 Reserve DCD1SR_2 DCD1SR_1 DCD1SR_0 R/W R/W R/W 0 0 0 1 B0 Reserve - 0 Typical Operating Conditions VODCD1(20mV/DIV, AC-COUPLING) VODCD1(20mV/DIV, AC-COUPLING) SW2(5V/DIV) VODCD2(20mV/DIV, AC-COUPLING) IL1 (500mA/DIV) VODCD2(20mV/DIV, AC-COUPLING) SW1(5V/DIV) IL2 (500mA/DIV) FIGURE 9. DCD OUTPUT VOLTAGE RIPPLE (VIN = 4.2V, FULL LOAD AT DCD1 AND DCD2) FIGURE 10. DCD OUTPUT VOLTAGE RIPPLE (VIN = 4.2V, PFM MODE) 13 FN7605.0 November 8, 2010 ISL9305 Typical Operating Conditions (Continued) VODCD1 (100mV/DIV VOLDO1 (100mV/DIV VODCD2 (10mV/DIV) VOLDO2 (10mV/DIV) IOUT_VODCD1 (500mA/DIV IOUT_LDO1 (200mA/DIV FIGURE 11. DCD OUTPUT TRANSIENT RESPONSE (VIN = 4.2V, LOAD STEP: 80mA to 800mA) FIGURE 12. LDO OUTPUT TRANSIENT RESPONSE (VIN = 4.2V, STEP LOAD: 30mA TO 300mA) IL2 (200mA/DIV) VODCD1 (2V/DIV) VODCD2 (1V/DIV) IL1 (200mA/DIV) SW1 (5V/DIV) VOLDO1 (1V/DIV) VOLDO2 (2V/DIV) SW2 (5V/DIV) FIGURE 13. START-UP SEQUENCY (V IN = 4.2V, NO LOAD) FIGURE 14. DCD1 and DCD2 SWITCHING WAVEFORM (VIN = 5V, FULL LOAD ON TWO CHANNELS) 1.23 1.22 OUTPUT VOLTAGE (V) 1.21 1.20 1.19 1.18 1.17 VIN = 5.5V 1.83 1.82 OUTPUT VOLTAGE (V) 1.81 1.80 1.79 1.78 1.77 1.76 VIN = 5.5V VIN = 3.6V VIN = 2.8V VIN = 3.6V VIN = 2.8V 1 10 100 1000 OUTPUT CURRENT (mA) 10000 1 10 100 1000 OUTPUT CURRENT (mA) 10000 FIGURE 15. DCD OUTPUT VOLTAGE vs LOAD (VOUT = 1 .2V, PFM/PWM) FIGURE 16. DCD OUTPUT VOLTAGE vs LOAD (VOUT = 1 .2V, PFM/PWM) 14 FN7605.0 November 8, 2010 ISL9305 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 100 1k VIN = 3.6V VIN = 5.5V VIN = 2.8V EFFICIENCY (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 OUTPUT CURRENT (mA) 1k VIN = 3.6V VIN = 5.5V VIN = 2.8V OUTPUT CURRENT (mA) FIGURE 17. EFFICIENCY vs OUTPUT CURRENT (VOUT = 1.8V, FORCED PWM MODE) FIGURE 18. EFFICIENCY vs OUTPUT CURRENT (VOUT = 1.8V, PFM to PWM) 70 60 RIPPLE REJECTION RATIO (dB) 50 40 30 20 10 PSRR QUIESCENT CURRENT (µA) 58 56 54 52 50 48 46 44 42 10 FREQUENCY (kHz) 100 1000 40 2.5 +25°C +85°C VIN = 3.6V VOUT = 2.6V -40°C VO = 1.2V DCD1 = DCD2 = NO SWITCHING, NO LOAD LDO1 = LDO2 = DISABLED 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 LOAD = 300mA 0 0.1 1 FIGURE 19. RIPPLE REJECTION RATIO vs FREQUENCY FIGURE 20. QUIESCENT CURRENT vs INPUT VOLTAGE 15 FN7605.0 November 8, 2010 ISL9305 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/8/10 REVISION FN7605.0 Initial Release CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL9305 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7605.0 November 8, 2010 ISL9305 Package Outline Drawing L16.4x4G 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/10 4X 1.95 4.00 A B 6 PIN 1 INDEX AREA 13 12X 0.65 16 6 PIN #1 INDEX AREA 1 12 4.00 2 . 10 ± 0 . 10 9 4 (4X) 0.15 8 TOP VIEW 16X 0 . 50 ± 0 . 1 BOTTOM VIEW 5 0.10 M C A B 4 0.30 ± 0.05 SEE DETAIL "X" 0.10 C 0.75 BASE PLANE SEATING PLANE 0.08 C C SIDE VIEW ( 3 . 6 TYP ) ( 2 . 10 ) ( 12X 0 . 65 ) C ( 16X 0 . 30 ) ( 16 X 0 . 70 ) TYPICAL RECOMMENDED LAND PATTERN 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. JEDEC reference drawing: MO220K. 17 FN7605.0 November 8, 2010