HA-2520

® HA-2520, HA-2522, HA-2525 Data Sheet February 16, 2009 FN2894.9 20MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers HA-2520, HA-2522, HA-2525 comprise a series of operational amplifiers delivering an unsurpassed combination of specifications for slew rate, bandwidth and settling time. These dielectrically isolated amplifiers are controlled at close loop gains greater than 3 without external compensation. In addition, these high performance components also provide low offset current and high input impedance. 120V/ms slew rate and 200ns (0.2%) settling time of these amplifiers make them ideal components for pulse amplification and data acquisition designs. These devices are valuable components for RF and video circuitry requiring up to 20MHz gain bandwidth and 2MHz power bandwidth. For accurate signal conditioning designs the HA-2520, HA-2522, HA-2525’s superior dynamic specifications are complemented by 10nA offset current, 100MΩ input impedance and offset trim capability. Features • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 120V/µs • Fast Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200ns • Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . 2MHz • Gain Bandwidth (AV ≥ 3) . . . . . . . . . . . . . . . . . . . . 20MHz • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 100MΩ • Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . .10nA • Compensation Pin for Unity Gain Capability • Pb-Free Available (RoHS Compliant) Applications • Data Acquisition Systems • RF Amplifiers • Video Amplifiers • Signal Generators Ordering Information PART NUMBER HA2-2520-2 HA7-2520-2 HA2-2522-2 HA2-2525-5 HA3-2525-5 HA2-25255ZR5254* (Note 2) HA3-2525-5Z (Note 1) HA7-2525-5 HA9P2525-5 PART MARKING HA2- 2520-2 HA7-2520-2 HA2- 2522-2 HA2- 2525-5 HA3- 2525-5 HA2-252-5ZR5254 TEMP. RANGE (°C) PACKAGE PKG. DWG. NO. Pinouts HA-2520, HA-2525 (8 LD CERDIP, 8 LD PDIP, 8 LD SOIC) TOP VIEW BAL -IN +IN V1 2 3 4 8 COMP V+ OUT BAL -55 to +125 8 Ld Metal Can T8.C -55 to +125 8 Ld CerDIP F8.3A -55 to +125 8 Ld Metal Can T8.C 0 to +75 0 to +75 0 to +75 8 Ld Metal Can T8.C 8 Ld PDIP E8.3 + 7 6 5 8 Ld Metal Can T8.C HA3- 2525-5Z HA7- 2525-5 2525 5 0 to +75 0 to +75 0 to +75 0 to +75 8 Ld PDIP* (Pb-Free) 8 Ld CerDIP 8 Ld SOIC 8 Ld SOIC (Pb-Free) E8.3 F8.3A M8.15 M8.15 BAL 1 HA-2520, HA-2522, HA-2525 (8 LD METAL CAN) TOP VIEW COMP 8 7 V+ HA9P2525-5Z 2525 -5Z (Note 1) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. *Pb-Free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. IN- 2 + 3 4 V5 6 OUT IN+ BAL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2005, 2006, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-2520, HA-2522, HA-2525 Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Thermal Information Thermal Resistance (Typical, Notes 3, 4) θJA (°C/W) θJC (°C/W) Metal Can Package . . . . . . . . . . . . . . . 165 80 PDIP Package* . . . . . . . . . . . . . . . . . . 96 N/A CERDIP Package. . . . . . . . . . . . . . . . . 135 50 SOIC Package . . . . . . . . . . . . . . . . . . . 157 N/A Maximum Junction Temperature (Hermetic Packages) . . . . . +175°C Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range HA-2520/2522-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C HA-2525-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on an evaluation PC board in free air. 4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. VSUPPLY = ±15V HA-2520-2 PARAMETER INPUT CHARACTERISTICS Offset Voltage 25 Full Offset Voltage Drift Bias Current Full 25 Full Offset Current 25 Full Input Resistance (Note 5) Common Mode Range TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Notes 6, 9) Common Mode Rejection Ratio (Note 7) Gain Bandwidth (Notes 5, 8) Minimum Stable Gain OUTPUT CHARACTERISTICS Output Voltage Swing (Note 6) Output Current (Note 9) Full Power Bandwidth (Notes 9, 14) TRANSIENT RESPONSE (AV = +3) Rise Time (Notes 6, 10, 11, 13) Overshoot (Notes 6, 10, 11, 13) 25 25 25 25 50 40 25 25 50 50 25 25 50 50 ns % Full 25 25 ±10.0 ±10 1.5 ±12. 0 ±20 2.0 ±10.0 ±10 1.2 ±12. 0 ±20 2.0 ±10.0 ±10 1.2 ±12. 0 ±20 2.0 V mA MHz 25 Full Full 25 25 10 7.5 80 10 3 15 90 20 7.5 5 74 10 3 15 90 20 -7.5 5 74 10 3 15 90 20 kV/V kV/V dB MHz V/V 25 Full 50 ±10.0 4 20 100 10 100 8 11 200 400 25 50 40 ±10.0 5 25 125 20 100 10 14 250 500 50 100 40 ±10.0 5 30 125 20 100 10 14 250 500 50 100 mV mV µV/°C nA nA nA nA MΩ V TEMP (°C) HA-2522-2 HA-2525-5 MAX (Note 16) UNITS Electrical Specifications MIN MAX MIN MAX MIN (Note 16) TYP (Note 16) (Note 16) TYP (Note 16) (Note 16) TYP 2 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Electrical Specifications VSUPPLY = ±15V (Continued) HA-2520-2 PARAMETER Slew Rate (Notes 6, 10, 13, 15) Settling Time (Notes 6, 10, 13, 15) POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio (Note 11) 25 Full 80 4 90 6 74 4 90 6 74 4 90 6 mA dB TEMP (°C) 25 25 HA-2522-2 HA-2525-5 MAX (Note 16) UNITS V/µs µs MIN MAX MIN MAX MIN (Note 16) TYP (Note 16) (Note 16) TYP (Note 16) (Note 16) TYP ±100 ±12 0 0.20 ±80 ±12 0 0.20 ±80 ±12 0 0.20 NOTES: 5. This parameter value is based on design calculations. 6. RL = 2kΩ. 7. VCM = ±10V. 8. AV > 10. 9. VO = ±10.0V. 10. CL = 50pF. 11. VO = ±200mV. 12. DV = ±5.0V. 13. See Transient Response Test Circuits and Waveforms. Slew Rate 14. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- . 2 π V PEAK 15. VOUT = ±5V. 16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 3 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Test Circuits and Waveforms +1.67V INPUT -1.67V +5V 75% OUTPUT -5V Δt 25% ΔV SLEW RATE = ΔV/Δt ERROR BAND ±10mV FROM FINAL VALUE ±67mV INPUT 0V OVERSHOOT ±200mV 90% OUTPUT 10% 0V RISE TIME SETTLING TIME NOTE: Measured on both positive and negative transitions from 0V to +200mV and 0V to -200mV at the output. FIGURE 1. SLEW RATE AND SETTLING TIME FIGURE 2. TRANSIENT RESPONSE V+ 1F INPUT 667.2Ω 2 7 0.001µF 6 4 1µF 100pF OUTPUT 3+ - IN + OUT 1667Ω V- 0.001µF 2001Ω 5pF 1333Ω 50pF 2N4416 D S G 4999.9Ω SETTLING TIME TEST POINT CR1 CR2 667Ω 2000Ω NOTES: 17. AV = -3. 18. Feedback and summing resistor ratios should be 0.1% matched. 19. Clipping diodes CR1 and CR2 are optional. HP5082-2810 recommended. FIGURE 3. SLEW RATE AND TRANSIENT RESPONSE V+ FIGURE 4. SETTLING TIME TEST CIRCUIT 20kΩ IN BAL. OUT COMP CC V- NOTE: Tested offset adjustment range is |VOS + 1mV| minimum referred to output. Typical ranges are ±20mV with RT = 20kΩ. FIGURE 5. SUGGESTED VOS ADJUSTMENT AND COMPENSATION HOOK-UP 4 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Schematic Diagram OFFSETPIN 1 BAL 1 200 R2AA R21 Q29 R11 R13 Q28 R16 Q27 +INPUT R15 Q1A Q2A Q17 R1A Q18 Q31 Q26 Q25 R6A Q22 R6B Q19 Q20 Q21A Q21B Q5A R3A Q2B Q1B Q11B Q4A Q4B Q16 440 1.8k R2A OFFSET+ BAL 2 200 R2BB R10 440 1.8k R2B Q3B Q15 Q23 R9 Q8 D138 R17 50 Q12B R18 30 D13A Q6 Q9 Q5B R3B Q10 D14 R19 R10 VQ11A Q12A R12 COMP V+ Q30 Q3A C1 1pF OUTPUT R1B Q24 Q7 -INPUT Typical Application Inverting Unity Gain Circuit Figure 6 shows a Compensation Circuit for an inverting unity gain amplifier. The circuit was tested for functionality with supply voltages from ±4V to ±15V, and the performance as tested was: Slew Rate ≈ 120V/µs; Bandwidth ≈ 10MHz; and Settling Time (0.1%) ≈ 500ns. Figure 7 illustrates the amplifier’s frequency response, and it is important to note that capacitance at pin 8 must be minimized for maximum bandwidth. 10k 10k IN 2k 500pF 5k + HA-2520 PHASE SHIFT (DEGREES) 15 10 GAIN (dB) 5 GAIN 0 -5 -10 -15 PHASE 0 -45 -90 -135 -180 10k OUT 100k 1M 10M - FIGURE 7. FREQUENCY RESPONSE FOR INVERTING UNITY GAIN CIRCUIT FIGURE 6. INVERTING UNITY GAIN CIRCUIT 5 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Typical Performance Curves 6 5 OFFSET VOLTAGE (mV) 4 3 2 1 0 -1 -2 -3 -60 BIAS CURRENT (nA) -40 -20 0 20 40 60 80 100 120 VS = ±15V, TA = +25°C, Unless Otherwise Specified -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) FIGURE 9. BIAS CURRENT vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) 40 OFFSET BIAS CURRENT (nA) 30 20 10 0 -10 -20 -30 -60 AVOL (kV/ V) -40 -20 0 20 40 60 80 100 120 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 10. OFFSET CURRENT vs TEMPERATURE (5 TYPICAL UNITS FROM 3 LOTS) 50 FIGURE 11. OPEN LOOP GAIN vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) 14 12 OUTPUT VOLTAGE SWING (±V) 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 RL = 2kΩ 40 OUTPUT CURRENT (±mA) 30 20 10 0 -10 -20 -30 -40 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) FIGURE 12. OUTPUT CURRENT vs SUPPLY VOLTAGE FIGURE 13. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE 6 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Typical Performance Curves VS = ±15V, TA = +25°C, Unless Otherwise Specified (Continued) 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 4 6 8 10 12 SUPPLY VOLTAGE (±V) 14 +125°C GAIN (dB) +25°C -55°C 100 80 60 GAIN AT A = 100 V 40 20 PHASE AT AV = 100 0 0 -45 -90 OPEN LOOP PHASE -135 10M -180 100M OPEN LOOP GAIN PHASE ANGLE (DEGREES) INPUT NOISE CURRENT (pA/√Hz) SUPPLY CURRENT (mA) 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 15. FREQUENCY RESPONSE 100 80 60 40 20 100pF 0 -20 100 300pF 1000 INPUT NOISE VOLTAGE (nV/√Hz) 500 INPUT NOISE CURRENT 100 50 INPUT NOISE VOLTAGE 10 5 100 50 0pF 10pF 30pF 50pF 10 5 1 0.5 1k 10k 100k 1M 10M 100M 1 1 10 100 1k FREQUENCY (Hz) 10k 0.1 100k FREQUENCY (Hz) FIGURE 16. OPEN LOOP FREQUENCY RESPONSE FOR VARIOUS VALUES OF CAPACITORS FROM COMP PIN TO GROUND 35 OUTPUT VOLTAGE SWING (VP-P) 30 25 20 15 10 5 0 10k VSUPPLY = ±10V VSUPPLY = ±15V 1.2 VSUPPLY = ±20V NORMALIZED TO ±15V DATA 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 100k 1M FREQUENCY (Hz) 10M FIGURE 17. INPUT NOISE CHARACTERISTICS RL = 2k Ω CL = 50pF BANDWIDTH NEGATIVE SLEW RATE POSITIVE SLEW RATE 5 7 9 11 13 15 17 19 20 SUPPLY VOLTAGE (±V) FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY FIGURE 19. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE 7 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Die Characteristics SUBSTRATE POTENTIAL: Unbiased TRANSISTOR COUNT: 40 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-2520, HA-2522, HA-2525 COMP V+ OUT BAL BAL -IN +IN V- 8 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Metal Can Packages (Can) REFERENCE PLANE A L L2 L1 A A ØD ØD1 Øe 2 1 Øb1 F Q Øb BASE AND SEATING PLANE BASE METAL LEAD FINISH β N k1 ØD2 T8.C MIL-STD-1835 MACY1-X8 (A1) e1 8 LEAD METAL CAN PACKAGE INCHES SYMBOL A Øb Øb1 Øb2 ØD MIN 0.165 0.016 0.016 0.016 0.335 0.305 0.110 MAX 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS MIN 4.19 0.41 0.41 0.41 8.51 7.75 2.79 MAX 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES 1 1 2 1 1 1 3 3 4 Rev. 0 5/18/94 α k ØD1 C L ØD2 e e1 F k k1 0.200 BSC 0.100 BSC 0.027 0.027 0.500 0.250 0.010 0.040 0.034 0.045 0.750 0.050 0.045 - 5.08 BSC 2.54 BSC 1.02 0.86 1.14 19.05 1.27 1.14 0.69 0.69 12.70 6.35 0.25 Øb1 Øb2 L L1 SECTION A-A L2 Q NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. a is the basic spacing from the centerline of the tab to terminal 1 and b is the basic spacing of each lead or lead position (N -1 places) from a, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. a b N 45° BSC 45° BSC 8 45° BSC 45° BSC 8 9 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90° 8 0.200 0.060 105° 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90° 8 5.08 1.52 105° 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH α aaa bbb ccc M N 10 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E eA eC C -C- e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 11 FN2894.9 February 16, 2009 HA-2520, HA-2522, HA-2525 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8° Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0° 8° 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0° 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN2894.9 February 16, 2009