HA-4741

® HA-4741 Data Sheet July 2004 FN2922.5 Quad, 3.5MHz, Operational Amplifier HA-4741, which contains four amplifiers on a monolithic chip, provides a new measure of performance for general purpose operational amplifiers. Each amplifier in the HA-4741 has operating specifications that equal or exceed those of the 741-type amplifier in all categories of performance. HA-4741 is well suited to applications requiring accurate signal processing by virtue of its low values of input offset voltage (0.5mV), input bias current (60nA) and input voltage noise (9nV/√Hz at 1kHz). 3.5MHz bandwidth, coupled with high open-loop gain, allow the HA-4741 to be used in designs requiring amplification of wide band signals, such as audio amplifiers. Audio application is further enhanced by the HA-4741’s negligible output crossover distortion. These excellent dynamic characteristics also make the HA-4741 ideal for a wide range of active filter designs. Performance integrity of multi-channel designs is assured by a high level of amplifier-to-amplifier isolation (69dB at 10kHz). A wide range of supply voltages (±2V to ±20V) can be used to power the HA-4741, making it compatible with almost any system including battery-powered equipment. HA-4741/883 product and data sheets available upon request. Features • Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6V/µs • Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5MHz • Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . 9nV/√Hz • Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV • Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 60nA • Supply Range. . . . . . . . . . . . . . . . . . . . . . . . ±2V to ±20V • No Crossover Distortion • Standard Quad Pinout Applications • Universal Active Filters • D3 Communications Filters • Audio Amplifiers • Battery-Powered Equipment Pinout HA-4741 (PDIP, CERDIP) TOP VIEW OUT1 1 -IN1 2 +IN1 3 V+ 4 1 + 4 14 OUT4 - 13 -IN4 + 12 +IN4 11 V+ 10 +IN3 2 3 9 -IN3 8 OUT3 Ordering Information PART NUMBER HA1-4741-2 HA3-4741-5 TEMP. RANGE (°C) -55 to 125 0 to 75 PACKAGE PKG. DWG. # +IN2 5 + -IN2 6 OUT2 7 - 14 Ld CERDIP F14.3 14 Ld PDIP E14.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1990, 1993, 1996, 1998. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. HA-4741 Absolute Maximum Ratings TA = 25°C Unless Otherwise Stated Supply Voltage Between V+ and V- Terminals . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Output Short Circuit Duration (Note 3). . . . . . . . . . . . . . . . Indefinite Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) CERDIP Package. . . . . . . . . . . . . . . . . 90 35 PDIP Package . . . . . . . . . . . . . . . . . . . 107 N/A Maximum Junction Temperature (Ceramic Package, Note 1) . . . . 175°C Maximum Junction Temperature (Plastic Packages, Note 1) . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range: HA-4741-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C HA-4741-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for the ceramic package, and below 150°C for the plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. One amplifier may be shorted to ground indefinitely. Electrical Specifications VSUPPLY = ±15V, Unless Otherwise Specified TEST CONDITIONS TEMP. (°C) HA-4741-2 MIN TYP MAX MIN HA-4741-5 TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Offset Voltage 25 Full ±12 - 0.5 4 5 60 15 0.5 9 3 5 200 325 30 75 - ±12 - 1 4 5 60 30 0.5 9 5 6.5 300 400 50 100 - mV mV µV/°C nA nA nA nA V MΩ nV/√Hz Average Offset Voltage Drift Bias Current Full 25 Full Offset Current 25 Full Common Mode Range Differential Input Resistance Input Voltage Noise TRANSFER CHARACTERISTICS Large Signal Voltage Gain VOUT = ±10V, RL = 2kΩ f = 1kHz Full 25 25 25 Full 25 Full 50 25 80 74 66 2.5 100 95 69 3.5 - 25 15 80 74 66 2.5 50 95 69 3.5 - kV/V kV/V dB dB dB MHz Common Mode Rejection Ratio Channel Separation (Note 4) Small Signal Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing Full Power Bandwidth (Notes 5, 6) Output Current Output Resistance VOUT = ±10V RL = 10kΩ RL = 2kΩ 25 25 Full Full 25 Full 25 ±12 ±10 ±5 - ±13.7 ±12.5 25 ±15 300 - ±12 ±10 ±5 - ±13.7 ±12.5 25 ±15 300 - V V kHz mA Ω 2 HA-4741 Electrical Specifications PARAMETER VSUPPLY = ±15V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (°C) HA-4741-2 MIN TYP MAX MIN HA-4741-5 TYP MAX UNITS TRANSIENT RESPONSE RL = 2kΩ, CL = 50pF Rise / Fall Time Overshoot Slew Rate VOUT = ±5V VOUT = 0 to ±200mV 25 25 25 75 25 ±1.6 140 40 75 25 ±1.6 140 40 ns % V/µs POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio NOTES: 4. Referred to input; f = 10kHz, RS = 1kΩ, VIN = 100mVPEAK. 5. VOUT = ±10V, RL = 2kΩ. 6. Full power bandwidth guaranteed based upon slew rate measurement: FPBW = S.R./2π VPEAK. ∆VS = ±5V 25 Full 80 4.5 95 5 80 5 95 7 mA dB Test Circuit and Waveforms + VIN 50pF 2kΩ VOUT FIGURE 1. SMALL AND LARGE SIGNAL TEST CIRCUIT +5V 200mV INPUT -5V +5V OUTPUT 0 -5V Volts = 5V/Div., Time = 5µs/Div. FIGURE 2. LARGE SIGNAL RESPONSE Volts = 40mV/Div., Time = 100ns/Div. FIGURE 3. SMALL SIGNAL RESPONSE 3 HA-4741 Schematic Diagram V+ R1 3K Q1 +VIN Q2 Q3 Q13 R6 80 -VIN Q4 Q5 Q12 R5 30K T1 Q7 Q6 D1 Q8 R2 12.6K Q9 R3 18K R4 20K VQ11 C1 Q10 Q14 Q15 R8 VOUT 150 R7 80 Typical Performance Curves 110 OPEN-LOOP VOLTAGE GAIN (dB) 100 90 80 70 60 50 40 30 20 10 0 -10 1 10 100 PHASE GAIN VSUPPLY = ±15V, TA = 25°C, Unless Otherwise Specified OUTPUT VOLTAGE SWING (VP-P) RL = 2K CL= 50pF 0 PHASE (DEGREES) VO = 28V VO = 18V VO = 8V V O = 2V VS = ±15V VS = ±10V VS = ±5V VS = ±2V 30 10 45 90 135 1.0 0.1 (VOLTAGE FOLLOWER) RL = ∞ CL = 50pF 180 1K 10K 100K FREQUENCY (Hz) 1M 10M 100 1K 10K FREQUENCY (Hz) 100K 1M FIGURE 4. OPEN LOOP FREQUENCY RESPONSE FIGURE 5. OUTPUT VOLTAGE SWING vs FREQUENCY NORMALIZED AC PARAMETERS REFERRED TO VALUE AT ±15V BANDWIDTH 1.0 SLEW RATE BANDWIDTH NORMALIZED VALUE REFERRED TO 25°C 1.1 1.2 1.1 0.9 1.0 BANDWIDTH .9 SLEW RATE 0.8 0.7 0 .8 -55 -25 0 25 50 75 100 125 TEMPERATURE (°C) ±5 ±10 ±15 SUPPLY VOLTAGE (V) ±20 FIGURE 6. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE FIGURE 7. NORMALIZED AC PARAMETERS vs TEMPERATURE 4 HA-4741 Typical Performance Curves 35 INPUT NOISE VOLTAGE (nV/√Hz) 30 25 20 15 10 5 0 10 100 1K FREQUENCY (Hz) 10K CURRENT NOISE VOLTAGE NOISE VSUPPLY = ±15V, TA = 25°C, Unless Otherwise Specified (Continued) 1.4 INPUT NOISE CURRENT (pA/√Hz) PHASE MARGIN (DEGREES) 1.2 1.0 0.8 0.6 0.4 0.2 0 100K 70 RL = 2 K 60 50 40 30 20 10 0 10 100 1000 10,000 LOAD CAPACITANCE (pF) 6 5 4 3 2 1 0 100,000 UNITY GAIN BANDWIDTH (MHz) 125 7 FIGURE 8. INPUT NOISE vs FREQUENCY FIGURE 9. SMALL SIGNAL BANDWIDTH AND PHASE MARGIN vs LOAD CAPACITANCE 30 25 20 15 10 5 0 100 1K 10K LOAD RESISTANCE (Ω) 100K 100 OUTPUT VOLTAGE (VP-P) 80 CURRENT (nA) BIAS CURRENT 60 40 OFFSET CURRENT 20 0 -50 -25 0 25 50 75 100 TEMPERATURE (°C) FIGURE 10. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 11. INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE 200 POWER CONSUMPTION (mW) 160 VS = ±15 120 VS = ±10 80 V S = ±5 40 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 12. POWER CONSUMPTION vs TEMPERATURE 5 HA-4741 Die Characteristics DIE DIMENSIONS: 87 mils x 75 mils x 19 mils 2210µm x 1910µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: 72 PROCESS: Junction Isolated Bipolar/JFET Metallization Mask Layout HA-4741 -IN4 +IN4 V+IN3 -IN3 OUT4 OUT3 OUT1 OUT2 -IN1 +IN1 V+ +IN2 -IN2 6 HA-4741 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 7 HA-4741 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8