HA-4902

HA-4900, HA-4902, HA-4905 Data Sheet October 20, 2005 FN2855.4 Precision Quad Comparators The HA-4900 series are monolithic, quad, precision comparators offering fast response time, low offset voltage, low offset current and virtually no channel-to-channel crosstalk for applications requiring accurate, high speed, signal level detection. These comparators can sense signals at ground level while being operated from either a single +5V supply (digital systems) or from dual supplies (analog networks) up to ±15V. The HA-4900 series contains a unique current driven output stage which can be connected to logic system supplies (VLOGIC+ and VLOGIC-) to make the output levels directly compatible (no external components needed) with any standard logic or special system logic levels. In combination analog/digital systems, the design employed in the HA-4900 series input and output stages prevents troublesome ground coupling of signals between analog and digital portions of the system. These comparators’ combination of features make them ideal components for signal detection and processing in data acquisition systems, test equipment and microprocessor/analog signal interface networks. For military grade product, refer to the HA-4902/883 data sheet. Features • Fast Response Time . . . . . . . . . . . . . . . . . . . . . . . . 130ns • Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0mV • Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . .10nA • Single or Dual Voltage Supply Operation • Selectable Output Logic Levels • Active Pull-Up/Pull-Down Output Circuit. No External Resistors Required • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Threshold Detector • Zero Crossing Detector • Window Detector • Analog Interfaces for Microprocessors • High Stability Oscillators • Logic System Interfaces Ordering Information PART NUMBER HA1-4900-2 HA1-4902-2 PART MARKING HA1-4900-2 HA1-4902-2 HA1-4905-5 HA3-4905-5 HA9P4905-5 TEMP RANGE (oC) PACKAGE PKG. DWG. # Pinout HA-4900, HA-4902 (CERDIP) HA-4905 (PDIP, CERDIP, SOIC) TOP VIEW VL+ OUT 1 -IN 1 +IN 1 V+IN 2 -IN 2 OUT 2 1 2 4 3 4 5 3 6 7 8 + 16 OUT 4 -55 to 125 16 Ld CERDIP F16.3 -55 to 125 16 Ld CERDIP F16.3 0 to 75 0 to 75 0 to 75 0 to 75 16 Ld CERDIP F16.3 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC (Pb-free) E16.3 M16.3 M16.3 HA1-4905-5 HA3-4905-5 HA9P4905-5 + 15 -IN 4 14 +IN 4 13 V+ + 1 12 +IN 3 11 -IN 3 10 OUT 3 9 VL- + HA9P4905-5Z HA9P4905(See Note) 5Z - -2 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-4900, HA-4902, HA-4905 Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 33V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Voltage Between VLOGIC+ and VLOGIC-. . . . . . . . . . . . . . . . . . .18V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Power Dissipation (Notes 1, 2) Thermal Information Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 85 25 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-4900-2, HA-4902-2. . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-4905-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Die Characteristics Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VNumber of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Die Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mils x 105 mils CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175oC for ceramic packages, and below 150oC for plastic packages. 2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and VLOGIC shown in curves of Power Dissipation vs Supply Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For instance, the combination of +15V, -15V, +5V, 0V (V+, V-, VLOGIC+, VLOGIC-) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V, 0V gives a T.P.D. of 450mW. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15V, VLOGIC+ = 5V, VLOGIC- = GND HA-4900-2 -55oC to 125oC MIN TYP MAX HA-4902-2 -55oC to 125oC MIN TYP MAX MIN HA-4905-5 0oC to 75oC TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Offset Voltage (Note 4) TEMP (oC) 25 Full V- 2 10 50 250 3 4 25 35 75 150 VIO + 0.3 VIO + 0.4 (V+) 2.4 - V- 2 10 50 250 5 8 35 45 150 200 VIO + 0.5 VIO + 0.6 (V+) 2.6 - V- 4 25 100 250 7.5 10 50 70 150 300 VIO + 0.5 VIO + 0.7 (V+) 2.4 - mV mV nA nA nA nA mV mV V MΩ Offset Current 25 Full Bias Current (Note 5) 25 Full Input Sensitivity (Note 6) 25 Full Common Mode Range Differential Input Resistance TRANSFER CHARACTERISTICS Large Signal Voltage Gain Response Time (tPD(0)) (Note 7) Response Time (tPD(1)) (Note 7) Full 25 25 25 25 - 400 130 180 200 215 - 400 130 180 200 215 - 400 130 180 200 215 kV/V ns ns 2 HA-4900, HA-4902, HA-4905 Electrical Specifications VSUPPLY = ±15V, VLOGIC+ = 5V, VLOGIC- = GND (Continued) HA-4900-2 -55oC to 125oC MIN TYP MAX HA-4902-2 -55oC to 125oC MIN TYP MAX MIN HA-4905-5 0oC to 75oC TYP MAX UNITS PARAMETER OUTPUT CHARACTERISTICS Output Voltage Level Logic “Low State” (VOL) (Note 8) Logic “High State” (VOH) (Note 8) Output Current ISINK ISOURCE TEMP (oC) Full Full 3.5 0.2 4.2 0.4 - 3.5 0.2 4.2 0.4 - 3.5 0.2 4.2 0.4 - V V Full Full 3.0 3.0 - - 3.0 3.0 - - 3.0 3.0 - - mA mA POWER SUPPLY CHARACTERISTICS Supply Current, IPS (+) Supply Current, IPS (-) Supply Current, IPS (Logic) Supply Voltage Range VLOGIC+ (Note 2) VLOGIC- (Note 2) NOTES: 4. Minimum differential input voltage required to ensure a defined output state. 5. Input bias currents are essentially constant with differential input voltages up to ±9V. With differential input voltages from ±9V to ±15V, bias current on the more negative input can rise to approximately 500µA. This will also cause higher supply currents. 6. VCM = 0V. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This parameter includes the effects of offset voltage and voltage gain. 7. For tPD(1); 100mV input step, -10mV overdrive. For tPD(0); -100mV input step, 10mV overdrive. Frequency ≈ 100Hz; Duty Cycle ≈ 50%; Inverting input driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V. 8. For VOH and VOL: ISINK = ISOURCE = 3.0mA. For other values of VLOGIC; VOH (Min) = VLOGIC + -1.5V. Full Full 0 -15.0 +15.0 0 0 -15.0 +15.0 0 0 -15.0 +15.0 0 V V 25 25 25 6.5 4 3.5 20 8 4 6.5 4 3.5 20 8 4 7 5 3.5 20 8 4 mA mA mA Test Circuit and Waveform +15V +5V OVERDRIVE tPD(0) tPD(1) DUT + INPUT VOUT 100mV VTH = 0V 100mV VTH = 0V -15V OVERDRIVE OUTPUT 1.5V 1.5V tPD(1) tPD(0) t=0 t=0 FIGURE 1. 3 HA-4900, HA-4902, HA-4905 Schematic Diagram R1 500Ω PR1 200kΩ Q1 Q3 D4B D4A Q4C D45 Q7 Q19 Q4 Q5 R16 540Ω +IN BIAS 1 Q18 Q17 Q21 Q22 D35 -IN Q33 Q34 Q30 Q20 Q36 D39 Q37 Q38 Q28 R9 4kΩ R10 4kΩ Q2 Q11 R2 13kΩ Q12 D11A R3 1kΩ Q13 R6 2.5kΩ R4 1kΩ Q14 R7 2.5kΩ R5 360Ω Q15 Q16 Q26 Q23 Q24 Q25 R11 8kΩ R12 Q29A 8kΩ Q29 D29B R24 14kΩ R15 8kΩ Q10 R20D 1kΩ R20C 1kΩ R20B 1kΩ R20A 1kΩ R21 1kΩ MN1 MN3 MN2 R17 19kΩ R14 5kΩ R23 MN5 100Ω Q31 R22 100Ω Q32 OUT MN6 VLOGIC+ V+ R18 664Ω BIAS 2 Q9D BIAS 3 BIAS 4 D9A Q9B Q9A Q9C VLOGICMN4 V- ONE FOURTH ONLY Applying the HA-4900 Series Comparators Supply Connections This device is exceptionally versatile in working with most available power supplies. The voltage applied to the V+ and Vterminals determines the allowable input signal range; while the voltage applied to the VL+ and VL- determines the output swing. In systems where dual analog supplies are available, these would be connected to V+ and V-, while the logic supply and return would be connected to VLOGIC+ and VLOGIC -. The analog and logic supply commons can be connected together at one point in the system, since the comparator is immune to noise on the logic supply ground. A negative output swing may be obtained by connecting VL+ to ground and VL- to a negative supply. Bipolar output swings (15VP-P, Max) may be obtained using dual supplies. In systems where only a single logic supply is available (+5V to 15V), V+ and VLOGIC+ may be connected together to the positive supply while V- and VLOGIC- are grounded. If an input signal could swing negative with respect the V- terminal, a resistor should be connected in series with the input to limit input current to < 5mA since the C-B junction of the input transistor would be forward biased. Power Supply Decoupling Decouple all power supply lines with 0.01µF ceramic capacitors to ground line located near the package to reduce coupling between channels or from external sources. Response Time Fast rise time (