HA-5320

® HA-5320 Data Sheet August 24, 2005 FN2857.7 1 Microsecond Precision Sample and Hold Amplifier The HA-5320 was designed for use in precision, high speed data acquisition systems. The circuit consists of an input transconductance amplifier capable of providing large amounts of charging current, a low leakage analog switch, and an output integrating amplifier. The analog switch sees virtual ground as its load; therefore, charge injection on the hold capacitor is constant over the entire input/output voltage range. The pedestal voltage resulting from this charge injection can be adjusted to zero by use of the offset adjust inputs. The device includes a hold capacitor. However, if improved droop rate is required at the expense of acquisition time, additional hold capacitance may be added externally. This monolithic device is manufactured using the Intersil Dielectric Isolation Process, minimizing stray capacitance and eliminating SCRs. This allows higher speed and latchfree operation. For further information, please see Application Note AN538. Features • Gain, DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x 106 V/V • Acquisition Time . . . . . . . . . . . . . . . . . . . . . .1.0µs (0.01%) • Droop Rate. . . . . . . . . . . . . . . . . . . . . . 0.08µV/µs (25°C) 17µV/µs (Full Temperature) • Aperture Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns • Hold Step Error (See Glossary) . . . . . . . . . . . . . . . . . 5mV • Internal Hold Capacitor • Fully Differential Input • TTL Compatible • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Precision Data Acquisition Systems • Digital to Analog Converter Deglitcher • Auto Zero Circuits • Peak Detector Pinouts HA-5320 (PDIP, CERDIP) TOP VIEW -INPUT 1 +INPUT 2 OFFSET ADJUST 3 OFFSET ADJUST 4 V- 5 SIG. GND 6 OUTPUT 7 14 S/H CONTROL 13 SUPPLY GND 12 NC 11 CEXT 10 NC 9 V+ INTEGRATOR 8 BANDWIDTH Ordering Information PART NUMBER HA1-5320-2 HA1-5320-5 HA3-5320-5 HA9P5320-5 PART MARKING HA1-5320-2 HA1-5320-5 HA3-5320-5 HA9P5320-5 TEMP. RANGE (°C) PACKAGE PKG. DWG. # -55 to 25 14 Ld CERDIP F14.3 0 to 75 0 to 75 0 to 75 0 to 75 14 Ld CERDIP F14.3 14 Ld PDIP 16 Ld SOIC 16 Ld SOIC (Pb-free) E14.3 M16.3 M16.3 HA9P5320-5Z HA9P5320-5Z (Note) HA-5320 (SOIC) TOP VIEW -INPUT 1 +INPUT 2 OFFSET ADJUST 3 OFFSET ADJUST 4 V- 5 SIG. GND 6 OUTPUT 7 NC 8 16 S/H CONTROL 15 SUPPLY GND 14 NC 13 CEXT 12 NC 11 V+ INTEGRATOR 10 BANDWIDTH 9 NC NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-5320 Functional Diagram OFFSET ADJUST 3 4 V+ 9 100pF HA-5320 -INPUT 1 +INPUT 2 + - 7 OUTPUT S/H CONTROL 14 INTEGRATOR BANDWIDTH 13 SUPPLY GND 5 V- 6 SIG. GND 11 CEXT 8 2 FN2857.7 August 24, 2005 HA-5320 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -15V Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . ±20mA Thermal Information Thermal Resistance (Typical, Note 3) θJA (°C/W) θJC (°C/W) CERDIP Package. . . . . . . . . . . . . . . . . 70 18 PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5320-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C HA-5320-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Supply Voltage Range (Typical, Note 2) . . . . . . . . . ±13.5V to ±20V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Internal Power Dissipation may limit Output Current below 20mA. 2. Specification based on a one time characterization. This parameter is not guaranteed. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified TEST CONDITIONS TEMP. (°C) HA-5320-2 MIN TYP MAX MIN HA-5320-5 TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Capacitance Offset Voltage Full 25 25 25 Full ±10 1 ±10 80 - 5 0.2 70 30 90 5 5 2.0 200 200 100 100 15 ±10 1 ±10 72 - 5 0.5 100 30 90 5 5 1.5 300 300 300 300 20 V MΩ pF mV mV nA nA nA nA V dB µV/°C Bias Current 25 Full Offset Current 25 Full Common Mode Range CMRR Offset Voltage Temperature Coefficient TRANSFER CHARACTERISTICS Gain Gain Bandwidth Product (AV = +1, Note 5) OUTPUT CHARACTERISTICS Output Voltage Output Current Full Power Bandwidth Output Resistance Total Output Noise (DC to 10MHz) Note 4 Hold Mode Sample Hold DC, (Note 12) CH = 100pF CH = 1000pF VCM = ±5V Full 25 Full 25 25 25 106 - 2 x 106 2.0 0.18 - 3 x 105 - 2 x 106 2.0 0.18 - V/V MHz MHz Full 25 25 25 25 25 ±10 ±10 - 600 1.0 125 125 200 200 ±10 ±10 - 600 1.0 125 125 200 200 V mA kHz Ω µVRMS µVRMS 3 FN2857.7 August 24, 2005 HA-5320 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (°C) HA-5320-2 MIN TYP MAX MIN HA-5320-5 TYP MAX UNITS PARAMETER TRANSIENT RESPONSE Rise Time Overshoot Slew Rate DIGITAL INPUT CHARACTERISTICS Input Voltage VIH VIL Input Current Note 5 Note 5 Note 6 25 25 25 - 100 15 45 - - 100 15 45 - ns % V/µs Full Full 25 Full 2.0 - - 0.8 4 10 0.1 2.0 - - 0.8 4 10 0.1 V V µA µA µA VIL = 0V VIH = +5V SAMPLE AND HOLD CHARACTERISTICS Acquisition Time (Note 7) To 0.1% To 0.01% Aperture Time (Note 8) Effective Aperture Delay Time Aperture Uncertainty Droop Rate Full 25 25 25 25 25 25 Full -50 - 0.8 1.0 25 -25 0.3 0.08 17 8 1.7 0.5 5 165 2 1.2 1.5 0 0.5 100 50 10 1.1 11 350 - -50 - 0.8 1.0 25 -25 0.3 0.08 1.2 8 0.12 0.5 5 165 2 1.2 1.5 0 0.5 100 50 10 1.1 11 350 - µs µs ns ns ns µV/µs µV/µs pA nA pC mV ns mV Drift Current Note 9 25 Full Charge Transfer Hold Step Error Hold Mode Settling Time Hold Mode Feedthrough POWER SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current Supply Voltage Range Power Supply Rejection Note 9 Note 9 To 0.01% 10VP-P, 100kHz 25 25 Full Full Note 10 Note 10 Note 2 V+, Note 11 V-, Note 11 25 25 ±13.5 11 -11 − - 13 -13 ±20 - ±13.5 80 65 11 -11 - 13 -13 ±20 - mA mA V dB dB Full Full 80 65 NOTES: 4. VO = 20VP-P; RL = 2kΩ; CL = 50pF; unattenuated output. 5. VO = 200mVP-P; RL = 2kΩ; CL = 50pF. 6. VO = 20V Step; RL = 2kΩ; CL = 50pF. 7. VO = 10V Step; RL = 2kΩ; CL = 50pF. 8. Derived from computer simulation only; not tested. 9. VIN = 0V, VIH = +3.5V, tR < 20ns (VIL to VIH). 10. Specified for a zero differential input voltage between +IN and -IN. Supply current will increase with differential input (as may occur in the Hold mode) to approximately ±46mA at 20V. 11. Based on a 1V delta in each supply, i.e. 15V ±0.5VDC. 12. RL = 1kΩ, CL = 30pF. 4 ®Teflon is a registered Trademark of Dupont Corporation. FN2857.7 August 24, 2005 HA-5320 Test Circuits and Waveforms 1 2 S/H CONTROL INPUT 14 -INPUT +INPUT S/H CONTROL HA-5320 (CH = 100pF) OUTPUT 7 8 11 NC NC VO FIGURE 1. CHARGE TRANSFER AND DRIFT CURRENT HOLD (+3.5V) SAMPLE (0V) HOLD (+3.5V) SAMPLE (0V) S/H CONTROL S/H CONTROL VO VO VP ∆t ∆V O NOTES: 13. Observe the “hold step” voltage VP. 14. Compute charge transfer: Q = VPCH. FIGURE 2. CHARGE TRANSFER TEST V+ ANALOG MUX OR SWITCH 1 10VP-P 100kHz SINE WAVE AIN S/H CONTROL INPUT 2 14 -IN +IN S/H CONTROL SUPPLY CEXT GND 13 TO SUPPLY COMMON 11 NC REF COM 6 TO SIGNAL GND HA-5320 9 5 V- NOTES: 15. Observe the voltage “droop”, ∆VO/∆t. 16. Measure the slope of the output during hold, ∆VO/∆t, and compute drift current: ID = CH ∆VO/∆t. FIGURE 3. DRIFT CURRENT TEST V IN NOTE: VOUT OUT INT. COMP. 8 NC 7 Feedthrough in V OUT dB = 20 log -------------V IN where: VOUT = VP-P, Hold Mode, VIN = VP-P. FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION Application Information The HA-5320 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note AN517 for a collection of circuit ideas. Hold Capacitor The HA-5320 includes a 100pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 7 and 11. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. If an external hold capacitor CEXT is used, then a noise bandwidth capacitor of value 0.1CEXT should be connected from pin 8 to ground. Exact value and type are not critical. The hold capacitor CEXT should have high insulation resistance and low dielectric absorption, to minimize droop errors. Polystyrene dielectric is a good choice for operating temperatures up to 85°C. Teflon® and glass dielectrics offer good performance to 125°C and above. FN2857.7 August 24, 2005 Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01µF to 0.1µF, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13. The ideal ground connections are pin 6 (SIG. Ground) directly to the system Signal Ground, and pin 13 (Supply Ground) directly to the system Supply Common. 5 HA-5320 The hold capacitor terminal (pin 11) remains at virtual ground potential. Any PC connection to this terminal should be kept short and “guarded” by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is the interval between the conditions of 10% open and 90% open. Typical Application Figure 5 shows the HA-5320 connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the HA-5320’s hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The application may call for an external hold capacitor CEXT as shown. As mentioned earlier, 0.1CEXT is then recommended at pin 8 to reduce output noise in the Hold mode. The HA-5320 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. Hold Step Error Hold Step Error is the output error due to Charge Transfer (see above). It may be calculated from the specified parameter, Charge Transfer, using the following relationship: Charge Transfer (pC) Hold Step (V) = ----------------------------------------------------------Hold Capacitance (pF) See Performance Curves. Effective Aperture Delay Time (EADT) The difference between the digital delay time from the Hold command to the opening of the S/H switch, and the propagation time from the analog input to the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command. Glossary of Terms Acquisition Time The time required following a “sample” command, for the output to reach its final value within ±0.1% or ±0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. Aperture Uncertainty The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. Drift Current The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula: ∆V I D (pA) = C H ( pF ) × ------- (V/s) ∆t Charge Transfer The small charge transferred to the holding capacitor from the inter-electrode capacitance of the switch when the unit is switched to the HOLD mode. Charge transfer is directly proportional to sample-to-hold offset pedestal error, where: Charge Transfer (pC) = CH (pF) x Hold Step Error (V) OFFSET ADJUST ±15mV 3 1 + VIN S/H CONTROL H S 13 HA-5320 6 8 0.1CEXT SYSTEM POWER GROUND SYSTEM SIGNAL GROUND 2 14 + 10kΩ -15V +15V HI-574A 4 5 9 11 CEXT 100pF 7 13 INPUT CONVERT DIGITAL OUTPUT 5 R/C 9 ANALOG COMMON NOTE: Pin Numbers Refer to DIP Package Only. FIGURE 5. TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE 6 FN2857.7 August 24, 2005 HA-5320 Typical Performance Curves 10 5 ACQUISITION TIME FOR 10V STEP TO +0.01% (µs) 1000 CH = 100pF, INTERNAL IDRIFT (pA) 1.0 0.5 VOLTAGE DROOP DURING HOLD MODE, (mV/100ms) 100 10 0.1 0.05 SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR, (mV) 1 0.01 100 1000 CH VALUE (pF) 10K 100K 0 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 6. TYPICAL SAMPLE AND HOLD PERFORMANCE AS A FUNCTION OF HOLD CAPACITOR FIGURE 7. DRIFT CURRENT vs TEMPERATURE 120 100 80 GAIN (dB) PHASE 60 40 20 0 GAIN (CH = 1100pF) (CH = 100pF) GAIN 90 135 180 0 45 PHASE (DEGREES) 0 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 8. OPEN LOOP GAIN AND PHASE RESPONSE CH = 100pF HOLD STEP VOLTAGE (mV) TA = 25°C 5.0 0.5 0.05 CH = 100pF CH = 1000pF CH = 0.01µF HOLD STEP VOLTAGE 75°C 25°C -10 -8 -6 -4 -2 2 4 6 8 10 2 DC INPUT (V) 3 4 LOGIC LEVEL HIGH (V) 5 FIGURE 9A. HOLD STEP vs INPUT VOLTAGE FIGURE 9B. HOLD STEP vs LOGIC (VIH) VOLTAGE FIGURE 9. TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR 7 FN2857.7 August 24, 2005 HA-5320 Die Characteristics DIE DIMENSIONS: 92 mils x 152 mils x 19 mils METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ TRANSISTOR COUNT: 184 SUBSTRATE POTENTIAL: V- Metallization Mask Layout HA-5320 SUPPLY GND (13) CEXT (11) V+ (9) S/H CTRL (14) -INPUT (1) (8) INT BW (7) OUTPUT +INPUT (2) (3) VIO ADJ (4) VIO ADJ (5) V- (6) SIG GND All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN2857.7 August 24, 2005