HA-5330_04

® HA-5330 Data Sheet June 2004 FN2858.5 650ns Precision Sample and Hold Amplifier The HA-5330 is a very fast sample and hold amplifier designed primarily for use with high speed A/D converters. It utilizes the Intersil Dielectric Isolation process to achieve a 650ns acquisition time to 12-bit accuracy and a droop rate of 0.01µV/µs. The circuit consists of an input transconductance amplifier capable of producing large amounts of charging current, a low leakage analog switch, and an integrating output stage which includes a 90pF hold capacitor. The analog switch operates into a virtual ground, so charge injection on the hold capacitor is constant and independent of VIN. Charge injection is held to a low value by compensation circuits and, if necessary, the resulting 0.5mV hold step error can be adjusted to zero via the Offset Adjust terminals. Compensation is also used to minimize leakage currents which cause voltage droop in the Hold mode. The HA-5330 will operate at reduced supply voltages (to ±10V) with a reduced signal range. The MIL-STD-883 data sheet for this device is available on request. Features • Very Fast Acquisition . . . . . . 500ns (0.1%) 650ns (0.01%) • Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . . . 0.01µV/µs • Very Low Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2mV • High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90V/µs • Wide Supply Range . . . . . . . . . . . . . . . . . . . . . ±10V to ±20V • Internal Hold Capacitor • Fully Differential Input • TTL/CMOS Compatible Applications • Precision Data Acquisition Systems • D/A Converter Deglitching • Auto-Zero Circuits • Peak Detectors Functional Diagram OFFSET ADJUST V+ 10 HA-5330 14 1 8 7 OUT 90pF Ordering Information PART NUMBER HA1-5330-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 14 Ld CERDIP PKG. DWG. # F14.3 3 4 Pinout HA-5330 (CERDIP) TOP VIEW +IN 1 NC 2 OFFSET ADJ. 3 OFFSET ADJ. 4 V5 14 -IN 13 NC 12 SIGNAL GND 11 SUPPLY GND 10 V+ 9 NC 8 S/H CONTROL - IN +IN S/H CONTROL 11 SUPPLY GND 5 V- 12 SIGNAL GND NC 6 OUTPUT 7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. HA-5330 Absolute Maximum Ratings Voltage between V+ and SUPPLY/SIG GND . . . . . . . . . . . . . . .+20V Voltage between V- and SUPPLY/SIG GND . . . . . . . . . . . . . . . -20V Voltage between SUPPLY GND and SIG GND . . . . . . . . . . . . ±2.0V Voltage between S/H Control and SUPPLY/SIG GND . . . . +8V, -6V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . ±17mA Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . ±10V to ±20V Thermal Information Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 66 16 Maximum Junction Temperature (Ceramic Package, Note 2) . . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Internal Power Dissipation may limit Output Current below ±17mA. 2. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175oC for the ceramic package. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER INPUT CHARACTERISTICS Input Voltage Range Input Resistance (Note 4) Input Capacitance Offset Voltage VSUPPLY = ±15V; S/H Control VIL = +0.8V (Sample): VIH = +2.0V (Hold); SIG GND = SUPPLY GND, Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS Full 25 25 25 Full ±10 5 ±10 86 15 3 0.2 1 ±20 20 100 1.5 10 ±300 300 - V MΩ pF mV mV µV/oC nA nA nA nA V dB Offset Voltage Temperature Coefficient Bias Current Full 25 Full Offset Current 25 Full Common Mode Range CMRR TRANSFER CHARACTERISTICS Gain Gain Bandwidth Product OUTPUT CHARACTERISTICS Output Voltage Output Current Full Power Bandwidth (Note 6) Output Resistance Hold Mode Sample Mode Total Output Noise, DC to 4MHz Sample Mode Hold Mode TRANSIENT RESPONSE Rise Time Overshoot Note 5 Note 5 DC Note 12 VCM = ±10V Full Full Full 25 2 x 106 - 2 x 107 4.5 - V/V MHz Full Full 25 25 25 ±10 ±10 - 1.4 0.2 10-5 230 190 0.001 - V mA MHz Ω Ω µVRMS µVRMS 25 - 25 25 - 70 10 - ns % 2 HA-5330 Electrical Specifications PARAMETER Slew Rate DIGITAL INPUT CHARACTERISTICS Input Voltage VIH VIL Input Current VIL = 0V VIH = 5V SAMPLE/HOLD CHARACTERISTICS Acquisition Time To 0.1%, Note 8 25 Full To 0.01%, Note 8 25 Full Aperture Time (Note 4) Effective Aperture Delay Time Aperture Uncertainty Droop Rate (Note 9) 25 25 25 25 Full Hold Step Error Hold Mode Settling Time Hold Mode Feedthrough POWER SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current Power Supply Rejection NOTES: 4. Derived from computer simulation only; not tested. 5. VI = 200mV Step; RL = 2kΩ; CL = 50pF. Slew Rate 6. Full power bandwidth based on slew rate measurement using: FPBW = --------------------------- . Distortion of wave shape occurs beyond 100kHz due 2 π V PEAK to slew rate enhancement circuitry. 7. VO = 20V Step; RL = 2kΩ; CL = 50pF. 8. VO = 10V Step; RL = 2kΩ; CL = 50pF. 9. This parameter is measured at ambient temperature extremes in a high speed test environment. Consequently, steady state heating effects from internal power dissipation are not included. 10. VIN = 0V; VIH = +3.5V; tR = 22ns (VIL to VIH). See graph. 11. Based on a 3V delta in each supply, i.e. 15V ±1.5VDC. 12. VOUT = 200mVP-P, RL = 2kΩ, CL = 50pF. Note 11 Full Full Full 86 18 19 100 24 25 mA mA dB Note 10 To 0.01% 20VP-P, 100kHz 25 25 Full -50 500 650 20 -25 0.1 0.01 0.5 100 -88 700 900 0 10 200 ns ns ns ns ns ns ns µV/µs µV/µs mV ns dB Full Full Full Full 2.0 10 10 0.8 40 40 V V µA µA Note 7 VSUPPLY = ±15V; S/H Control VIL = +0.8V (Sample): VIH = +2.0V (Hold); SIG GND = SUPPLY GND, Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) 25 MIN TYP 90 MAX UNITS V/µs 3 HA-5330 Application Information The HA-5330 has the uncommitted differential inputs of an op amp, allowing the Sample/Hold function to be combined with many conventional op amp circuit ideas. See the Intersil Application Note AN517 for a collection of circuit ideas. Output Stage The HA-5330 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01µF to 0.1µF, ceramic) should be provided from each power supply terminal to the Supply GND Terminal on pin 11. Glossary of Terms Acquisition Time The time required following a “sample” command, for the output to reach its final value within ±0.1% or ±0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. Typical Applications The HA-5330 is configured as a unity gain noninverting amplifier by simply connecting the output (pin 7) to the inverting input (pin 14). As an input device for a fast successive - approximation A/D converter, it offers an extremely high throughput rate. Also, the HA-5330’s pedestal error is adjustable to zero by using an Offset Adjust potentiometer (10K to 50K) center tapped to V-. V10kΩ - 50kΩ 3 4 Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is that interval between the conditions of 10% open and 90% open. Hold Step Error Hold step error is the output shift due to charge transfer from the sample to the hold mode. It is also referred to as “offset step” or “pedestal error”. 3.0 2.0 1.0 0.0 -1.0 -2.0 20 40 60 80 100 RISE TIME (ns) 0V TO 3.5V The ideal ground connections are pin 11 (Supply Ground) directly to the system Supply Common, and pin 12 (Signal Ground) directly to the system Signal Ground (Analog Ground). Hold Capacitor The HA-5330 includes a 90pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on the internal capacitor). MAGNITUDE 40 Effective Aperture Delay Time (EADT) The difference between the digital delay time from the Hold command to the opening of the S/H switch, and the propagation time from the analog input to the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command. PHASE 0 ±15V SUPPLIES -20 90 0 -40 1K 10K 100K ±12V SUPPLIES 1M 180 10M PHASE (DEGREES) MAGNITUDE (dB) 20 Aperture Uncertainty FREQUENCY (Hz) FIGURE 2. MAGNITUDE AND PHASE RESPONSE (CLOSED LOOP GAIN = 100) The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. 4 HOLD STEP ERROR (mV) FIGURE 1. HA-5330 OFFSET ADJUST FIGURE 3. HOLD STEP ERROR vs S/H CONTROL RISE TIME HA-5330 Die Characteristics DIE DIMENSIONS: 99 mils x 166 mils x 19 mils 2510µm x 4210µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (POWERED UP): Signal GND TRANSISTOR COUNT: 205 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5330 +IN -IN SIGNAL GND SUPPLY GND V+ OFFSET ADJ OFFSET ADJ V- OUTPUT S/H CONTROL All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 5