HA-5340

HA-5340 Data Sheet September 1998 File Number 2859.3 700ns, Low Distortion, Precision Sample and Hold Amplifier The HA-5340 combines the advantages of two sample/ hold architectures to create a new generation of monolithic sample/hold. High amplitude, high frequency signals can be sampled with very low distortion being introduced. The combination of exceptionally fast acquisition time and specified/characterized hold mode distortion is an industry first. Additionally, the AC performance is only minimally affected by additional hold capacitance. To achieve this level of performance, the benefits of an integrating output stage have been combined with the advantages of a buffered hold capacitor. To the user this translates to a front-end stage that has high bandwidth due to charging only a small capacitive load and an output stage with constant pedestal error which can be nulled out using the offset adjust pins. Since the performance penalty for additional hold capacitance is low, the designer can further minimize pedestal error and droop rate without sacrificing speed. Low distortion, fast acquisition, and low droop rate are the result, making the HA-5340 the obvious choice for high speed, high accuracy sampling systems. For a Military temperature range version request the HA-5340/883 data sheet. Features • Fast Acquisition Time (0.01%) . . . . . . . . . . . . . . . . . 700ns • Fast Hold Mode Settling Time (0.01%). . . . . . . . . . . . 200n • Low Distortion (Hold Mode) . . . . . . . . . . . . . . . . . . -72dBc (VIN = 200kHz, fS = 450kHz, 5VP-P) • Bandwidth Minimally Affected By External CH • Fully Differential Analog Inputs • Built-In 135pF Hold Capacitor • Pin Compatible with HA-5320 Applications • High Bandwidth Precision Data Acquisition Systems • Inertial Navigation and Guidance Systems • Ultrasonics • SONAR • RADAR Pinouts HA-5340 (PDIP) TOP VIEW Ordering Information PART NUMBER HA3-5340-5 HA9P5340-5 TEMP. RANGE (oC) 0 to 75 0 to 75 PACKAGE 14 Ld PDIP 16 Ld SOIC PKG. NO. E14.3 M16.3 -IN 1 +IN 2 OFFSET ADJ. 3 OFFSET ADJ. 4 V- 5 SIG. GND 6 OUTPUT 7 CHOLD EXTERNAL (OPTIONAL) 14 S/H CONTROL 13 SUPPLY GND 12 NC 11 EXTERNAL HOLD CAP. 10 NC 9 V+ 8 NC Functional Diagram ADJUST OFFSET HA-5340 (SOIC) TOP VIEW -IN 1 +IN 2 OFFSET ADJ. 3 7 OUT OFFSET ADJ. 4 NC 5 V- 6 16 S/H CONTROL 15 SUPPLY GND 14 NC 13 NC EXTERNAL 12 HOLD CAP. 11 NC 10 NC 9 V+ 3 4 11 7 CHOLD 120pF -IN +IN S/H CONTROL 1 2 14 9 V+ 5 V13 6 CCOMP 15pF SIG. GND 7 OUTPUT 8 SUPPLY SIGNAL GND GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-5340 Absolute Maximum Ratings Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -6V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Junction Temperature (Plastic Package, Note 1) . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5340-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . ±12V to ±18V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation must be designed to maintain the junction temperature below 150oC for the plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified HA-5340-5 TEMP. (oC) PARAMETER INPUT CHARACTERISTICS Input Voltage Range Input Resistance (Note 3) Input Capacitance Input Offset Voltage TEST CONDITIONS MIN TYP MAX UNITS Full 25 25 25 Full -10 -10 72 1 ±70 ±50 83 - +10 3 1.5 3.0 30 ±350 ±350 +10 - V MΩ pF mV mV µV/oC nA nA nA nA V dB dB Offset Voltage Temperature Coefficient Bias Current Full 25 Full Offset Current 25 Full Common Mode Range CMRR ±10V, Note 4 Full 25 Full TRANSFER CHARACTERISTICS Gain Gain Bandwidth Product DC CH External = 0pF CH External = 100pF CH External = 1000pF TRANSIENT RESPONSE Rise Time Overshoot Slew Rate DIGITAL INPUT CHARACTERISTICS Input Voltage VIH VIL Input Current VIL = 0V VIH = 5V Full Full Full Full 2.0 7 4 0.8 40 40 V V µA µA 200mV Step 200mV Step 10V Step 25 25 25 40 20 35 60 30 50 ns % V/µs 25 Full Full Full 110 140 10 9.6 6.7 dB MHz MHz MHz 2 HA-5340 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified (Continued) HA-5340-5 PARAMETER OUTPUT CHARACTERISTICS Output Voltage Output Current Full Power Bandwidth (Note 5) Output Resistance Hold Mode Full Full Full 25 Full Total Output Noise DC to 10MHz DISTORTION CHARACTERISTICS SAMPLE MODE Signal to Noise Ratio (RMS Signal to RMS Noise) Total Harmonic Distortion VIN = 200kHz, 20VP-P VIN = 200kHz, 5VP-P VIN = 200kHz, 10VP-P VIN = 200kHz, 20VP-P VIN = 500kHz, 5VP-P Intermodulation Distortion HOLD MODE (50% Duty Cycle S/H) Signal to Noise Ratio (RMS Signal to RMS Noise) fS = 450kHz Total Harmonic Distortion fS = 450kHz VIN = 200kHz, 5VP-P VIN = 200kHz, 10VP-P VIN = 200kHz, 20VP-P fS = 450kHz VIN = 100kHz, 5VP-P VIN = 100kHz, 10VP-P VIN = 100kHz, 20VP-P fS = 2fIN(Nyquist) VIN = 20kHz, 5VP-P VIN = 50kHz, 5VP-P VIN = 100kHz, 5VP-P Intermodulation Distortion fS = 450kHz SAMPLE AND HOLD CHARACTERISTICS Acquisition Time 10V Step to 0.01% 25 Full 10V Step to 0.1% Droop Rate CH = Internal VIL = 0V, VIH = 4.0V, tR = 5ns To ±1mV 20VP-P, 200kHz, Sine 25 25 Full Hold Step Error Hold Mode Settling Time Hold Mode Feedthrough EADT (Effective Aperture Delay Time) Aperture Uncertainty 25 Full Full 25 25 700 430 0.1 15 200 -76 -15 0.2 900 600 95 300 ns ns ns µV/µs µV/µs mV ns dB ns ns VIN = 10VP-P (f1 = 20kHz, f2 = 21kHz) 25 -79 dBc 25 25 25 25 25 25 25 25 25 -72 -66 -56 -84 -71 -61 -95 -91 -82 dBc dBc dBc dBc dBc dBc dBc dBc dBc VIN = 200kHz, 5VP-P VIN = 200kHz, 10VP-P 25 25 76 76 dB dB VIN = 10VP-P, f1 = 20kHz, f2 = 21kHz Full Full Full Full Full Full -90 -76 -70 -66 -78 115 -100 -82 -74 -75 -83 dB dBc dBc dBc dBc dBc Sample Mode Hold Mode 25 25 -10 -10 0.6 0.9 0.05 0.07 325 325 +10 +10 0.1 0.15 400 400 V mA MHz Ω Ω µVRMS µVRMS TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS 3 HA-5340 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified (Continued) HA-5340-5 PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current PSRR NOTES: 3. Derived from Computer Simulation only, not tested. 4. +CMRR is measured from 0V to +10V, -CMRR is measured from 0V to -10V. 5. Based on the calculation FPBW = Slew Rate/2πVPEAK (VPEAK = 10V). 10% Delta Full Full Full 75 19 19 82 25 25 mA mA dB TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS Test Circuits and Waveforms 1 2 S/H CONTROL INPUT 14 -INPUT +INPUT S/H CONTROL HA-5340 (CH = 135pF = INTERNAL) 11 NC 7 OUTPUT VO FIGURE 1. HOLD STEP ERROR AND DROOP RATE S/H CONTROL HOLD (+4.0V) SAMPLE (0V) S/H CONTROL HOLD (+4.0V) SAMPLE (0V) VO ∆t ∆VO VO NOTES: 7. Observe the voltage “droop”, ∆VO/∆t. VP NOTE: 6. Observe the “hold step” voltage VP. FIGURE 2. HOLD STEP ERROR 8. Measure the slope of the output during hold, ∆VO/∆t. 9. Droop can be positive or negative - usually to one rail or the other not to GND. FIGURE 3. DROOP RATE TEST V+ ANALOG MUX OR SWITCH 1 20VP-P 200kHz SINE WAVE AIN S/H CONTROL INPUT 2 -IN +IN SUPPLY GND 13 TO SUPPLY COMMON HA-5340 V- NOTE: 9 5 VOUT OUT REF COM 6 TO SIGNAL GND 7 V IN 10. Feedthrough in V OUT dB = 20 log -------------- where: V IN VOUT = VP-P, Hold Mode, VIN = VP-P 14 S/H CONTROL FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION 4 HA-5340 Application Information The HA-5340 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note AN517 for a collection of circuit ideas. capacitor types offer good performance over the specified operating temperature range. The hold capacitor terminal (pin 11) remains at virtual ground potential. Any PC connection to this terminal should be kept short and “guarded” by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. ®Teflon is a registered Trademark of Dupont Corporation. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01µF to 0.1µF, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13. The ideal ground connections are pin 6 (SIG. GND) directly to the system Signal Ground, and pin 13 (Supply Ground) directly to the system Supply Common. Typical Application Figure 5 shows the HA-5340 connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the HA-5340’s hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The HA-5340 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. Hold Capacitor The HA-5340 includes a 135pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 7 and 11. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. The hold capacitor CH should have high insulation resistance and low dielectric absorption, to minimize droop errors. Teflon®, polystyrene and polypropylene dielectric -15V +15V ≈ ±15mV 50kΩ 3 4 5 9 11 CH OFFSET ADJUST HI - 774 1 VIN 2 15pF 14 HA - 5340 13 6 5 9 R/C ANALOG COMMON CONVERT DIGITAL OUTPUT 120pF 7 13 INPUT S/H CONTROL H S SYSTEM POWER GROUND SYSTEM SIGNAL GROUND NOTE: Pin Numbers Refer to DIP Package Only. FIGURE 5. TYPICAL HA-5340 CONNECTIONS; NONINVERTING UNITY GAIN MODE 5 HA-5340 Typical Performance Curves TA = 25oC, VS = ±15V, Unless Otherwise Specified S/H CONTROL 4V 0V S/H CONTROL 4V 0V 10V 0pF 470pF 0V VOUT VOUT 1000pF 2200pF FIGURE 6. TACQ POS 0 TO +10 STEP FIGURE 7. TACQ vs ADDITIONAL CH 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 1 2300 ACQUISITION TIME TO ±1mV (ns) 2100 1900 1700 1500 1300 1100 900 700 10 100 1000 0 400 800 1200 1600 2000 2400 EXTERNAL HOLD CAPACITANCE (pF) EXTERNAL HOLD CAPACITANCE (pF) DROOP RATE (µV/µs) 125oC 100oC 75oC FIGURE 8. DROOP RATE vs HOLD CAPACITANCE FIGURE 9. ACQUISITION TIME (0.01%) vs HOLD CAPACITANCE 13 12 11 HOLD STEP ERROR (mV) 10 9 8 7 6 5 4 3 2 1 0 5 10 TRISE (ns) 15 20 VIH = 4V VIH = 3V CH = INTERNAL TEMPERATURE = 25oC HOLD STEP ERROR (mV) 20 VIH = 4V CH = 470pF 10 0 -10 -55 -35 -15 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 10. HOLD STEP ERROR vs TRISE FIGURE 11. HOLD STEP ERROR vs TEMPERATURE 6 HA-5340 Typical Performance Curves 14 12 10 8 6 4 VIH = 4V 2 0 200 400 600 800 1000 -10 -55 -35 -15 0 25 50 75 100 125 TRISE = 5ns TA = 25oC HOLD STEP ERROR (mV) TA = 25oC, VS = ±15V, Unless Otherwise Specified 20 (Continued) VIH = 4V, CH = INTERNAL tR = 5ns, 10ns, 20ns HOLD STEP ERROR (mV) 10 5ns 10ns 20ns 0 EXTERNAL HOLD CAPACITANCE (pF) TEMPERATURE (oC) FIGURE 12. HOLD STEP ERROR vs HOLD CAPACITANCE FIGURE 13. HOLD STEP ERROR vs TEMPERATURE MAGNITUDE (dB) 40 MAGNITUDE 180 PHASE ANGLE (DEGREES) MAGNITUDE (dB) 20 90 40 MAGNITUDE 20 CH = 1000pF CH = 470pF CH = 0pF 0 PHASE CH = 1000pF CH = 470pF CH = 0pF 180 PHASE ANGLE (DEGREES) 20 0 PHASE 0 90 -90 AV = +100, ±15V AND ±12V SUPPLIES (NOTE) 1K 10K 100K 1M 10M 0 -180 -90 NOTE: ±15V and ±12V supplies trace the same line within the width of the line, therefore only one line is shown. FIGURE 14. CLOSED LOOP PHASE/GAIN AV = +100 1M 10M -180 1K 10K 100K FIGURE 15. CLOSED LOOP PHASE/GAIN -20 -20 fSAMPLE ≅ 450kHz VOUT = 5VP-P HA-5320 SAMPLE AND HOLD MODES THD (dBc) -40 THD (dBc) -40 HA-5320 SAMPLE AND HOLD MODES -60 -60 HA-5340 HOLD MODE HA-5340 HOLD MODE -80 HA-5340 SAMPLE MODE -100 0 100K 200K 300K 400K 500K FREQUENCY (Hz) -80 HA-5340 SAMPLE MODE -100 5 VOUT P-P 10 at 200kHz, fSAMPLE ≅ 450kHz FIGURE 16. THD vs FREQUENCY FIGURE 17. THD vs VOUT 7 HA-5340 Die Characteristics DIE DIMENSIONS: 84mils x 139mils x 19mils METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kÅ ± 2.0kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 196 Metallization Mask Layout HA-5340 (11) EXTERNAL HOLD CAP SUPPLY (13) GND S/H (14) CONTROL -IN (1) (9) +VSUPPLY (7) OUTPUT (7) OUTPUT +IN (2) (6) SIG GND OFFSET ADJ (3) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com OFFSET ADJ (4) 8 -VSUPPLY (5)