HA3-2542-5

HA-2542 Data Sheet October 1999 File Number 2899.3 70MHz, High Slew Rate, High Output Current Operational Amplifier The HA-2542 is a wideband, high slew rate, monolithic operational amplifier featuring an outstanding combination of speed, bandwidth, and output drive capability. Utilizing the advantages of the Intersil D.I. technology this amplifier offers 350V/µs slew rate, 70MHz gain bandwidth, and ±100mA output current. Application of this device is further enhanced through stable operation down to closed loop gains of 2. For additional flexibility, offset null and frequency compensation controls are included in the HA-2542 pinout. The capabilities of the HA-2542 are ideally suited for high speed coaxial cable driver circuits where low gain and high output drive requirements are necessary. With 5.5MHz full power bandwidth, this amplifier is most suitable for high frequency signal conditioning circuits and pulse video amplifiers. Other applications utilizing the HA-2542 advantages include wideband amplifiers and fast samplehold circuits. For more information on the HA-2542, please refer to Application Note AN552 (Using the HA-2542), or Application Note AN556 (Thermal Safe-Operating-Areas for High Current Op Amps). For a lower power version of this product, please see the HA-2842 data sheet. Features • Stable at Gains of 2 or Greater • Gain Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 70MHz • High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 300V/µs (Min) • High Output Current . . . . . . . . . . . . . . . . . . . 100mA (Min) • Power Bandwidth . . . . . . . . . . . . . . . . . . . . . 5.5MHz (Typ) • Output Voltage Swing . . . . . . . . . . . . . . . . . . . ±10V (Min) • Monolithic Bipolar Dielectric Isolation Construction Applications • Pulse and Video Amplifiers • Wideband Amplifiers • Coaxial Cable Drivers • Fast Sample-Hold Circuits • High Frequency Signal Conditioning Circuits Pinout HA-2542 (PDIP, CERDIP) TOP VIEW NC 1 NC 2 BAL 3 14 NC 13 BAL 12 COMP + 11 V+ 10 OUT 9 NC 8 NC Ordering Information PART NUMBER HA1-2542-5 HA3-2542-5 TEMP. RANGE (oC) 0 to 75 0 to 75 PACKAGE 14 Ld CERDIP 14 Ld PDIP PKG. NO. F14.3 E14.3 -IN 4 +IN 5 V- 6 NC 7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-2542 Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . .35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Output Current . . . . . . . . . . . . . . . . 50mA Continuous, 125mAPEAK Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Junction Temperature (Note 1, Hermetic Packages) . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Range HA-2542-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175oC for ceramic packages, and below 150oC for plastic packages. By using Application Note AN556 on Safe Operating Area equations, along with the thermal resistances, proper load conditions can be determined. Heatsinking will be required in many applications. See the “Application Information” section to determine if heat sinking is required for your application. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15V, RL = 1kΩ, CL ≤ 10pF, Unless Otherwise Specified HA-2542-5 0oC TO 75oC MIN TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Offset Voltage TEST CONDITIONS TEMP. (oC) 25 Full ±10 - 5 8 14 15 26 45 1 100 1 2.2 10 3 10 20 35 50 7 9 - mV mV µV/oC µA µA nA/oC µA µA kΩ pF V µVP-P nV/√Hz pA/√Hz Average Offset Voltage Drift Bias Current Full 25 Full Average Bias Current Drift Offset Current Full 25 Full Input Resistance Input Capacitance Common Mode Range Input Noise Voltage Input Noise Density Input Noise Current Density TRANSFER CHARACTERISTICS Large Signal Voltage Gain VO = ±10V 0.1Hz to 100Hz f = 1kHz, RG = 0Ω f = 1kHz, RG = 0Ω 25 25 Full 25 25 25 25 Full 10 5 70 2 - 30 20 100 70 - kV/V kV/V dB V/V MHz Common Mode Rejection Ratio Minimum Stable Gain Gain Bandwidth Product OUTPUT CHARACTERISTICS Output Voltage Swing Output Current (Note 3) Output Resistance VCM = ±10V Full 25 AV = 100 25 Full 25 25 ±10 100 - ±11 5 - V mA Ω 2 HA-2542 Electrical Specifications VSUPPLY = ±15V, RL = 1kΩ, CL ≤ 10pF, Unless Otherwise Specified (Continued) HA-2542-5 0oC TO 75oC MIN 4.7 TYP 5.5 0.1 0.2 50mA (e.g. ≤50% duty cycle for 100mA). Slew Rate 4. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- . 2 π V PEAK 5. Differential gain and phase are measured at 5MHz with a 1V differential input voltage. 6. Refer to Test Circuits section of this data sheet. 7. VIN = 1VRMS; f = 10kHz; AV = 10. VS = ±5V to ±15V Full 70 30 31 79 40 mA mA dB Test Circuits and Waveforms IN + - OUT 500Ω 500Ω VIN NOTES: 8. VS = ±15V. 9. AV = +2. 10. CL ≤ 10pF. Vertical Scale: VIN = 2.0V/Div., VOUT = 5.0V/Div. Horizontal Scale: 200ns/Div. VOUT TEST CIRCUIT LARGE SIGNAL RESPONSE 3 HA-2542 Test Circuits and Waveforms (Continued) VIN VOUT Vertical Scale: 100mV/Div. Horizontal Scale: 50ns/Div. Vertical Scale: 100mV/Div. Horizontal Scale: 10ns/Div. VS = ±15V, RL = 1kΩ. Propagation delay variance is negligible over full temperature range. PROPAGATION DELAY NOTES: SETTLING POINT SMALL SIGNAL RESPONSE 11. AV = -2. 12. Feedback and summing resistors must be matched (0.1%). 13. HP5082-2810 clipping diodes recommended. 14. Tektronix P6201 FET probe used at settling point. 15. For 0.01% settling time, heat sinking is suggested to reduce thermal effects and an analog ground plane with supply decoupling is suggested to minimize ground loop errors. 2.5kΩ 5kΩ 1kΩ 500Ω VIN + V+ - VOUT V- SETTLING TIME TEST CIRCUIT (SEE NOTES 11 - 15.) Schematic Diagram BAL R11 R7 R8 R9 QP14 R10 75Ω R25 5kΩ QP34 R12 75Ω QP16 BAL R26 5kΩ QP35 R15 QP15 QP13 QP33 R14 QN12 QP31 QP11 QN23 QP5 QP7 QP32 QN42 QN44 R18 DZ45 +IN QN1 R6 QN2 -IN C1 QP36 QN COMP QN18 4 HA-2542 Application Information (Refer to Application Note AN552 for Further Information) The Intersil HA-2542 is a state of the art monolithic device which also approaches the “ALL-IN-ONE” amplifier concept. This device features an outstanding set of AC parameters augmented by excellent output drive capability providing for suitable application in both high speed and high output drive circuits. Primarily intended to be used in balanced 50Ω and 75Ω coaxial cable systems as a driver, the HA-2542 could also be used as a power booster in audio systems as well as a power amp in power supply circuits. This device would also be suitable as a small DC motor driver. The applications shown in Figures 2 through Figure 4 demonstrate the HA-2542 at gains of +100 and +2 and as a video cable driver for small signals. Power Dissipation Considerations At high output currents, especially with the PDIP package, care must be taken to ensure that the Maximum Junction Temperature (TJ, see “Absolute Maximum Ratings” table) is not exceeded. As an example consider the HA-2542 in the PDIP package, with a required output current of 20mA at VOUT = 5V. The power dissipation is the quiescent power (1.2W = 30V x 40mA) plus the power dissipated in the output stage (POUT = 200mW = 20mA x (15V - 5V)), or a total of 1.4W. The thermal resistance (θJA) of the PDIP package is 100oC/W, which increases the junction temperature by 140oC over the ambient temperature (TA). Remaining below TJMAX requires that TA be restricted to ≤ 10oC (150oC - 140oC). Heatsinking would be required for operation at ambient temperatures greater than 10oC. Note that the problem isn’t as severe with the CERDIP package due to it’s lower thermal resistance, and higher TJMAX. Nevertheless, it is recommended that Figure 1 be used to ensure that heat sinking is not required. MAXIMUM TA WITHOUT HEATSINK (oC) 120 100 80 60 40 20 0 0 5 10 15 20 25 30 35 40 45 OUTPUT CURRENT (100% DUTY CYCLE, mA) 50 VOUT = ±5V VS = ±15V CERDIP PDIP FIGURE 1. MAXIMUM OPERATING TEMPERATURE vs OUTPUT CURRENT Allowable output power can be increased by decreasing the quiescent dissipation via lower supply voltages. For more information please refer to Application Note AN556, “Thermal Safe Operating Areas for High Current Op Amps”. Prototyping Guidelines For best overall performance in any application, it is recommended that high frequency layout techniques be used. This should include: 1) mounting the device through a ground plane: 2) connecting unused pins (NC) to the ground: 3) mounting feedback components on Teflon standoffs and or locating these components as close to the device as possible: 4) placing power supply decoupling capacitors from device supply pins to ground. 5 HA-2542 Frequency Compensation The HA-2542 may be externally compensated with a single capacitor to ground. This provides the user the additional flexibility in tailoring the frequency response of the amplifier. A guideline to the response is demonstrated on the typical performance curve showing the normalized AC parameters versus compensation capacitance. It is suggested that the user check and tailor the accurate compensation value for each application. As shown additional phase margin is achieved at the loss of slew rate and bandwidth. For example, for a voltage gain of +2 (or -1) and a load of 500pF/2kΩ, 20pF is needed for compensation to give a small signal bandwidth of 30MHz with 40o of phase margin. If a full power output voltage of ±10V is needed, this same configuration will provide a bandwidth of 5MHz and a slew rate of 200V/µs. If maximum bandwidth is desired and no compensation is needed, care must be given to minimize parasitic capacitance at the compensation pin. In some cases where minimum gain applications are desired, bending up or totally removing this pin may be the solution. In this case, care must also be given to minimize load capacitance. For wideband positive unity gain applications, the HA-2542 can also be over-compensated with capacitance greater than 30pF to achieve bandwidths of around 25MHz. This over-compensation will also improve capacitive load handling or lower the noise bandwidth. This versatility along with the ±100mA output current makes the HA-2542 an excellent high speed driver for many power applications. Typical Applications 40 GAIN (dB) 30 20 10 0 OUT 990Ω 10Ω -45 -90 -135 -180 PHASE (DEGREES) PHASE (DEGREES) 0 IN + - Frequency (0dB) = 44.9MHz, Phase Margin (0dB) = 40o FREQUENCY RESPONSE FIGURE 2. NONINVERTING CIRCUIT (AVCL = 100) 8 GAIN (dB) 6 4 2 0 50Ω 0 -45 -90 -135 -180 IN + - OUT 50Ω Frequency (dB) = 56MHz, Phase Margin (3dB) = 40o FREQUENCY RESPONSE FIGURE 3. NONINVERTING CIRCUIT (AVCL = 2) 6 HA-2542 Typical Applications (Continued) IN + 75Ω OUT 1kΩ 1kΩ 75Ω IN - OUT 1V/Div.; 100ns/Div. PULSE RESPONSE FIGURE 4. VIDEO CABLE DRIVER (AVCL = 2) 1 RT 2 3 4 5 6 7 14 13 12 NOTES: 16. Suggested compensation scheme 5pF - 20pF. CCOMP V+ + 11 10 9 8 17. Tested Offset Adjustment Range is |VOS +1mV| minimum referred to output. 18. Typical range is ±20mV with RT = 5kΩ. FIGURE 5. SUGGESTED OFFSET VOLTAGE ADJUSTMENT AND FREQUENCY COMPENSATION 7 HA-2542 Typical Performance Curves 1000 INPUT NOISE VOLTAGE (nV/√Hz) 1000 INPUT NOISE CURRENT (pA/√Hz) 10 8 OFFSET VOLTAGE (mV) 6 4 2 0 -2 -4 -6 -8 1 1 10 100 1K 10K FREQUENCY (Hz) 1 100K -10 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) VS = ±12V SIX REPRESENTATIVE UNITS 100 100 INPUT NOISE VOLTAGE 10 INPUT NOISE CURRENT 10 FIGURE 6. INPUT NOISE VOLTAGE AND INPUT NOISE CURRENT vs FREQUENCY FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE TA = 25oC VS = ±15V 100K INPUT RESISTANCE (Ω) BIAS CURRENT (µA) 29 27 25 23 21 19 17 15 13 11 9 VS = ±12V SIX REPRESENTATIVE UNITS 10K V+ 1000 + V100 900Ω 100Ω 10 100K 1M 10M FREQUENCY (Hz) 100M 7 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 8. INPUT RESISTANCE vs FREQUENCY FIGURE 9. BIAS CURRENT vs TEMPERATURE 18 17 16 BIAS CURRENT (µA) 15 14 (dB) 13 12 11 10 9 8 7 5 7 9 11 SUPPLY VOLTAGE (±V) 13 15 TA = 25oC SIX REPRESENTATIVE UNITS 120 VS = ±15V 110 CMRR 100 90 80 PSRR 70 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 10. BIAS CURRENT vs SUPPLY VOLTAGE FIGURE 11. PSRR AND CMRR vs TEMPERATURE 8 HA-2542 Typical Performance Curves 32 30 SUPPLY CURRENT (mA) 28 26 24 (dB) 22 20 18 25oC 16 14 12 4 6 8 10 12 SUPPLY VOLTAGE (±V) 14 125oC 100 1K 10K 100K 1M 10M -55oC 120 100 +PSRR 80 60 40 20 0 -PSRR CMRR (Continued) VS = ±15V TA = 25oC RL = 2kΩ FREQUENCY (Hz) FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE, AT VARIOUS TEMPERATURES FIGURE 13. PSRR AND CMRR vs FREQUENCY 500 RL = 100Ω 400 SLEW RATE (V/µs) AV = 2 AV = 2 300 ±15V ±10V AVOL (kV/V) 55 50 45 40 35 30 25 20 15 125 10 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 120 VS = ± 8 VS = ±7 VS = ±12 VS = ±15 200 AV = 10 100 AV = 10 0 -50 -25 0 AV = 2 ±5V ±15V AV = 10 ±10V ±5V 25 50 75 TEMPERATURE (oC) 100 FIGURE 14. SLEW RATE vs TEMPERATURE AT VARIOUS SUPPLY VOLTAGES FIGURE 15. OPEN LOOP GAIN vs TEMPERATURE, AT VARIOUS SUPPLY VOLTAGES 12.0 OUTPUT VOLTAGE SWING (V) 25oC +VOUT NORMALIZED TO VALUE AT 0pF 10.0 -55oC 8.0 +VOUT 6.0 4.0 2.0 0.0 -2.0 -4.0 -6.0 -8.0 25oC -VOUT 125oC -VOUT 9 11 SUPPLY VOLTAGE (±V) 13 15 125oC +VOUT 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 5 10 15 20 COMPENSATION CAPACITANCE (pF) 25 BANDWIDTH SLEW RATE PHASE MARGIN -10.0 -55oC -12.0 -VOUT -14.0 5 7 FIGURE 16. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE, AT VARIOUS TEMPERATURES FIGURE 17. NORMALIZED AC PARAMETERS vs COMPENSATION CAPACITANCE 9 HA-2542 Typical Performance Curves (Continued) 12 OUTPUT VOLTAGE (V) 10 8 6 4 2 0 0.1 1 10 FREQUENCY (Hz) RL = 100Ω MAXIMUM SWING UNDISTORTED SWING OUTPUT VOLTAGE (V) HA-2542 AV = 10 VS = ±15V TA = 25oC MAXIMUM SWING RL = 1kΩ UNDISTORTED SWING 12 10 8 6 4 2 RL = 100Ω MAXIMUM SWING UNDISTORTED SWING HA-2542 AV = 10 VS = ±10V TA = 25oC RL = 1kΩ MAXIMUM SWING UNDISTORTED SWING 100 0 0.1 1 FREQUENCY (Hz) 10 100 FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY FIGURE 19. OUTPUT VOLTAGE SWING vs FREQUENCY 70 60 50 GAIN (dB) 40 30 20 10 0 0.1 AV = 10 AV = 100 AV = 1000 GAIN (dB) HA-2542 TA = 25oC RL = 1kΩ VS = ±15V 12 9 6 3 0 VIN + VV+ PHASE GAIN 25oC 125oC -55oC 0 -45 -90 -135 -180 100M PHASE (DEGREES) -55oC 25oC GAIN = +2 500Ω VS = ±8V RL = 1kΩ 500Ω CL ≤ 10pF VIN ≤ 90mV 125oC 1M 10M FREQUENCY (Hz) AV = 2 1 10 FREQUENCY (MHz) 100 100K FIGURE 20. FREQUENCY RESPONSE CURVES FIGURE 21. HA-2542 CLOSED LOOP GAIN vs TEMPERATURE 10 HA-2542 Die Characteristics DIE DIMENSIONS: 106 mils x 73 mils x 19 mils 2700µm x 1850µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: 43 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-2542 -IN +IN BAL BAL V- OUTPUT V+ COMP 11 HA-2542 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 12 HA-2542 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 13