HA3-5114-5

HA-5102, HA-5104, HA-5114 Data Sheet April 1999 File Number 2925.4 Dual and Quad, 8MHz and 60MHz, Low Noise Operational Amplifiers Low noise and high performance are key words describing HA-5102, HA-5104 and HA-5114. These general purpose amplifiers offer an array of dynamic specifications ranging from a 3V/µs slew rate and 8MHz bandwidth (5102/04) to 20V/µs slew rate and 60MHz gain-bandwidth-product (HA-5114). Complementing these outstanding parameters is a very low noise specification of 4.3nV/√Hz at 1kHz. Fabricated using the Intersil high frequency DI process, these operational amplifiers also offer excellent input specifications such as a 0.5mV offset voltage and 30nA offset current. Complementing these specifications are 108dB open loop gain and 60dB channel separation. Consuming a very modest amount of power (90mW/ package for duals and 150mW/package for quads), HA5102/04/14 also provide 15mA of output current. This impressive combination of features make this series of amplifiers ideally suited for designs ranging from audio amplifiers and active filters to the most demanding signal conditioning and instrumentation circuits. These operational amplifiers are available in dual or quad form with industry standard pinouts allowing for immediate interchangeability with most other dual and quad operational amplifiers. HA-5102 HA-5114 Dual, Comp. HA-5104 Quad, Uncomp. Quad, Comp. Features • Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/√Hz • Bandwidth. . . . . . . . . . . . . . . . . . . . 8MHz (Compensated) 60MHz (Uncompensated) • Slew Rate . . . . . . . . . . . . . . . . . . . . 3V/µs (Compensated) 20V/µs (Uncompensated) • Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV • Available in Duals or Quads Applications • • • • • • High Q, Active Filters Audio Amplifiers Instrumentation Amplifiers Integrators Signal Generators For Further Design Ideas, See Application Note AN554 Pinouts HA-5102 (PDIP, CERDIP) TOP VIEW OUT1 1 -IN1 2 +IN1 3 V- 4 8 V+ + + 7 OUT2 6 -IN2 5 +IN2 Refer to the /883 data sheet for military product. HA-5104 (PDIP, CERDIP) HA-5114 (PDIP) TOP VIEW OUT1 1 -IN1 2 1 4 14 OUT4 Ordering Information PART NUMBER HA3-5102-5 HA7-5102-2 HA1-5104-2 HA1-5104-5 HA3-5104-5 HA9P5104-9 HA3-5114-5 HA9P5114-9 TEMP. RANGE (oC) 0 to 75 -55 to 125 -55 to 125 0 to 75 0 to 75 -40 to 85 0 to 75 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld CERDIP 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 16 Ld SOIC 14 Ld PDIP 16 Ld SOIC PKG. NO E8.3 F8.3A F14.3 F14.3 E14.3 M16.3 E14.3 M16.3 + + 13 -IN4 12 +IN4 11 V- +IN1 3 V+ 4 +IN2 5 -IN2 6 OUT2 7 + - + - 10 +IN3 9 -IN3 8 OUT3 2 3 HA5104/5114 (SOIC) TOP VIEW OUT1 1 -IN1 2 +IN1 3 V+ 4 +IN2 5 -IN2 6 OUT2 7 NC 8 + 16 OUT4 1 + 4 + 15 -IN4 14 +IN4 13 V+ 12 +IN3 11 -IN3 10 OUT3 9 NC - 2 3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-5102, HA-5104, HA-5114 Absolute Maximum Ratings Supply Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Output Short Circuit Duration (Note 3). . . . . . . . . . . . . . . . Indefinite Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) 8 Lead PDIP Package . . . . . . . . . . . . . 92 N/A 8 Lead CERDIP Package. . . . . . . . . . . 135 50 14 Lead CERDIP Package. . . . . . . . . . 80 30 14 Lead PDIP Package . . . . . . . . . . . . 86 N/A SOIC Package (HA-5104, HA-5114) . . 96 N/A Maximum Junction Temperature (Note 1, Hermetic Package) . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5102/5104-2 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-5102/5104/5114-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HA-5104/5114-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175oC for hermetic packages, and below 150oC for plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. Any one amplifier may be shorted to ground indefinitely. Electrical Specifications VSUPPLY = ±15V, Unless Otherwise Specified HA-5102-2, -5 MIN TYP MAX HA-5104-2, -5 HA-5114 -5 MIN TYP MAX MIN HA-5104-9 HA-5114-9 TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Offset Voltage TEMP. (oC) 25 Full ±12 0.5 3 130 30 500 - 2.0 2.5 200 325 75 125 - ±12 0.5 3 130 30 500 - 2.5 3.0 200 325 75 125 - ±12 0.5 3 130 30 500 - 2.5 3.0 200 500 75 125 - mV mV µV/oC nA nA nA nA kΩ V Offset Voltage Average Drift Bias Current Full 25 Full Offset Current 25 Full Input Resistance Common Mode Range TRANSFER CHARACTERISTICS Large Signal Voltage Gain, (VOUT = ±5V, RL = 2kΩ) Common Mode Rejection Ratio (VCM = ±5.0V) Small Signal Bandwidth, HA-5102/5104 (AV = 1) Gain Bandwidth Product, HA-5114 (AV = 10) Channel Separation (Note 4) OUTPUT CHARACTERISTICS Output Voltage Swing (RL = 10kΩ) (RL = 2kΩ) Output Current, (VOUT = ±5V) Full Power Bandwidth (Note 5) HA-5102/5104 HA-5114 25 Full 25 Full Full 25 25 25 100 100 86 - 250 95 8 60 60 - 100 100 86 - 250 95 8 60 60 - 80 80 80 - 250 95 8 60 60 - kV/V kV/V dB MHz MHz dB Full Full Full 25 25 ±12 ±10 ±10 16 191 ±13 ±12 ±15 47 318 - ±12 ±10 ±10 16 191 ±13 ±12 ±15 47 318 - ±12 ±10 ±7 16 191 ±13 ±12 ±15 47 318 - V V mA kHz kHz 2 HA-5102, HA-5104, HA-5114 Electrical Specifications VSUPPLY = ±15V, Unless Otherwise Specified (Continued) HA-5102-2, -5 MIN TYP 110 MAX HA-5104-2, -5 HA-5114 -5 MIN TYP 110 MAX MIN HA-5104-9 HA-5114-9 TYP 110 MAX UNITS Ω PARAMETER Output Resistance STABILITY Minimum Stable Closed Loop Gain HA-5102/5104 HA-5114 TEMP. (oC) 25 Full Full 1 10 - - 1 10 - - 1 10 - - V/V V/V TRANSIENT RESPONSE (Note 6) Rise Time HA-5102/5104 HA-5114 Overshoot HA-5102/5104 HA-5114 Slew Rate HA-5102/5104 HA-5114 Settling Time (Note 7) HA-5102/5104 HA-5114 NOISE CHARACTERISTICS (Note 8) Input Noise Voltage f = 10Hz f = 1kHz Input Noise Current f = 10Hz f = 1kHz Broadband Noise Voltage f = DC to 30kHz 25 25 25 25 25 9 4.3 5.1 0.57 870 25 6.0 15 3 9 4.3 5.1 0.57 870 25 6.0 15 3 9 4.3 5.1 0.57 870 25 6.0 15 3 nV/√Hz nV/√Hz pA/√Hz pA/√Hz nVRMS 25 25 25 25 25 25 25 25 1 12 108 48 20 30 3 20 4.5 0.6 200 100 35 40 1 12 108 48 20 30 3 20 4.5 0.6 200 100 35 40 1 12 108 48 20 30 3 20 4.5 0.6 200 100 35 40 ns ns % % V/µs V/µs µs µs POWER SUPPLY CHARACTERISTICS Supply Current (All Amps) Power Supply Rejection Ratio, (∆VS = ±5V) NOTES: 4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = 10kHz; VIN = 100mVPEAK; RS = 1kΩ . Slew Rate 5. Full power bandwidth is guaranteed by equation: Full power bandwidth = ---------------------------- . 2 π V PEAK 6. Refer to Test Circuits section of the data sheet. 7. Settling time is measured to 0.1% of final value for a 1V input step, and AV = -10 for HA-5114, and a 10V input step, AV = -1 for HA-5102/5104. 8. The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-lot variation. 25 Full 86 3.0 100 5.0 86 5.0 100 6.5 80 5.0 100 6.5 mA dB 3 HA-5102, HA-5104, HA-5114 Test Circuits and Waveforms HA-5102, HA-5104 2kΩ 2kΩ IN + 1kΩ 50pF OUT IN + 2kΩ 50pF OUTPUT +5V INPUT 0V -5V 200mV INPUT +5V OUTPUT 0V -5V 0V Vertical = 5V/Div., Horizontal = 5µs/Div. (AV = -1) FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT HA-5114 Vertical = 40mV/Div., Horizontal = 50ns/Div. (AV = +1) FIGURE 2. SMALL SIGNAL RESPONSE CIRCUIT +0.5V OUTPUT 0V INPUT -0.5V +5V 0V OUTPUT -5V INPUT 0V 200mV Input = 0.5V/Div., Output = 5V/Div., Time = 500ns/Div. Input = 10mV/Div., Output = 50mV/Div., Time = 50ns/Div. 4 HA-5102, HA-5104, HA-5114 Test Circuits and Waveforms (Continued) +15V 2N4416 IN + TO OSCILLOSCOPE 1.8kΩ 50pF OUT 5kΩ 500Ω (NOTE 9) 5kΩ 2kΩ +15V + 200Ω VIN 200Ω (NOTE 9) 2kΩ 2kΩ VOUT -15V 50pF NOTES: 9. AV = -1 (HA-5102/5104), AV = -10 (HA-5114). 10. Feedback and summing resistors should be 0.1% matched. NOTE: AV = +10. 11. Clipping diodes are optional, HP5082-2810 recommended. FIGURE 4. SETTLING TIME CIRCUIT FIGURE 3. LARGE AND SMALL SIGNAL RESPONSE CIRCUIT (AV = +10) Simplified Schematic V+ OUTPUT V+INPUT -INPUT 5 HA-5102, HA-5104, HA-5114 Typical Performance Curves 15 VS = ±15V, TA = 25oC HIGH 10 TYPICAL LOW 5 NOISE CURRENT (pA/√Hz) 10 5.0 VS = ±15V, TA = 25oC NOISE VOLTAGE (nV/√Hz) 1.0 0.5 0 10 100 FREQUENCY (Hz) 1K 0.1 10 100 FREQUENCY (Hz) 1K FIGURE 5. INPUT NOISE VOLTAGE DENSITY FIGURE 6. INPUT NOISE CURRENT DENSITY VS = ±15V, TA = 25oC, 50µV/Div., 1s/Div., AV = 1000V/V Input Noise = 0.232µVP-P FIGURE 7. 0.1Hz TO 10Hz NOISE 2.0 VS = ±15V INPUT OFFSET VOLTAGE (mV) 1.5 OFFSET VOLTAGE (mV) VS = ±15V, TA = 25oC, 500µV/Div., 1s/Div., AV = 1000V/V Total Output Noise = 2.075µVP-P FIGURE 8. 0.1Hz TO 1MHz NOISE 2.0 TA = 25oC 1.5 1.0 1.0 0.5 0.5 0 -60 0 -40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 18 TEMPERATURE (oC) SUPPLY VOLTAGE (±V) FIGURE 9. VIO vs TEMPERATURE FIGURE 10. VIO vs VS 6 HA-5102, HA-5104, HA-5114 Typical Performance Curves 4 2 VS = ±15V 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -60 -40 -20 (Continued) 100 90 INPUT BIAS CURRENT (nA) 80 70 60 50 40 30 20 10 0 20 40 60 80 100 120 VS = ±15V INPUT OFFSET CURRENT (nA) 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 11. IIO vs TEMPERATURE 5 TOTAL SUPPLY CURRENT (mA) 5 TOTAL SUPPLY CURRENT (mA) FIGURE 12. IBIAS vs TEMPERATURE VS = ±15V, IOUT = 0 TA = 25oC, IOUT = 0 4 4 3 3 2 2 1 1 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) 0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±V) FIGURE 13. ICC vs TEMPERATURE (HA-5104/14) 5 OPEN LOOP VOLTAGE GAIN (105V/V) FIGURE 14. ICC vs VS (HA-5102) OPEN LOOP VOLTAGE GAIN (105V/V) VS = ±15V, ∆VO = ±10V, RL = 2kΩ 5.5 5.0 VO = ±10V, VS = ±15V 125oC 4 25oC 4.0 3 2 3.0 -55oC 1 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) 2.0 1K 2K 4K 6K 8K 10K LOAD RESISTANCE (Ω) FIGURE 15. AVOL vs TEMPERATURE FIGURE 16. AVOL vs LOAD RESISTANCE 7 HA-5102, HA-5104, HA-5114 Typical Performance Curves 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 140 130 0 TA = 25oC, RL = 2kΩ MAX OUTPUT SWING (±V) (Continued) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TA = 25oC, RL = 2kΩ OPEN LOOP GAIN (kV/V) 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) FIGURE 17. AVOL vs VS FIGURE 18. VOUT vs VS 45 VS = ±15V, TA = 25oC 0 OUTPUT CURRENT (mA) 40 -20 35 CMRR (dB) 350 400 450 VOUT = -15V -40 30 VOUT = +15V 25 -60 -80 20 0 50 100 150 200 250 300 TIME (SECONDS) -100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 19. OUTPUT SHORT CIRCUIT CURRENT vs TIME FIGURE 20. CMRR vs FREQUENCY 0 POWER SUPPLY REJECTION (dB) 6 VS = ±15V, RL = 2kΩ, CL = 50pF 225 -55oC PHASE SHIFT (DEGREES) GAIN 135 -20 VOLTAGE GAIN (dB) 0 -3 -6 125oC GAIN -40 +PSRR -PSRR -80 45 0 -60 -12 -45 125oC PHASE -55oC PHASE -135 -18 -100 1K 10K 100K 1M -24 10K 100K 1M FREQUENCY (Hz) 10M -225 40M FREQUENCY (Hz) FIGURE 21. PSRR vs FREQUENCY FIGURE 22. HA-5104/02 UNITY GAIN FREQUENCY RESPONSE 8 HA-5102, HA-5104, HA-5114 Typical Performance Curves 25 20 15 VOLTAGE GAIN (dB) 10 5 0 -5 -10 -15 -20 -25 100 1K 10K 100K 1M 10M PHASE 0 45 90 135 180 100M GAIN PHASE SHIFT (DEGREES) (Continued) VOLTAGE GAIN (dB) AVCL = +10, TA = 25oC, RL = 2kΩ, CL = 50pF 120 100 80 60 PHASE SHIFT (DEGREES) 40 HA-5102/5104 GAIN 20 0 VS = ±15V, TA = 25oC, RL = 2kΩ , CL = 50pF HA-5114 GAIN HA-5114 PHASE 0 45 90 HA-5102/5104 PHASE 100 1K 10K 100K 1M 10M 135 180 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 23. HA-5114 FREQUENCY RESPONSE FIGURE 24. OPEN LOOP GAIN vs FREQUENCY 60 50 OVERSHOOT (%) 40 30 20 10 VS = ±15V, TA = 25oC, RL = 2kΩ SLEW RATE (NORMALIZED) 1.1 RL = 2kΩ, CL = 50pF, VS = ±15V 1.0 0.9 0.8 0.7 0 10 100 1K 10K LOAD CAPACITANCE (pF) 0.6 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 25. SMALL SIGNAL OVERSHOOT vs CLOAD FIGURE 26. SLEW RATE vs TEMPERATURE 1.1 RL = 2kΩ, CL = 50pF, VS = ±15V RISE TIME (NORMALIZED) 1.0 0.9 0.8 0.7 0.6 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 27. RISE TIME vs TEMPERATURE 9 HA-5102, HA-5104, HA-5114 Die Characteristics DIE DIMENSIONS: 98.4 mils x 67.3 mils x 19 mils 2500µm x 1710µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 93 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5102 V+IN1 -IN1 OUT1 +IN2 -IN2 OUT2 V+ 10 HA-5102, HA-5104, HA-5114 Die Characteristics DIE DIMENSIONS: 95 mils x 99 mils x 19 mils 2420µm x 2530µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 175 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5104 +IN2 V+ +IN1 -IN2 -IN1 OUT2 OUT3 OUT1 OUT4 -IN3 -IN4 +IN3 V- +IN4 HA-5114 +IN2 V+ +IN1 -IN2 -IN1 OUT2 OUT3 OUT1 OUT4 -IN3 -IN4 +IN3 V- +IN4 11 HA-5102, HA-5104, HA-5114 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 12 HA-5102, HA-5104, HA-5114 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 13 HA-5102, HA-5104, HA-5114 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH α aaa bbb ccc M N 14 HA-5102, HA-5104, HA-5114 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 15 HA-5102, HA-5104, HA-5114 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 A1 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.394 0.010 0.016 16 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 16 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 16