HFA1110_06

® HFA1110 Data Sheet June 6, 2006 FN2944.8 750MHz, Low Distortion Unity Gain, Closed Loop Buffer The HFA1110 is a unity gain closed loop buffer that achieves -3dB bandwidth of 750MHz, while offering excellent video performance and low distortion. Manufactured on Intersil’s proprietary complementary bipolar UHF-1 process, the HFA1110 also offers very fast slew rate, and high output current. It is one more example of Intersil’s intent to enhance its leadership position in products for high speed signal processing applications. The HFA1110’s settling time of 11ns to 0.1%, low distortion and ability to drive capacitive loads make it an ideal flash A/D driver. The HFA1110 is an enhanced, pin compatible upgrade for the AD9620, AD9630, CLC110, EL2072, BUF600 and BUF601. For buffer applications requiring a standard op amp pinout, or selectable gain (-1, +1, +2), see the HFA1112 data sheet. For output limiting see the HFA1113 data sheet. For military grade product please refer to the HFA1110/883 data sheet. Features • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 750MHz • Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1300V/µs • Fast Settling Time (0.2%). . . . . . . . . . . . . . . . . . . . . . 7ns • High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA • Fixed Gain of +1 • Gain Flatness (100MHz) . . . . . . . . . . . . . . . . . . . . 0.03dB • Differential Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025° • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04% • 3rd Harmonic Distortion (50MHz). . . . . . . . . . . . . . -80dBc • 3rd Order Intercept (100MHz) . . . . . . . . . . . . . . . . 30dBm • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Video Switching and Routing • RF/IF Processors • Driving Flash A/D Converters • High-Speed Communications Pinout HFA1110 (SOIC) TOP VIEW V+ OPT V+ NC IN 1 2 3 4 -+ 8 7 6 5 OUT NC OPT V- • Impedance Transformation • Line Driving • Radar Systems Ordering Information PART NUMBER HFA1110IB PART TEMP. MARKING RANGE (°C) PACKAGE 1110IB 1110IBZ -40 to 85 -40 to 85 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # M8.15 M8.15 V- HFA1110IBZ (Note) Pin Descriptions NAME V+ Opt V+ NC IN VOpt VNC OUT PIN NUMBER 1 2 3 4 5 6 7 8 DESCRIPTION Positive Supply Optional Positive Supply No Connection Input Negative Supply Optional Negative Supply No Connection Output HFA1110EVAL High Speed Buffer DIP Evaluation Board NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HFA1110 Absolute Maximum Ratings Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER INPUT CHARACTERISTICS Output Offset Voltage (Note 2) VSUPPLY = ±5V, RL = 100Ω, Unless Otherwise Specified TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS 25 Full 39 35 25 - 8 10 45 14 51 10 50 2 25 35 40 65 - mV mV µV/°C dB dB nV/√Hz pA/√Hz µA µA kΩ pF Output Offset Voltage Drift PSRR Full 25 Full Input Noise Voltage (Note 2) Input Noise Current (Note 2) Input Bias Current (Note 2) 100kHz 100kHz 25 25 25 Full Input Resistance Input Capacitance TRANSFER CHARACTERISTICS Gain VOUT = 2VP-P ±2V Full Scale 25 25 25 Full 0.980 0.975 - 0.990 0.003 1.02 1.025 - V/V V/V % ±V ±V mA mA ±V mA mA DC Non-Linearity (Note 2) OUTPUT CHARACTERISTICS Output Voltage (Note 2) 25 25 Full R L = 5 0Ω 3.0 2.5 50 35 3.3 3.0 60 50 - Output Current (Note 2) 25, 85 -40 POWER SUPPLY CHARACTERISTICS Supply Voltage Range Supply Current (Note 2) Full 25 Full AC CHARACTERISTICS -3dB Bandwidth (Note 2) Slew Rate Full Power Bandwidth (Note 2) Gain Flatness (Note 2) VOUT = 0.2VP-P VOUT = 5VP-P VOUT = 4VP-P To 100MHz To 30MHz Linear Phase Deviation (Note 2) 2nd Harmonic Distortion (Note 2) 3rd Harmonic Distortion (Note 2) 3rd Order Intercept (Note 2) DC to 100MHz 50MHz, VOUT = 2VP-P 50MHz, VOUT = 2VP-P 100MHz 25 25 25 25 25 25 25 25 25 750 1300 150 ±0.03 ±0.01 ±0.3 4.5 - 21 - 5.5 26 33 - MHz V/µs MHz dB dB ° dBc dBc dBm -60 -80 30 2 FN2944.8 June 6, 2006 HFA1110 Electrical Specifications PARAMETER -1dB Gain Compression Reverse Gain (S12, Note 2) TRANSIENT RESPONSE Rise Time Overshoot (Note 2) 0.2% Settling Time (Note 2) 0.1% Settling Time (Note 2) Overdrive Recovery Time Differential Gain Differential Phase NOTE: 2. See Typical Performance Curves for more information. 3.58MHz, RL = 75Ω 3.58MHz, RL = 75Ω VOUT = 0.5V Step VOUT = 1.0V Step, Input Signal Rise/Fall = 1ns VOUT = 1V to 0V VOUT = 1V to 0V 25 25 25 25 25 25 25 0.5 2.5 7 11 15 0.04 0.025 ns % ns ns ns % ° VSUPPLY = ±5V, RL = 100Ω, Unless Otherwise Specified (Continued) TEST CONDITIONS 100MHz 100MHz, VOUT = 1VP-P TEMP (°C) 25 25 MIN TYP 14 -60 MAX UNITS dBm dB Application Information PC Board Layout The frequency performance of this amplifier depends a great deal on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value chip (0.1µF) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and may cause oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output. See the “Recommended RS vs Load Capacitance” graph for specific recommendations. An example of a good high frequency layout is the Evaluation Board shown below. 50Ω +5V 0.1µF 10µF 1 2 3 IN 50Ω 4 HFA1110 8 7 6 5 10µF -5V 0.1µF RS OUT SCHEMATIC DIAGRAM BOTTOM LAYOUT Evaluation Board An evaluation board is available for the HFA1110 (part number HFA1110EVAL). Please contact your local sales office for information. The layout and schematic of the board are shown here: NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics Part Number 08-350000-10. 1 TOP LAYOUT 3 FN2944.8 June 6, 2006 HFA1110 Typical Performance Curves VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 OUTPUT VOLTAGE (V) 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 TIME (5ns/DIV) TIME (5ns/DIV) FIGURE 1. SMALL SIGNAL PULSE RESPONSE FIGURE 2. LARGE SIGNAL PULSE RESPONSE 2 1 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 -8 0 200M 400M 600M 800M 1G FREQUENCY (Hz) 1M 10M PHASE VOUT = 200mVP-P GAIN VOUT = 200mVP-P VOUT = 1VP-P 6 GAIN (dB) 0 -45 PHASE (°) -90 -135 -180 -225 -270 RL = 1 kΩ 100M 3 0 -3 -6 0 PHASE (°) -90 -180 -270 -360 1G RL = 5 0Ω RL = 1 kΩ RL = 100Ω FREQUENCY (Hz) FIGURE 3. FREQUENCY RESPONSE FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS 2 1 BANDWIDTH (MHz) 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 -8 1M 10M 100M FREQUENCY (Hz) 1G VOUT = 200mVP-P VOUT = 2.5VP-P VOUT = 4VP-P 890 870 850 830 810 790 770 750 730 710 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (°C) FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FIGURE 6. -3dB BANDWIDTH vs TEMPERATURE 4 FN2944.8 June 6, 2006 HFA1110 Typical Performance Curves 0.25 0.20 0.15 DEVIATION (°) GAIN (dB) 0.10 0.05 0 -0.05 -0.10 VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 1M 10M FREQUENCY (Hz) 100M 200M 0 15M 30M 45M 60M 75M 90M 105M 120M 135M 150M FREQUENCY (Hz) FIGURE 7. GAIN FLATNESS FIGURE 8. DEVIATION FROM LINEAR PHASE 50 -20 +135 INTERCEPT POINT (dBm) 40 GAIN (dB) PHASE -40 GAIN +45 PHASE (°) -30 +90 30 20 -50 0 10 -60 0 200M 400M VOUT = 1VP-P 600M 800M 1G 0 0 50M 100M 150M 200M 250M 300M 350M 400M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 9. REVERSE GAIN AND PHASE (S12) FIGURE 10. TWO-TONE, THIRD ORDER INTERMODULATION INTERCEPT -30 -40 100MHz DISTORTION (dBc) DISTORTION (dBc) -50 -60 -70 -80 -90 -100 50MHz 30MHz -30 -40 -50 -60 -70 -80 -90 -100 -5 -3 -1 1 3 5 7 9 11 13 -5 -3 -1 1 3 5 7 9 11 13 OUTPUT POWER (dBm) OUTPUT POWER (dBm) 50MHz 30MHz 100MHz FIGURE 11. SECOND HARMONIC DISTORTION vs POUT FIGURE 12. THIRD HARMONIC DISTORTION vs POUT 5 FN2944.8 June 6, 2006 HFA1110 Typical Performance Curves VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) VOUT = 1V 0.8 0.4 0.2 0 -0.2 -0.4 -0.8 50 45 40 35 30 25 20 15 10 5 0 SETTLING ERROR (%) RS ( Ω ) 0 40 80 120 160 200 CL (pF) 240 280 320 360 -5 0 5 10 15 20 25 30 35 40 45 TIME (ns) FIGURE 13. SETTLING RESPONSE FIGURE 14. RECOMMENDED SERIES OUTPUT RESISTOR vs CLOAD 21 18 OVERSHOOT (%) 15 12 9 6 VO = 0.5VP-P 3 0 200 VO = 2.0VP-P VO = 1.0VP-P ERROR (%) 0.04 0.02 RL = 200Ω RL = 100Ω RL = 1k Ω 0 -0.02 300 400 500 600 700 800 900 1000 -0.04 -3.0 -2.0 INPUT RISE TIME (ps) -1.0 0 1.0 INPUT VOLTAGE (V) 2.0 3.0 FIGURE 15. OVERSHOOT vs INPUT RISETIME FIGURE 16. INTEGRAL LINEARITY ERROR 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 6 7 8 9 10 TOTAL SUPPLY VOLTAGE (V+ - V-, V) 25 24 SUPPLY CURRENT (mA) 23 22 21 20 19 18 17 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) SUPPLY CURRENT (mA) FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 18. SUPPLY CURRENT vs TEMPERATURE 6 FN2944.8 June 6, 2006 HFA1110 Typical Performance Curves 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 -60 VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 10 OUTPUT OFFSET VOLTAGE (mV) 9.8 9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8 7.8 -60 -40 -20 0 20 40 60 80 100 120 BIAS CURRENT (µA) -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 19. BIAS CURRENT vs TEMPERATURE FIGURE 20. OFFSET VOLTAGE vs TEMPERATURE 3.8 3.7 NOISE VOLTAGE (nV/√Hz) 100 200 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 -60 +VOUT (RL = 100Ω) +VOUT (RL = 50Ω) 60 120 |-VOUT |(RL = 100Ω) |-VOUT |(RL = 50Ω) 40 INI 20 ENI 80 40 -40 -20 0 20 40 60 80 100 120 0 100 1k 10k 0 100k TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 22. INPUT NOISE vs FREQUENCY 7 FN2944.8 June 6, 2006 NOISE CURRENT (pA/√Hz) OUTPUT VOLTAGE (V) 3.6 80 160 HFA1110 Die Characteristics DIE DIMENSIONS: 63 mils x 44 mils x 19 mils 1600µm x 1130µm x 483µm METALLIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AlCu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ PASSIVATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-) Metallization Mask Layout HFA1110 NC IN V- NC NC NC NC V+ OUT 8 FN2944.8 June 6, 2006 HFA1110 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN2944.8 June 6, 2006