HFA1145

® HFA1145 Data Sheet June 1, 2006 FN3955.5 330MHz, Low Power, Current Feedback Video Operational Amplifier with Output Disable The HFA1145 is a high speed, low power current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 process. This amplifier features a TTL/CMOS compatible disable control, pin 8, which when pulled low reduces the supply current and forces the output into a high impedance state. This allows easy implementation of simple, low power video switching and routing systems. Component and composite video systems also benefit from this op amp’s excellent gain flatness, and good differential gain and phase specifications. Multiplexed A/D applications will also find the HFA1145 useful as the A/D driver/multiplexer. The HFA1145 is a low power, high performance upgrade for the CLC410. For Military grade product, please refer to the HFA1145/883 data sheet. Features • Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 5.8mA • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 330MHz • Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 1000V/μs • Gain Flatness (to 75MHz) . . . . . . . . . . . . . . . . . . ±0.1dB • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% • Differential Phase . . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • Output Enable/Disable Time . . . . . . . . . . . . . 180ns/35ns • Pin Compatible Upgrade for CLC410 • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Flash A/D Drivers • Video Switching and Routing • Professional Video Processing • Video Digitizing Boards/Systems • Multimedia Systems Ordering Information PART NUMBER (BRAND) HFA1145IB HFA1145IBZ (Note) HFA1145IP HFA1145IPZ (Note) PART MARKING 1145IB 1145IBZ HFA1145IP HFA1145IPZ TEMP. RANGE (°C) PACKAGE PKG. DWG. # M8.15 M8.15 E8.3 E8.3 • RGB Preamps • Medical Imaging • Hand Held and Miniaturized RF Equipment • Battery Powered Communications -40 to 85 8 Ld SOIC -40 to 85 8 Ld SOIC (Pb-free) -40 to 85 8 Ld PDIP -40 to 85 8 Ld PDIP* (Pb-free) Pinout HFA1145 (SOIC) TOP VIEW NC 1 -IN 2 +IN 3 V- 4 8 DISABLE HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps Note: Requires a SOIC-to-DIP adapter. See “Evaluation Board” section inside. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. + 7 V+ 6 OUT 5 NC 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HFA1145 Absolute Maximum Ratings Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Output Current (Note 1) . . . . . . . . . . . . . . . . . Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>600V Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Die Only) . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (NOTE 3) TEST LEVEL PARAMETER INPUT CHARACTERISTICS Input Offset Voltage TEST CONDITIONS TEMP. (°C) MIN TYP MAX UNITS A A 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 47 45 45 50 47 47 0.8 0.5 0.5 - 2 3 1 50 48 48 54 50 50 6 10 5 0.5 0.8 0.8 1.2 0.8 0.8 2 5 60 3 4 4 5 8 10 15 25 60 1 3 3 7.5 15 200 6 8 8 mV mV μV/°C dB dB dB dB dB dB μA μA nA/°C μA/V μA/V μA/V MΩ MΩ MΩ μA μA nA/°C μA/V μA/V μA/V Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio ΔVCM = ±1.8V ΔVCM = ±1.8V ΔVCM = ±1.2V Input Offset Voltage Power Supply Rejection Ratio ΔVPS = ±1.8V ΔVPS = ±1.8V ΔVPS = ±1.2V Non-Inverting Input Bias Current B A A A A A A A A Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity ΔVPS = ±1.8V ΔVPS = ±1.8V ΔVPS = ±1.2V Non-Inverting Input Resistance ΔVCM = ±1.8V ΔVCM = ±1.8V ΔVCM = ±1.2V Inverting Input Bias Current B A A A A A A A A Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity ΔVCM = ±1.8V ΔVCM = ±1.8V ΔVCM = ±1.2V B A A A 2 FN3955.5 June 1, 2006 HFA1145 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL A A A C C A A f = 100kHz f = 100kHz f = 100kHz B B B PARAMETER Inverting Input Bias Current Power Supply Sensitivity TEST CONDITIONS ΔVPS = ±1.8V ΔVPS = ±1.8V ΔVPS = ±1.2V TEMP. (°C) 25 85 -40 25 25 25, 85 -40 25 25 25 MIN ±1.8 ±1.2 - TYP 2 4 4 60 1.6 ±2.4 ±1.7 3.5 2.5 20 MAX 5 8 8 - UNITS μA/V μA/V μA/V Ω pF V V nV/√Hz pA/√Hz pA/√Hz Inverting Input Resistance Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) Input Noise Voltage Density (Note 6) Non-Inverting Input Noise Current Density (Note 6) Inverting Input Noise Current Density (Note 6) TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Note 6) AV = -1 C 25 - 500 - kΩ RF = 510Ω, Unless Otherwise Specified AV = +1, +RS = 510Ω B B AV = -1, RF = 425Ω AV = +2 AV = +10, RF = 180Ω AV = +1, +RS = 510Ω AV = -1 AV = +2 B B B B B 25 Full 25 25 Full 25 Full 25 25 25 25 Full 25 Full 25 25 Full 270 240 300 330 260 130 90 135 140 115 ±0.03 ±0.04 ±0.11 ±0.22 ±0.03 ±0.09 1 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz dB dB dB dB dB dB V/V Full Power Bandwidth (VOUT = 5VP-P at AV = +2/-1, 4VP-P at AV = +1, Note 6) Gain Flatness (AV = +2, VOUT = 0.2VP-P, Note 6) B B B B B To 25MHz To 75MHz B B Gain Flatness To 25MHz (AV = +1, +RS = 510Ω, VOUT = 0.2VP-P, Note 6) To 75MHz Minimum Stable gain OUTPUT CHARACTERISTICS AV = +2, RF = 510Ω, Unless Otherwise Specified Output Voltage Swing (Note 6) Output Current (Note 6) Output Short Circuit Current Closed Loop Output Impedance (Note 6) DC AV = -1, RL = 100Ω B B A A A 25 Full 25, 85 -40 25 25 ±3 ±2.8 50 28 - ±3.4 ±3 60 42 90 0.08 - V V mA mA mA Ω AV = -1, RL = 50Ω A A B B 3 FN3955.5 June 1, 2006 HFA1145 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL B B B B B PARAMETER Second Harmonic Distortion (VOUT = 2VP-P, Note 6) Third Harmonic Distortion (VOUT = 2VP-P, Note 6) Reverse Isolation (S12, Note 6) TRANSIENT CHARACTERISTICS Rise and Fall Times TEST CONDITIONS 10MHz 20MHz 10MHz 20MHz 30MHz TEMP. (°C) 25 25 25 25 25 MIN - TYP -48 -44 -50 -45 -55 MAX - UNITS dBc dBc dBc dBc dB AV = +2, RF = 510Ω, Unless Otherwise Specified VOUT = 0.5VP-P B B 25 Full 25 25 25 25 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 25 25 25 1.1 1.4 3 5 3 11 1000 975 650 580 1400 1200 800 700 2100 1900 1000 900 15 23 30 8.5 ns ns % % % % V/μs V/μs V/μs V/μs V/μs V/μs V/μs V/μs V/μs V/μs V/μs V/μs ns ns ns ns Overshoot (Note 4) (VOUT = 0 to 0.5V, VIN tRISE = 1ns) Overshoot (Note 4) (VOUT = 0.5VP-P, VIN tRISE = 1ns) Slew Rate (VOUT = 4VP-P, AV = +1, +RS = 510Ω) +OS -OS +OS -OS +SR B B B B B B -SR (Note 5) B B Slew Rate (VOUT = 5VP-P, AV = +2) +SR B B -SR (Note 5) B B Slew Rate (VOUT = 5VP-P, AV = -1) +SR B B -SR (Note 5) B B Settling Time (VOUT = +2V to 0V step, Note 6) To 0.1% To 0.05% To 0.02% B B B B Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz) Differential Phase (f = 3.58MHz) DISABLE CHARACTERISTICS Disabled Supply Current DISABLE Input Logic Low DISABLE Input Logic High VIN = ±2V AV = +2, RF = 510Ω, Unless Otherwise Specified RL = 150Ω RL = 75Ω RL = 150Ω RL = 75Ω B B B B 25 25 25 25 - 0.02 0.03 0.03 0.05 - % % Degrees Degrees VDISABLE = 0V A A A A Full Full 25, 85 -40 Full 2.0 2.4 - 3 100 4 0.8 200 mA V V V μA DISABLE Input Logic Low Current VDISABLE = 0V A 4 FN3955.5 June 1, 2006 HFA1145 Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL A B B B 2V, A B B ± PARAMETER DISABLE Input Logic High Current Output Disable Time (Note 6) Output Enable Time (Note 6) Disabled Output Capacitance Disabled Output Leakage Off Isolation (VDISABLE = 0V, VIN = 1VP-P, Note 6) POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 6) TEST CONDITIONS VDISABLE = 5V VIN = ±1V, VDISABLE = 2.4V to 0V VIN = ±1V, VDISABLE = 0V to 2.4V VDISABLE = 0V VDISABLE = 0V, VIN = VOUT = ±3V At 5MHz At 25MHz TEMP. (°C) Full 25 25 25 Full 25 25 MIN - TYP 1 35 180 2.5 3 -75 -60 MAX 15 10 - UNITS μA ns ns pF μA dB dB C A A 25 25 Full ±4.5 - 5.8 5.9 ±5.5 6.1 6.3 V mA mA NOTES: 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. Undershoot dominates for output signal swings below GND (e.g. 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0 to 0.5V condition. See the “Application Information” section for details. 5. Slew rates are asymmetrical if the output swings below GND (e.g. a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details. 6. See Typical Performance Curves for more information. Application Information Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HFA1145 design is optimized for RF = 510Ω at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains, however, the amplifier is more stable so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. For a gain of +1, a resistor (+RS) in series with +IN is required to reduce gain peaking and increase stability. GAIN (ACL) -1 +1 +2 +5 +10 RF (Ω) 425 510 (+RS = 510Ω) 510 200 180 BANDWIDTH (MHz) 300 270 330 300 130 Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND. DISABLE Input TTL Compatibility The HFA1145 derives an internal GND reference for the digital circuitry as long as the power supplies are symmetrical about GND. With symmetrical supplies the digital switching threshold (VTH = (VIH + VIL)/2 = (2.0 + 0.8)/2) is 1.4V, which ensures the TTL compatibility of the DISABLE input. If asymmetrical supplies (e.g. +10V, 0V) are utilized, the switching threshold becomes: V+ + VV TH = ------------------- + 1.4V 2 and the VIH and VIL levels will be VTH ± 0.6V, respectively. 5 FN3955.5 June 1, 2006 HFA1145 Optional GND Pad (Die Use Only) for TTL Compatibility The die version of the HFA1145 provides the user with a GND pad for setting the disable circuitry GND reference. With symmetrical supplies the GND pad may be left unconnected, or tied directly to GND. If asymmetrical supplies (e.g. +10V, 0V) are utilized, and TTL compatibility is desired, die users must connect the GND pad to GND. With an external GND, the DISABLE input is TTL compatible regardless of supply voltage utilized. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 270MHz (for AV = +1). By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, the bandwidth decreases as the load capacitance increases. For example, at AV = +1, RS = 62Ω, CL = 40pF, the overall bandwidth is limited to 180MHz, and bandwidth drops to 75MHz at AV = +1, RS = 8Ω, CL = 400pF. 50 SERIES OUTPUT RESISTANCE (Ω) Pulse Undershoot and Asymmetrical Slew Rates The HFA1145 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (See Figures 5, 8, and 11). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (See Figures 5, 8, and 11), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (See Figures 4, 7, and 10). PC Board Layout This amplifier’s frequency response depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10μF) tantalum in parallel with a small value (0.1μF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the device’s input and output connections. Capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. 40 30 20 A V = +2 A V = +1 10 0 0 50 100 200 300 150 250 LOAD CAPACITANCE (pF) 350 400 FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE Evaluation Board The performance of the HFA1145 may be evaluated using the HFA11XX Evaluation Board and a SOIC to DIP adaptor like the Aries Electronics Part Number 14-350000-10. The layout and schematic of the board are shown in Figure 2. The VH connection may be used to exercise the DISABLE pin, but note that this connection has no 50Ω termination. To order evaluation boards (part number HFA11XXEVAL), please contact your local sales office. 6 FN3955.5 June 1, 2006 HFA1145 VH 1 +IN OUT VL VGND V+ FIGURE 2A. TOP LAYOUT 510 R1 1 50Ω IN 10μF 0.1μF 2 3 4 -5V 8 7 6 5 GND GND 0.1μF 50Ω OUT VL 510 VH FIGURE 2B. TOP LAYOUT 10μF +5V FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT Typical Performance Curves 200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) A V = +1 +RS = 510Ω VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified 3.0 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.) AV = +1 +RS = 510Ω FIGURE 3. SMALL SIGNAL PULSE RESPONSE FIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE 7 FN3955.5 June 1, 2006 HFA1145 Typical Performance Curves 2.0 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = +1 +RS = 510Ω OUTPUT VOLTAGE (mV) VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 200 A V = +2 150 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) FIGURE 5. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 6. SMALL SIGNAL PULSE RESPONSE 3.0 AV = +2 2.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 TIME (5ns/DIV.) 2.0 AV = +2 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 8. LARGE SIGNAL BIPOLAR PULSE RESPONSE 200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) AV = +10 RF = 180Ω OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 AV = +10 RF = 180Ω TIME (5ns/DIV.) FIGURE 9. SMALL SIGNAL PULSE RESPONSE FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE 8 FN3955.5 June 1, 2006 HFA1145 Typical Performance Curves 2.0 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) 0V AV = +1, VIN = 1V TIME (50ns/DIV.) OUT 400mV/DIV. AV = +10 RF = 180Ω DISABLE 800mV/DIV. (0.4V to 2.4V) VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 12. OUTPUT ENABLE AND DISABLE RESPONSE GAIN (dB) 3 0 -3 VOUT = 200mVP-P +RS = 510Ω (+1) +RS = 0Ω (-1) NORMALIZED GAIN (dB) AV = + 1 3 0 -3 AV = +10 A V = +5 A V = +2 NORMALIZED PHASE (DEGREES) AV = - 1 A V = +2 AV = - 1 0 90 180 A V = +1 0.3 1 10 FREQUENCY (MHz) 100 500 270 VOUT = 200mVP-P RF = 510Ω (+2) RF = 200Ω (+5) RF = 180Ω (+10) 0.3 1 A V = +5 AV = +10 90 180 270 500 10 FREQUENCY (MHz) 100 FIGURE 13. FREQUENCY RESPONSE FIGURE 14. FREQUENCY RESPONSE NORMALIZED GAIN (dB) AV = + 2 3 0 -3 VOUT = 200mVP-P NORMALIZED GAIN (dB) 3 0 -3 VOUT = 4VP-P (+1) VOUT = 5VP-P (-1, +2) +RS = 510Ω (+1) A V = +1 AV = + 2 AV = - 1 VOUT = 1.5VP-P VOUT = 5VP-P VOUT = 200mVP-P PHASE (DEGREES) 0 90 VOUT = 1.5VP-P VOUT = 5VP-P 0.3 1 10 FREQUENCY (MHz) 100 500 180 270 1 10 FREQUENCY (MHz) 100 200 FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FIGURE 16. FULL POWER BANDWIDTH 9 FN3955.5 June 1, 2006 PHASE (DEGREES) 0 HFA1145 Typical Performance Curves NORMALIZED GAIN (dB) VOUT = 200mVP-P 3 0 RL = 100Ω BANDWIDTH (MHz) -3 RL = 50Ω AV = + 2 VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) RL = 500Ω RL = 1k Ω 500 A V = +2 400 AV = + 1 VOUT = 200mVP-P RF = 180Ω (+10) +RS = 510Ω (+1) 300 PHASE (DEGREES) RL = 5 0Ω RL = 100Ω RL = 1k Ω RL = 500Ω 0 90 180 270 200 AV = +10 100 0.3 1 10 FREQUENCY (MHz) 100 500 0 -100 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS FIGURE 18. -3dB BANDWIDTH vs TEMPERATURE +RS = 510Ω (+1) 0.25 NORMALIZED GAIN (dB) 0.20 0.15 0.10 0.05 0 -0.05 -0.10 1 10 FREQUENCY (MHz) 75 A V = +1 A V = +2 OFF ISOLATION (dB) VOUT = 200mVP-P -30 -40 -50 -60 -70 -80 -90 A V = +2 VIN = 1VP-P 0.3 1 10 FREQUENCY (MHz) 100 FIGURE 19. GAIN FLATNESS FIGURE 20. OFF ISOLATION REVERSE ISOLATION (dB) -40 -50 -60 -70 -80 -90 AV = -1 VOUT = 2VP-P AV = +1, +2 OUTPUT IMPEDANCE (Ω) 1K 100 10 1 0.1 0.01 A V = +2 0.3 1 10 FREQUENCY (MHz) 100 0.3 1 10 100 FREQUENCY (MHz) 1000 FIGURE 21. REVERSE ISOLATION (S12) FIGURE 22. ENABLED OUTPUT IMPEDANCE 10 FN3955.5 June 1, 2006 HFA1145 Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) A V = +2 0.8 0.6 SETTLING ERROR (%) VOUT = 2V -30 AV = + 2 -40 0.4 0.2 0.1 0 -0.2 -0.4 -0.6 -0.8 DISTORTION (dBc) 20MHz -50 10MHz -60 -70 3 8 13 18 23 28 TIME (ns) 33 38 43 48 -5 0 5 10 15 OUTPUT POWER (dBm) FIGURE 23. SETTLING RESPONSE FIGURE 24. SECOND HARMONIC DISTORTION vs POUT -30 A V = +2 3.6 3.5 OUTPUT VOLTAGE (V) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 AV = -1 |-VOUT| (RL= 100Ω) +VOUT (RL= 100Ω) -40 DISTORTION (dBc) 20MHz -50 10MHz +VOUT (RL= 50Ω) -60 |-VOUT| (RL= 50Ω) -70 -5 0 5 OUTPUT POWER (dBm) 10 15 2.6 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 25. THIRD HARMONIC DISTORTION vs POUT 100 100 POWER SUPPLY CURRENT (mA) FIGURE 26. OUTPUT VOLTAGE vs TEMPERATURE 6.1 INI- NOISE CURRENT (pA/√Hz) NOISE VOLTAGE (nV/√Hz) 6.0 5.9 10 ENI INI+ 1 0.1 10 5.8 5.7 5.6 1 1 10 FREQUENCY (kHz) 100 3.5 4 4.5 5 5.5 6 6.5 7 7.5 POWER SUPPLY VOLTAGE (±V) FIGURE 27. INPUT NOISE CHARACTERISTICS FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE 11 FN3955.5 June 1, 2006 HFA1145 Die Characteristics DIE DIMENSIONS: 59 mils x 59 mils x 19 mils 1500μm x 1500μm x 483μm METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ PASSIVATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ TRANSISTOR COUNT: 75 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) Metallization Mask Layout HFA1145 -IN DISABLE V+ OUT +IN V- OPTIONAL GND (NOTE) NOTE: This pad is not bonded out on packaged units. Die users may set a GND reference, via this pad, to ensure the TTL compatibility of the DIS input when using asymmetrical supplies (e.g. V+ = 10V, V- = 0V). See the “Application Information” section for details. 12 FN3955.5 June 1, 2006 HFA1145 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN3955.5 June 1, 2006