HFA1149_04

® UCT ENT P R OD LETE REPLACEM er at BS O O ED t Cent /tsc MEND uppor ECO M chn RData Sheet ical S intersil.com NO . Te r www ct our conta NTERSIL o I 1-888- HFA1149 August 2004 FN4304.4 450MHz, Low Power, Video Operational Amplifier with Programmable Output Disable The HFA1149 is a high speed, low power, current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 process. This amplifier features a unique combination of power and performance specifically tailored for video applications. The HFA1149 incorporates an output disable pin which is TTL/CMOS compatible, and user programmable for polarity (active high or low). This feature eliminates the inverter required between amplifiers in multiplexer configurations. The ultra-fast (12ns/20ns) disable/enable times make the HFA1149 the obvious choice for pixel switching and other high speed multiplexing applications. The HFA1149 is a high performance, pin compatible upgrade for the popular HA-5020 and HFA1145, as well as the CLC410. For a comparably performing op amp without an output disable, please refer to the HFA1109 data sheet. Features • Wide - 3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 450MHz • Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . . 0.8dB • Very Fast Slew Rate (AV = +2) . . . . . . . . . . . . . 1100V/µs • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1.7MΩ • Differential Gain/Phase . . . . . . . . . . 0.02%/0.02 Degrees • Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 10mA • Fast Output Disable/Enable . . . . . . . . . . . . . . . .12ns/20ns Applications • Professional Video Processing • Video Switchers and Routers • Medical Imaging • PC Multimedia Systems • Video Pixel Switching • Video Distribution Amplifiers Part # Information PART NUMBER (BRAND) HFA1149IB (H1149) HFA11XXEVAL TEMP. RANGE (oC) -40 to 85 PACKAGE 8 Ld SOIC PKG. NO. M8.15 • Flash Converter Drivers • Radar/IF Processing HFA1149 PIN DESCRIPTIONS PIN NAME DESCRIPTION Optional Logic Threshold Set. Maintains disable pin TTL compatibility with asymmetrical supplies (e.g., +10V, 0V). Defines Polarity of Disable Input. High or floating selects active low disable (i.e., DIS). TTL Compatible Disable Input. Output is driven to a true Hi-Z state when active. Polarity depends on state of Polarity Set Pin. DIP Evaluation Board for High Speed Op Amps Threshold Set Pinout HFA1149 (SOIC) TOP VIEW THRESHOLD SET 1 -IN 2 +IN 3 V- 4 + 8 DIS / DIS 7 V+ 6 OUT 5 POLARITY SET Polarity Set DIS /DIS HFA1149 DISABLE FUNCTIONALITY POLARITY SET (PIN 5) High or Float High or Float Low Low DISABLE (PIN 8) High or Float Low High or Float Low OUTPUT (PIN 6) Enabled Disabled Disabled Enabled 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HFA1149 Absolute Maximum Ratings Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V DC Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY ±1V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Output Current (Note 2) . . . . . . . . . . . . . . . . Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . 1000V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . 1000V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . 50V Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability. Electrical Specifications VSUPPLY = ±5V, AV = +2, RF = 250Ω , RL = 100Ω , Unless Otherwise Specified (NOTE 3) TEST LEVEL TEMP. (oC) PARAMETER INPUT CHARACTERISTICS Input Offset Voltage TEST CONDITIONS MIN TYP MAX UNITS A A 25 Full Full 25 Full 25 Full 25 Full Full 25 Full 25 Full Full 25 Full 25 Full 25, 85 -40 25 25 Full 47 45 50 47 0.8 0.5 ±2 1 2 10 50 48 53 51 4 5 30 0.5 0.5 2 3 40 3 3 1.6 1.6 1.7 1.4 60 1.6 ±2.5 5 8 10 15 1 3 10 15 6 8 5 8 - mV mV µV/oC dB dB dB dB µA µA nA/oC µA/V µA/V µA µA nA/oC µA/V µA/V µA/V µA/V MΩ MΩ Ω pF V Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio Input Offset Voltage Power Supply Rejection Ratio Non-Inverting Input Bias Current ∆VCM = ±2V ∆VCM = ±2V ∆VPS = ±1.25V ∆VPS = ±1.25V B A A A A A A Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity Inverting Input Bias Current ∆VPS = ±1.25V ∆VPS = ±1.25V B A A A A Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity Inverting Input Bias Current Power Supply Sensitivity Non-Inverting Input Resistance ∆VCM = ±2V ∆VCM = ±2V ∆VPS = ±1.25V ∆VPS = ±1.25V ∆VCM = ±2V ∆VCM = ±2V Inverting Input Resistance Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) B A A A A A A B B A 2 HFA1149 Electrical Specifications VSUPPLY = ±5V, AV = +2, RF = 250Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL B B B TEMP. (oC) 25 25 25 PARAMETER Input Noise Voltage Density (Note 5) Non-Inverting Input Noise Current Density (Note 5) Inverting Input Noise Current Density (Note 5) TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain (Note 5) Minimum Stable Gain AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Note 5) TEST CONDITIONS f = 100kHz f = 100kHz f = 100kHz MIN - TYP 4 2.4 40 MAX - UNITS nV/√Hz pA/√Hz pA/√Hz B B AV = -1, RF = 200Ω AV = +1, +RS = 700Ω A V = +2 25 Full - 500 1 - kΩ V/V B B B B B B 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 300 290 280 260 390 350 -1.0 -1.1 -1.6 -1.7 -1.9 -2.2 ±0.3 ±0.4 ±0.8 ±0.9 ±1.3 ±1.4 ±3 ±2.8 ±33 ±30 - 375 360 330 320 450 410 0 0 -0.45 -0.45 -0.75 -0.75 -0.85 -0.85 ±0.1 ±0.1 ±0.35 ±0.35 ±0.6 ±0.6 ±3.2 ±3 ±36 ±33 120 0.05 -55 -57 -68 -60 -65 0.2 0.5 - MHz MHz MHz MHz MHz MHz dB dB dB dB dB dB dB dB dB dB dB dB dB dB Gain Peaking AV = +2, VOUT = 0.2VP-P To 125MHz B B Gain Flatness (AV = +2, VOUT = 0.2VP-P, Note 5) B B To 200MHz B B To 250MHz B B To 125MHz Gain Flatness AV = +1, +RS = 700Ω , VOUT = 0.2VP-P (Note 5) To 200MHz B B B B To 250MHz B B OUTPUT CHARACTERISTICS Output Voltage Swing, Unloaded (Note 5) Output Current (Note 5) Output Short Circuit Current Closed Loop Output Resistance (Note 5) Second Harmonic Distortion (VOUT = 2VP-P, Note 5) Third Harmonic Distortion (VOUT = 2VP-P, Note 5) Reverse Isolation (S12) TRANSIENT CHARACTERISTICS Rise and Fall Times VOUT = 0.5VP-P B B 25 Full 1.1 1.1 1.3 1.4 ns ns AV = -1, RL = ∞ AV = -1, RL = 75Ω A V = -1 DC, AV = +1, Enabled 20MHz 60MHz 20MHz 60MHz 30MHz A A A A B B B B B B B 25 Full 25, 85 -40 25 25 25 25 25 25 25 V V mA mA mA Ω dBc dBc dBc dBc dB 3 HFA1149 Electrical Specifications VSUPPLY = ±5V, AV = +2, RF = 250Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 3) TEST LEVEL B B Slew Rate AV = -1, RF = 200Ω VOUT = 5VP-P AV = +1, VOUT = 4VP-P, +RS = 700Ω AV = +2, VOUT = 5VP-P Settling Time (VOUT = +2V to 0V step, Note 5) To 0.1% To 0.05% To 0.01% Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz) RL = 150Ω RL = 75Ω Differential Phase (f = 3.58MHz) RL = 150Ω RL = 75Ω POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 4) C A A 25 25 Full ±4.5 9.6 10 ±5.5 10 11 V mA mA B B B B B B B B 25 Full 25 Full 25 Full 25 Full 0.02 0.03 0.04 0.05 0.02 0.02 0.05 0.06 0.06 0.09 0.09 0.12 0.06 0.06 0.09 0.13 % % % % Degrees Degrees Degrees Degrees VIN = ±2V B B B B B B B B B B TEMP. (oC) 25 Full 25 Full 25 Full 25 Full 25 25 25 25 PARAMETER Overshoot TEST CONDITIONS VOUT = 0.5VP-P MIN 2300 2200 475 430 940 800 - TYP 0 0.5 2600 2500 550 500 1100 950 19 23 36 5 MAX 2 5 - UNITS % % V/µs V/µs V/µs V/µs V/µs V/µs ns ns ns ns HFA1149 DISABLE CHARACTERISTICS Polarity Set = Floating, Threshold Set = Floating, Unless Otherwise Specified Disabled Supply Current Digital Input Logic Low (Note 4) Digital Input Logic High (Note 4) VDIS = 0V A A A A Digital Input Logic Low Current (Note 4) Digital Input Logic High Current (Note 4) Output Disable Time (Note 5) Output Enable Time (Note 5) Disabled Output Capacitance Disabled Output Leakage Off Isolation (VDIS = 0V, VIN = 1VP-P, Note 5) NOTES: 3. Test Level: A. Production tested; B. Typical or guaranteed limit based on characterization; C. Design Typical for information only. 4. Digital inputs are Polarity Set and DIS / DIS. 5. See Typical Performance Curves for more information. VDIGITAL = 0V VDIGITAL = 5V VIN = ±0.5V, VDIS = 2.4V to 0V VIN = ±0.5V, VDIS = 0V to 2.4V VDIS = 0V ± VDIS = 0V, VIN = VOUT = ±3V At 10MHz At 30MHz 2V, A A B B B A B B Full Full 25 Full Full Full 25 25 25 Full 25 25 2.0 2.2 2.8 100 1 12 20 2.5 3 -64 -54 3.5 0.8 200 15 10 mA V V V µA µA ns ns pF µA dB dB 4 HFA1149 Application Information Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF . All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF . The HFA1149 design is optimized for a 250Ω RF at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (ACL) -1 +1 +2 +5 +10 RF (Ω) 200 250 (+RS = 700Ω) 250 100 90 BANDWIDTH (MHz) 375 330 450 160 70 The DIS / DIS input is TTL compatible, and unlike most competitive devices, the TTL compatibility can be maintained when the HFA1149 is operated at supplies other than ±5V (see the “Threshold Set input” section below). An internal resistive bias network ensures that the DIS / DIS pin is pulled high if it is undriven on the PCB. Polarity Set Input A novel feature of the HFA1149 is the polarity programmability of the disable control pin (DIS / DIS). Depending on the state of the Polarity Set input (pin 5), the designer can define the active state to be high or low for the DIS / DIS input (see the “HFA1149 Disable Functionality” table on the front page). With this feature, a 2:1 multiplexer can be created by defining one amplifier’s disable control as active low (Polarity Set = High or floating), and the other amplifier’s control as active high (Polarity Set = Low). Note that if the Polarity Set pin is left floating, an internal pull-up resistor pulls the pin high, and the HFA1149 becomes a drop-in replacement for any standard ±5V supply op amp with output disable (e.g., CLC410, CLC411, CLC430, HA-5020, HFA1145, AD810). Likewise, if the disable and polarity set pins are both floated, the HFA1149 works just like a standard op amp (i.e., the output is always enabled). Threshold Set Input for TTL Compatibility The HFA1149 derives an internal threshold reference for the digital circuitry as long as the power supplies are nominally ±5V. This reference is used to ensure the TTL compatibility of the DIS / DIS and Polarity Set inputs. With symmetrical ±5V supplies the Threshold Set pin (Pin 1) must be floated to guarantee TTL compatibility. If asymmetrical supplies (e.g., +10V, 0V) are utilized, and TTL compatibility is desired, the Threshold Set pin must be connected to an external voltage (e.g., GND for +10V, 0V operation). The following equation should be used to determine the voltage (VTHSET) to be applied to the Threshold Set pin: VV THSET = 1.58 ( V DIGTH + 1.6V ) – ----- – 0.46 ( V+ ) , 8 Table 1 lists recommended RF values, and the expected bandwidth, for various closed loop gains. For a gain of +1, a resistor (+RS) in series with +IN is required to reduce gain peaking and increase stability Output Disable Function The HFA1149 incorporates an output disable function that is useful for reducing power dissipation or for multiplexing signals onto a common analog bus. When disabled, the inverting input and the output become high impedances (however, the feedback network for gains other than +1 still present a load to ground from the output), the supply current reduces by 68%, and the input to output isolation becomes greater than 60dB. The amplifier is disabled by driving the DIS / DIS input to its active state. The active state of the DIS / DIS input is user programmable via the HFA1149’s Polarity Set input (see next paragraph). If the Polarity Set input is left floating, or is tied to a logic high (e.g., V+), then the disable function is activated by a logic low on the DIS / DIS input (typical of most output disable op amps). If the Polarity Set input is connected to a logic low (e.g., GND), then a logic high on the DIS / DIS input disables the amplifier. where VDIGTH is the desired switching point (typically 1.4V for TTL compatibility) of the Polarity Set and DIS / DIS inputs. Figure 1 illustrates the input impedance of the Threshold Set pin for calculating the input current at a given VTHSET. V+ 7kΩ VTHSET 3kΩ 25kΩ V- FIGURE 1. THRESHOLD SET INPUT IMPEDANCE 5 HFA1149 PC Board Layout The frequency response of this amplifier depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. Thus, it is recommended that the ground plane be removed under traces connected to -IN, and connections to -IN should be kept as short as possible. . BOARD SCHEMATIC 510Ω 510Ω VH 1 50Ω IN 10µF 0.1µF -5V GND 2 3 4 8 7 6 5 GND 0.1µF 50Ω OUT VL 10µF +5V TOP LAYOUT VH 1 +IN OUT V+ VL VGND Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth. By decreasing RS as CL increases, the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. BOTTOM LAYOUT Evaluation Board The performance of the HFA1149 may be evaluated using the HFA11XX Evaluation Board (part number HFA11XXEVAL). Please contact your local sales office for information. When evaluating this amplifier, the two 510Ω gain setting resistors on the evaluation board should be changed to 250Ω. The layout and schematic of the board are shown in Figure 2. NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics Part Number 08-350000-10. FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT 6 HFA1149 Typical Performance Curves 200 A V = +2 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified 2.0 A V = +2 OUTPUT VOLTAGE (V) FIGURE 3. SMALL SIGNAL PULSE RESPONSE 200 A V = +1 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 2.0 FIGURE 4. LARGE SIGNAL PULSE RESPONSE A V = +1 TIME (5ns/DIV.) FIGURE 5. SMALL SIGNAL PULSE RESPONSE 200 AV = -1 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 2.0 FIGURE 6. LARGE SIGNAL PULSE RESPONSE AV = -1 TIME (5ns/DIV.) FIGURE 7. SMALL SIGNAL PULSE RESPONSE FIGURE 8. LARGE SIGNAL PULSE RESPONSE 7 HFA1149 Typical Performance Curves 200 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 AV = +10 0 -50 A V = +5 -100 -150 -200 TIME (5ns/DIV.) AV = + 5 VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 2.0 1.5 1.0 0.5 AV = +10 0 AV = +10 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = + 5 AV = +10 A V = +5 FIGURE 9. SMALL SIGNAL PULSE RESPONSE FIGURE 10. LARGE SIGNAL PULSE RESPONSE GAIN (dB) 3 0 -3 VOUT = 200mVP-P GAIN AV = +1 NORMALIZED PHASE (DEGREES) 125 DISABLE 800mV/DIV. (0.4V TO 2.4V) 0 PHASE A V = +1 A V = -1 0 90 180 A V = -1 0.3 TIME (10ns/DIV.) 1 10 FREQUENCY (MHz) 100 270 700 OUTPUT 400mV/DIV. 0 AV = +2, VIN = 0.5V AV = +1 FIGURE 11. OUTPUT ENABLE AND DISABLE RESPONSE FIGURE 12. FREQUENCY RESPONSE NORMALIZED GAIN (dB) 510 3 0 -3 BANDWIDTH (MHz) AV = +10 AV = + 5 PHASE (DEGREES) PHASE AV = +2 0 90 AV = +10 AV = +5 180 270 700 450 420 390 360 A V = +1 A V = -1 VOUT = 200mVP-P GAIN AV = +2 480 A V = +2 330 300 -75 0.3 1 10 FREQUENCY (MHz) 100 -50 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 13. FREQUENCY RESPONSE FIGURE 14. -3dB BANDWIDTH vs TEMPERATURE 8 HFA1149 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 116 AV = + 1 106 0.1 0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 1 VOUT = 200mVP-P ( VIO ) ) I AZOL (dB, 20 LOG 96 86 76 66 56 46 36 26 0.01 0.1 0.3 1 3 6 10 30 100 0 45 90 135 180 500 PHASE (DEGREES) 12 15 A V = +2 10 FREQUENCY (MHz) 100 500 FREQUENCY (MHz) FIGURE 15. GAIN FLATNESS FIGURE 16. OPEN LOOP TRANSIMPEDANCE -30 AV = +1 -40 DISTORTION (dBc) 100MHz -20 AV = +1 -30 100MHz -40 DISTORTION (dBc) -50 50MHz -60 20MHz -70 10MHz -50 -60 -70 20MHz -80 50MHz 10MHz -80 -90 -90 -6 -3 0 3 6 OUTPUT POWER (dBm) 9 12 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) FIGURE 17. 2nd HARMONIC DISTORTION vs POUT FIGURE 18. 3rd HARMONIC DISTORTION vs POUT -30 AV = +2 -40 100MHz DISTORTION (dBc) DISTORTION (dBc) -50 50MHz -60 10MHz -70 20MHz -80 -30 AV = +2 -40 100MHz -50 50MHz -60 20MHz -70 10MHz -80 -90 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 15 -90 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 FIGURE 19. 2nd HARMONIC DISTORTION vs POUT FIGURE 20. 3rd HARMONIC DISTORTION vs POUT 9 HFA1149 Typical Performance Curves -20 VOUT = 2VP-P -30 DISTORTION (dBc) -30 A V = +1 DISTORTION (dBc) -40 -40 A V = -1 A V = +2 -60 VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) -20 VOUT = 2VP-P -50 AV = +2, -1 -60 AV = +1 -50 -70 -70 AV = +1 -80 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 -80 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) FIGURE 21. 2nd HARMONIC DISTORTION vs FREQUENCY FIGURE 22. 3rd HARMONIC DISTORTION vs FREQUENCY A V = +2 OUTPUT RESISTANCE (Ω) 1K OFF ISOLATION (dB) 100 10 1 0.1 0.01 -30 -40 -50 -60 -70 -80 -90 -100 A V = +2 VIN = 1VP-P 0.3 1 10 FREQUENCY (MHz) 100 1000 0.5 1 10 FREQUENCY (MHz) 100 FIGURE 23. CLOSED LOOP OUTPUT RESISTANCE FIGURE 24. OFF ISOLATION 3.6 3.4 3.2 OUTPUT VOLTAGE (V) 3.0 +VOUT (RL = 50Ω) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 -75 -50 -25 0 25 50 75 100 125 |-VOUT| (RL = 50Ω) |-VOUT| (RL = 100Ω) +VOUT (RL = 50Ω) +VOUT (RL = 100Ω) |-VOUT| (RL = 100Ω) SUPPLY CURRENT (mA) 14 13.5 13 12.5 12 11.5 11 10.5 10 9.5 9 8.5 4 4.5 5 5.5 6 6.5 7 7.5 8 TEMPERATURE (°C) SUPPLY VOLTAGE (±V) FIGURE 25. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE 10 HFA1149 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 17 16 15 NOISE VOLTAGE (nV/√Hz) SUPPLY CURRENT (mA) 14 13 12 11 10 9 8 7 6 5 4 -75 VS = ±4V VS = ±5V VS = ±8V 100 100 INIINI+ 10 ENI 10 INI+ 1 -50 -25 0 25 50 75 100 125 0.1 TEMPERATURE (oC) 1 10 FREQUENCY (kHz) 1 100 FIGURE 27. SUPPLY CURRENT vs TEMPERATURE FIGURE 28. INPUT NOISE CHARACTERISTICS A V = +2 0.1 SETTLING ERROR (%) VOUT = 2V 0.05 0.025 0 -0.025 -0.05 -0.1 10 20 30 40 50 60 70 80 90 100 TIME (ns) FIGURE 29. SETTLING RESPONSE 11 NOISE CURRENT (pA/√Hz) HFA1149 Die Characteristics DIE DIMENSIONS 59 mils x 80 mils x 19 mils 1500µm x 2020µm x 483µm METALLIZATION Type: Metal 1: AICu(2%)/TiW Type: Metal 2: AICu(2%) Thickness: Metal 1: 8kÅ ±0.4kÅ Thickness: Metal 2: 16kÅ ±0.8kÅ GLASSIVATION Type: Nitride Thickness: 4kÅ ±0.5kÅ TRANSISTOR COUNT 130 SUBSTRATE POTENTIAL (POWERED UP) Floating (Recommend Connection to V-) Metallization Mask Layout HFA1149 THRESHOLD SET NC DIS / DIS NC V+ -IN OUT NC POLARITY SET +IN V- NC NC 12 HFA1149 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 A1 B C D E α µ A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13