HFA1212IB

UC T PROD ENT OLETE REPLACEM r at OBS Cente c NDED s OMME upport O REC Technical S ntersil.com/t N Data our Sheetwww.i t contac TERSIL or -888-IN 1 ® HFA1212 July 2004 FN3607.6 Dual 350MHz, Low Power Closed Loop Buffer Amplifier The HFA1212 is a dual closed loop Buffer featuring user programmable gain and high speed performance. Manufactured on Intersil’s proprietary complementary bipolar UHF-1 process, these devices offer wide -3dB bandwidth of 350MHz, very fast slew rate, excellent gain flatness and high output current. A unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components. Gain selection is accomplished via connections to the inputs, as described in the “Application Information” section. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. Features • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025% • Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 350MHz • Very Fast Slew Rate (AV = -1) . . . . . . . . . . . . . . 1100V/µs • Low Supply Current . . . . . . . . . . . . . . . . . . . . 6mA/Buffer • High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA • Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V • User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors • Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns • Standard Operational Amplifier Pinout Applications • High Resolution Monitors • Professional Video Processing • Medical Imaging Part # Information PART NUMBER (BRAND) HFA1212IB (H1212I) TEMP. RANGE (oC) -40 to 85 PACKAGE 8 Ld SOIC PKG. NO. M8.15 • Video Digitizing Boards/Systems • RF/IF Processors • Battery Powered Communications • Flash Converter Drivers • High Speed Pulse Amplifiers Pinout HFA1212 (SOIC) TOP VIEW OUT1 -IN1 +IN1 V1 2 3 4 + + 8 7 6 5 V+ OUT2 -IN2 +IN2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004. All Rights Reserved HFA1212 Absolute Maximum Rating Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Output Current (Note 1) . . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .600V Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current should not exceed 30mA for maximum reliability. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. TEST CONDITIONS (NOTE 3) TEST LEVEL TEMP (oC) PARAMETER INPUT CHARACTERISTICS Output Offset Voltage MIN TYP MAX UNITS A A 25 Full Full 25 Full 25 85 -40 25 85 -40 25 Full Full 25 Full 25 Full 25 85 -40 25 25 25, 85 -40 25 25 42 40 40 45 43 43 0.8 0.5 0.5 ±1.8 ±1.2 - 2 3 22 45 44 45 49 48 48 1 3 30 0.5 1.1 1.4 1.3 350 2 ±2.4 ±1.7 7 3.6 10 15 70 15 30 15 25 80 15 25 1 3 - mV mV µV/oC mV mV dB dB dB dB dB dB µA µA nA/oC µA µA µA/V µA/V MΩ MΩ MΩ Ω pF V V nV/√Hz pA/√Hz Average Output Offset Voltage Drift Channel-to-Channel Output Offset Voltage Mismatch Common-Mode Rejection Ratio ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Power Supply Rejection Ratio ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Input Bias Current B A A A A A A A A A A Input Bias Current Drift Channel-to-Channel Input Bias Current Mismatch Input Bias Current Power Supply Sensitivity ∆VPS = ±1.25V ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Inverting Input Resistance Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR and +RIN tests) Input Noise Voltage Density (Note 4) Input Noise Current Density (Note 4) f = 100kHz f = 100kHz B A A A A Input Resistance A A A C C A A B B 2 HFA1212 Electrical Specifications VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued) TEST CONDITIONS (NOTE 3) TEST LEVEL TEMP (oC) PARAMETER TRANSFER CHARACTERISTICS Gain (VIN = -1V to +1V) MIN TYP MAX UNITS AV = -1 A A 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full -0.98 0.975 0.98 0.975 1.96 1.95 - 0.996 1.000 0.992 0.993 1.988 1.990 - -1.02 -1.025 1.02 1.025 2.04 2.05 ±0.02 ±0.025 ±0.025 ±0.025 ±0.04 ±0.05 V/V V/V V/V V/V V/V V/V V/V V/V V/V V/V V/V V/V AV = +1 A A AV = +2 A A Channel-to-Channel Gain Mismatch A V = -1 A A AV = +1 A A AV = +2 A A AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Note 4) A V = -1 AV = +1, +RS = 620Ω AV = +2 Full Power Bandwidth (VOUT = 5VP-P at AV = +2 or -1, VOUT = 4VP-P at AV = +1, Note 4) Gain Flatness (VOUT = 0.2VP-P, Note 4) Crosstalk (All Channels Hostile, Note 4) OUTPUT CHARACTERISTICS Output Voltage Swing (Note 4) Output Current (Note 4) Output Short Circuit Current DC Closed Loop Output Impedance Second Harmonic Distortion (AV = +2, VOUT = 2VP-P, Note 4) Third Harmonic Distortion (AV = +2, VOUT = 2VP-P, Note 4) Reverse Isolation (S12, Note 4) AV = +2 10MHz 20MHz 10MHz 20MHz 30MHz, AV = +2 A V = -1 AV = -1, RL = 50Ω A A A A B B B B B B B 25 Full 25, 85 -40 25 25 25 25 25 25 25 ±3.0 ±2.8 50 28 ±3.2 ±3.0 55 42 100 0.2 -60 -50 -60 -50 -65 V V mA mA mA Ω dBc dBc dBc dBc dB A V = -1 AV = +1, +RS = 620Ω AV = +2 AV = +2, To 25MHz AV = +2, To 50MHz 5MHz 10MHz B B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 300 240 350 165 150 125 ±0.03 ±0.04 -65 -60 MHz MHz MHz MHz MHz MHz dB dB dB dB TRANSIENT RESPONSE AV = +2, Unless Otherwise Specified Rise and Fall Times (VOUT = 0.5VP-P) Rise Time Fall Time B B 25 25 1.0 1.1 ns ns 3 HFA1212 Electrical Specifications VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued) TEST CONDITIONS +OS -OS AV = -1 +SR -SR AV = +1, +RS = 620Ω AV = +2 +SR -SR +SR -SR Settling Time (VOUT = +2V to 0V Step, Note 4) To 0.1% To 0.05% To 0.02% Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz, AV = +2) Differential Phase (f = 3.58MHz, AV = +2) POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current C A A NOTE: 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. See Typical Performance Curves for more information. 5. Negative overshoot dominates for output signal swings below GND (e.g. 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 0.5V condition. See the “Application Information” section for details. 25 25 Full ±4.5 5.9 6.1 ±5.5 6.1 6.3 V mA/Op Amp mA/Op Amp RL = 150Ω RL = 150Ω B B 25 25 0.025 0.03 % Degrees VIN = ±2V (NOTE 3) TEST LEVEL B B B B B B B B B B B B TEMP (oC) 25 25 25 25 25 25 25 25 25 25 25 25 PARAMETER Overshoot (VOUT = 0.5VP-P, VIN tRISE = 1ns, Note 5) Slew Rate (VOUT = 5VP-P at AV = +2 or -1, VOUT = 4VP-P at AV = +1) MIN - TYP 4 13 2000 1150 1100 850 1300 900 24 37 60 8.5 MAX - UNITS % % V/µs V/µs V/µs V/µs V/µs V/µs ns ns ns ns Application Information HFA1212 Advantages The HFA1212 features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. Implementing a dual, gain of 2, cable driver with this IC eliminates the four gain setting resistors, which frees up board space for termination resistors. Like most newer high performance amplifiers, the HFA1212 is a current feedback amplifier (CFA). CFAs offer high bandwidth and slew rate at low supply currents, but can be difficult to use because of their sensitivity to feedback capacitance and parasitics on the inverting input (summing node). The HFA1212 eliminates these concerns by bringing the gain setting resistors on-chip. This yields the optimum placement and value of the feedback resistor, while minimizing feedback and summing node parasitics. Because there is no access to the summing node, the PCB parasitics do not impact performance at gains of +2 or -1 (see “Unity Gain Considerations” for discussion of parasitic impact on unity gain performance). The HFA1212’s closed loop gain implementation provides better gain accuracy, lower offset and output impedance, and better distortion compared with open loop buffers. Closed Loop Gain Selection This “buffer” operates in closed loop gains of -1, +1, or +2, with gain selection accomplished via connections to the ±inputs. Applying the input signal to +IN and floating -IN selects a gain of +1 (see next section for layout caveats), while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded through a 50Ω resistor. The table below summarizes these connections: GAIN (ACL) -1 +1 +2 CONNECTIONS +INPUT 50Ω to GND Input Input -INPUT Input NC (Floating) GND 4 HFA1212 Unity Gain Considerations Unity gain selection is accomplished by floating the -Input of the HFA1212. Anything that tends to short the -Input to GND, such as stray capacitance at high frequencies, will cause the amplifier gain to increase toward a gain of +2. The result is excessive high frequency peaking, and possible instability. Even the minimal amount of capacitance associated with attaching the -Input lead to the PCB results in approximately 6dB of gain peaking. At a minimum this requires due care to ensure the minimum capacitance at the -Input connection. Table 1 lists five alternate methods for configuring the HFA1212 as a unity gain buffer, and the corresponding performance. The implementations vary in complexity and involve performance trade-offs. The easiest approach to implement is simply shorting the two input pins together, and applying the input signal to this common node. The amplifier bandwidth decreases from 430MHz to 280MHz, but excellent gain flatness is the benefit. A drawback to this approach is that the amplifier input noise voltage and input offset voltage terms see a gain of +2, resulting in higher noise and output offset voltages. Alternately, a 100pF capacitor between the inputs shorts them only at high frequencies, which prevents the increased output offset voltage but delivers less gain flatness. Another straightforward approach is to add a 620W resistor in series with the amplifier’s positive input. This resistor and the HFA1212 input capacitance form a low pass filter which rolls off the signal bandwidth before gain peaking occurs. This configuration was employed to obtain the data sheet AC and transient parameters for a gain of +1. PC Board Layout This amplifier’s frequency response depends greatly on the care taken in designing the PC board (PCB). The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. An example of a good high frequency layout is the Evaluation Board shown in Figure 3. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 350MHz. By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth decreases as the load capacitance increases. TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS APPROACH Remove -IN Pin +RS = 620Ω +RS = 620Ω and Remove -IN Pin Short +IN to -IN (e.g., Pins 2 and 3) 100pF Capacitor Between +IN and -IN PEAKING (dB) 4.5 0 0.5 0.6 0.7 BW (MHz) 430 220 215 280 290 ±0.1dB GAIN FLATNESS (MHz) 21 27 15 70 40 Pulse Overshoot The HFA1212 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased overshoot on the negative portion of the output waveform (see Figure 6, Figure 9, and Figure 12). This overshoot isn’t present for small bipolar signals (see Figure 4, Figure 7, and Figure 10) or large positive signals (see Figure 5, Figure 8 and Figure 11). 5 HFA1212 50 SERIES OUTPUT RESISTANCE (Ω) 40 50Ω OUT 30 IN 20 AV = +2 10 −5V 10µF 0 0 50 100 150 200 250 300 350 400 0.1µF AV = +1 50Ω R1 (NOTE) 1 2 3 4 − + 8 7 6 5 GND GND 0.1µF +5V 10µF NOTE: R1 = ∞ (AV = +1) or 0Ω (AV = +2) LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC Evaluation Board The performance of the HFA1212 may be evaluated using the HA5023 Evaluation Board, slightly modified as follows: 1. Remove the two feedback resistors, and leave the connections open. 2. a. For AV = +1 evaluation, remove the gain setting resistors (R1), and leave pins 2 and 6 floating. b. For AV = +2, replace the gain setting resistors (R1) with 0Ω resistors to GND. 3. Replace the 0Ω series output resistors with 50Ω. The modified schematic for amplifier 1, and the board layout are shown in Figures 2 and 3. NOTE: Note: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics Part Number 08-350000-10. FIGURE 3B. BOTTOM LAYOUT FIGURE 3. EVALUATION BOARD LAYOUT To order evaluation boards (part number HA5023EVAL), please contact your local sales office. FIGURE 3A. TOP LAYOUT 6 HFA1212 Typical Performance Curves 200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) A V = +2 VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified 2.0 1.5 1.0 OUTPUT VOLTAGE (V) 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = +2 FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 1.5 AV = + 2 200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) AV = + 1 1.0 OUTPUT VOLTAGE (V) 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE 2.0 1.5 AV = + 1 2.0 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = + 1 1.0 OUTPUT VOLTAGE (V) 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE 7 HFA1212 Typical Performance Curves (Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified 200 AV = - 1 150 100 OUTPUT VOLTAGE (V) 50 0 -50 -100 -150 -200 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = − 1 OUTPUT VOLTAGE (mV) TIME (5ns/DIV.) FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 1.5 1.0 OUTPUT VOLTAGE (V) 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) NORMALIZED GAIN (dB) AV = - 1 6 3 0 -3 -6 -9 PHASE GAIN AV = + 2 NORMALIZED PHASE (DEGREES) A V = +1 AV = -1 0 -90 A V = +1 A V = +2 -180 -270 -360 600 VOUT = 200mVP-P +RS = 620Ω (+1) +RS = 0Ω (-1, +2) 1 10 100 FREQUENCY (MHz) FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 13. FREQUENCY RESPONSE NORMALIZED GAIN (dB) 6 3 NORMALIZED GAIN (dB) 0 -3 -6 -9 AV = -1 A V = +2 A V = +1 VOUT = 4VP-P (+1) VOUT = 5VP-P (-1, +2) +RS = 620Ω (+1) 1 10 FREQUENCY (MHz) 100 300 0.7 VOUT = 200mVP-P 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 1 AV = + 1 10 FREQUENCY (MHz) AV = -1 100 AV = + 2 +RS = 620Ω (+1) +RS = 0Ω (-1, +2) FIGURE 14. FULL POWER BANDWIDTH FIGURE 15. GAIN FLATNESS 8 HFA1212 Typical Performance Curves -10 -20 -30 CROSSTALK (dB) -40 GAIN (dB) -50 -60 -70 -80 -90 -100 -110 0.3 1 10 FREQUENCY (MHz) A V = +2 100 AV = + 1 AV = -1 (Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 AV = + 2 RL = ∞ RL = 100Ω -110 0.3 1 10 FREQUENCY (MHz) 100 500 FIGURE 16. REVERSE ISOLATION FIGURE 17. ALL HOSTILE CROSSTALK -40 -45 DISTORTION (dBc) -50 -55 10MHz -60 -65 -70 -10 DISTORTION (dBc) 20MHz -40 -45 -50 20MHz -55 -60 10MHz -65 -5 0 5 10 15 -70 -10 -5 OUTPUT POWER (dBm) 0 5 OUTPUT POWER (dBm) 10 15 FIGURE 18. 2nd HARMONIC DISTORTION vs POUT FIGURE 19. 3rd HARMONIC DISTORTION vs POUT 20 0.10 SETTLING ERROR (%) A V = +1 NOISE VOLTAGE (nV/÷√Hz) 16 20 0.05 16 0 12 12 -0.05 8 ENI 8 -0.10 4 INI 0 0.1 4 13 33 53 73 93 113 TIME (ns) 133 153 173 1 10 FREQUENCY (kHz) 0 100 FIGURE 20. SETTLING RESPONSE FIGURE 21. INPUT NOISE CHARACTERISTICS 9 NOISE CURRENT (pA/÷√Hz) HFA1212 Typical Performance Curves 3.6 3.5 OUTPUT VOLTAGE (V) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 |-VOUT| (RL= 50Ω) +VOUT (RL= 50Ω) AV = - 1 (Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified |-VOUT| (RL= 100Ω) +VOUT (RL= 100Ω) TEMPERATURE (oC) FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE Die Characteristics DIE DIMENSIONS: 69 mils x 92 mils x 19 mils 1750µm x 2330µm x 483µm METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ PASSIVATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ TRANSISTOR COUNT: 180 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) 10 HFA1212 Metallization Mask Layout HFA1212 -IN1 OUT1 NC V+ NC +IN1 OUT2 NC NC -IN2 NC V- NC +IN2 11 HFA1212 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 A1 B C D E α µ A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12