HFA3524IA96

HFA3524 TM Data Sheet March 2000 File Number 4062.8 2.5GHz/600MHz Dual Frequency Synthesizer The Intersil 2.4GHz PRISM® chip set is a highly integrated six-chip solution for RF modems employing Direct Sequence Spread Spectrum (DSSS) signaling. The HFA3524 600MHz Dual Frequency Synthesizer is one of the six chips in the PRISM chip set (see the Typical Application Diagram). The HFA3524 is a monolithic, integrated dual frequency synthesizer, including prescaler, is to be used as a local oscillator for RF and first IF of a dual conversion transceiver. The HFA3524 contains a dual modulus prescaler. A 32/33 or 64/65 prescaler can be selected for the RF synthesizer and a 8/9 or a 16/17 prescaler can be selected for the IF synthesizer. Using a digital phase locked loop technique, the HFA3524 can generate a very stable, low noise signal for the RF and IF local oscillator. Serial data is transferred into the HFA3524 via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The HFA3524 features very low current consumption of 13mA at 3V. Features • 2.7V to 5.5V Operation • Low Current Consumption • Selectable Powerdown Mode ICC = 1µA Typical at 3V • Dual Modulus Prescaler, 32/33 or 64/65 • Selectable Charge Pump High Z State Mode Applications • Systems Targeting IEEE 802.11 Standard • PCMCIA Wireless Transceiver • Wireless Local Area Network Modems • TDMA Packet Protocol Radios • Part 15 Compliant Radio Links • Portable Battery Powered Equipment Ordering Information PART NUMBER HFA3524IA HFA3524IA96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld TSSOP Tape and Reel PKG. NO. M20.173 Functional Block Diagram fIN IF IF PRESCALER 15-BIT IF N COUNTER PHASE COMP CHARGE PUMP IF LD 15-BIT IF R COUNTER OSCIN OSC 15-BIT RF R COUNTER RF LD f OUT LOCK DETECT FASTLOCK MUX FO/LD DO IF CHARGE PUMP fIN RF RF PRESCALER 18-BIT RF N COUNTER PHASE COMP DO RF CLOCK DATA LE 22-BIT DATA REGISTER 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. HFA3524 Typical Application Diagram HFA3724 (FILE# 4067) TUNE/SELECT HSP3824 (FILE# 4064) RXI DATA TO MAC CTRL SPREAD DPSK MOD. PRISM CHIP SET FILE #4063 HFA3424 (NOTE) (FILE# 4131) A/D DESPREAD DPSK DEMOD HFA3624 UP/DOWN CONVERTER (FILE# 4066) I RXQ A/D CCA 802.11 MAC-PHY INTERFACE ÷2 0o/90o M U X M U X RSSI A/D TXI RFPA HFA3925 (FILE# 4132) VCO VCO TXQ Q QUAD IF MODULATOR DUAL SYNTHESIZER DSSS BASEBAND PROCESSOR HFA3524 (FILE# 4062) NOTE: Required for systems targeting 802.11 specifications. TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA352 For additional information on the PRISM chip set, see us on the web http://www.intersil.com/prism or call (321) 724-7800 to access Intersil’ AnswerFAX system. When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive. The four-digit file numbers are shown in Typical Application Diagram, and correspond to the appropriate circuit. 2 HFA3524 Pinout HFA3524 (TSSOP) TOP VIEW VCC1 VP1 DO RF GND fIN RF f IN RF GND OSCIN GND 1 2 3 4 5 6 7 8 9 20 VCC2 19 VP2 18 DO IF 17 GND 16 fIN IF 15 f IN IF 14 GND 13 LE 12 DATA 11 CLOCK FO/LD 10 Pin Descriptions PIN NUMBER 1 PIN NAME VCC1 I/O DESCRIPTION Power supply voltage input. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power Supply for RF charge pump. Must be > VCC. Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. Ground. RF prescaler input. Small signal input from the VCO. RF prescaler complimentary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. Ground. Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Ground. Multiplexed output of the RF/lF programmable or reference dividers, RF/lF lock detect signals and Fastlock mode. CMOS output (see Programmable Modes). High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge, into the 22-bit shift register. Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. Load enable CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). Ground. IF prescaler complimentary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. IF prescaler input. Small signal input from the VCO. Ground. IF charge pump output. For connection to a loop filter for driving the input of an external VCO. Power Supply for IF charge pump. Must be >VCC. Power supply voltage input Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VP1 DO RF GND fIN RF f IN RF GND OSCIN GND FO/LD Clock Data LE GND f IN IF O I l I O I l l I 16 17 18 19 20 fIN IF GND DO IF VP2 VCC2 I O - 3 HFA3524 Block Diagram VCC1 VP1 1 1X 4X RF LOCK DETECT RF CHARGE PUMP 2 PU DO RF 3 PD GND 4 fOUT/ LOCK DETECT/ FASTLOCK MULTIPLEXER 1X IF LOCK DETECT 4X 20 VCC2 VP2 IF CHARGE PUMP 19 PU 18 PD 17 GND DO IF RF PHASE DETECTOR FR 1 FP 1 FR 2 FP 2 IF PHASE DETECTOR SWALLOW CONTROL SWALLOW CONTROL 5 fIN RF 6 f IN RF - + 32/33 OR 64/65 RF PRESCALER PROGRAMMABLE 18-BIT (RF) N-COUNTER PROGRAMMABLE 15-BIT (IF) N-COUNTER 8/9 OR 16/17 IF PRESCALER 16 + 15 fIN IF f IN IF 1-BIT RF PWDN 1-BIT P1 LATCH (RF) 18-BIT N-LATCH (IF) 15-BIT N-LATCH 1-BIT P2 LATCH 1-BIT IF PWDN 14 GND 7 GND 5-BIT MODE LATCH 15-BIT R1 LATCH LATCH DECODE OSCIN 8 PROGRAMMABLE 15-BIT (R1) REFERENCE COUNTER 13 LE 9 GND PROGRAMMABLE 15-BIT (R2) REFERENCE COUNTER 20-BIT SHIFT REGISTER 2-BIT CONTROL LATCH 12 DATA 11 CLOCK 5-BIT MODE LATCH 15-BIT R2 LATCH 10 FOLD NOTES: 1. VCC1 supplies power to the RF prescaler, N-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter and phase detector, RF and IF R-counters along with the OSCIN buffer and all digital circuitry. VCC1 and VCC2 are separated by a diode and must be run at the same voltage level. 2. VP1 and VP2 can be run independently as long as VP ≥ VCC. 4 HFA3524 Absolute Maximum Ratings Power Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Voltage on Any Pin with GND = 0V (VI) . . . . . . . . . . . -0.3V to +6.5V Thermal Resistance (Typical, Note 3) θJA (oC/W) TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Storage Temperature Range (TS) . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 4s) (TL) . . . . . . . . . .260oC (TSSOP - Lead Tips Only) Thermal Information Operating Conditions Power Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC to +5.5V Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Power Supply Current RF + IF RF Only Powerdown Current Operating Frequency Operating Frequency Oscillator Frequency Maximum Phase Detector Frequency RF Input Sensitivity VCC = 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified HFA3524 SYMBOL ICC VCC = 2.7V to 5.5V VCC = 2.7V to 5.5V ICC-PWDN fIN RF fIN IF fOSC fφ PfIN RF VCC = 3.0V VCC = 5.0V VCC = 3.0V 0.5 45 5 10 -15 -10 -10 0.5 0.8VCC -1.0 -1.0 -100 VCC -0.4 50 10 50 50 50 50 13 10 1 25 2.5 600 44 +4 +4 +4 0.2VCC 1.0 1.0 100 0.4 mA mA µA GHz MHz MHz MHz dBm dBm dBm VP-P V V µA µA µA µA V V V V ns ns ns ns ns ns TEST CONDITIONS MIN TYP MAX UNITS IF Input Sensitivity Oscillator Sensitivity High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Oscillator Input Current Oscillator Input Current High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Load Enable Set Up Time Load Enable Pulse Width PfIN IF VOSC VIH VIL IIH IIL IIH IIL VOH VOH VOL VOL tCS tCH tCWH tCWL tES tEW VCC = 2.7V to 5.5V OSCIN (Note) (Note) VIH = VCC = 5.5V (Note) VIL = 0V, VCC = 5.5V (Note) VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V IOH = -500µA IOH = -1mA IOL = 500µA IOL = 1mA See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing NOTE: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN. 5 HFA3524 Charge Pump Specifications PARAMETER Charge Pump Output Current VCC = 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified HFA3524 SYMBOL IDO-SOURCE IDO-SINK IDO-SOURCE IDO-SINK Charge Pump High Z State Current CP Sink vs Source Mismatch (Note 5) CP Current vs Voltage (Note 6) CP Current vs Temperature (Note 7) NOTES: 4. See Programmable Modes for ICPO description. 5. IDO vs VDO = Charge Pump Output Current magnitude variation vs Voltage = [1/2 •{| I1 | - | I3 |}]/[1/2 • {| I1 | + | I3 |}] • 100% and [1/2 • | I4 | - | I6 |]/[1/2 • {| I4 | + | I6 |}] • 100%. 6. IDO-SINK vs IDO-SOURCE = Charge Pump Output Current Sink vs Source Mismatch = [| I2 | - | I5 |]/[1/2 • {| I2 | + | I5 |}] • 100%. 7. IDO vs TA = Charge Pump Output Current magnitude variation vs Temperature = [| I2 at temp | - | I2 at 25oC |]/ | I2 at 25oC | • 100% and [| I5 at temp | - | I5 at 25oC |]/ | I5 at 25oC | • 100%. IDO-HIGH Z IDO-SINK vs IDOSOURCE TEST CONDITIONS VDO = VP/2, ICPO = HIGH (Note 4) VDO = VP/2, ICPO = HIGH (Note 4) VDO = VP/2, ICPO = LOW (Note 4) VDO = VP/2, ICPO = LOW (Note 4) 0.5V ≤ VDO ≤ VP - 0.5, -40oC < T < 85oC VDO = VP/2, TA = 25oC 0.5V ≤ VDO ≤ VP - 0.5, T < 25oC VDO = VP/2, -40oC < T < 85oC MIN -2.5 - TYP -5.0 5.0 -1.25 1.25 3 10 10 MAX 2.5 10 15 - UNITS mA mA mA mA nA % % % IDO vs VDO IDO vs T CURRENT (mA) I3 I2 I1 VOLTAGE OFFSET ∆V I4 I5 I6 I1 = CP sink current at VDO = VP - ∆V I2 = CP sink current at VDO = VP/2 I3 = CP sink current at VDO = ∆V VP/2 0 ∆V I4 = CP source current at VDO = VP - ∆V DO VOLTAGE I5 = CP source current at VDO = VP/2 I6 = CP source current at VDO = ∆V FIGURE 1. CHARGE PUMP CURRENT SPECIFICATION DEFINITIONS ∆V VP-∆V VP CLOCK PC PARALLEL PORT DATA LE FC FOLD 12K IN HP5385A FREQUENCY COUNTER fIN 0Ω 100pF 13dB ATTN VCC 0.01µF VP OSCIN 51 RF 50Ω SMHU 835.8011.52 SIGNAL GENERATOR 10MHz EXT REF OUT 39K 2.2µF 100pF 100pF 2.2µF 2.7V 5.0V FIGURE 2. RF SENSITIVITY TEST BLOCK DIAGRAM 6 HFA3524 Typical HFA3524 Performance Curves 15 14 IDO HIGH Z STATE (pA) 13 ICC (mA) 12 11 10 9 8 7 2.5 T = 25oC T = 40oC T = 85oC 1500 1250 1000 750 500 250 0 -250 -500 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 0 1 2 3 DO VOLTAGE (V) 4 5 6 T = 25oC T = 70oC T = 90oC FIGURE 3. ICC vs VCC FIGURE 4. IDO HIGH Z STATE vs DO VOLTAGE 6 4 DO CURRENT (mA) VP = 2.7V 2 0 -2 -4 -6 VP = 2.7V VP = 5.5V VP = 5.5V DO CURRENT (mA) 2.0 1.5 VP = 5.5V 1.0 VP = 2.7V 0.5 0 -0.5 -1.0 -1.5 -2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DO VOLTAGE (V) DO VOLTAGE (V) VP = 2.7V VP = 5.5V FIGURE 5. CHARGE PUMP CURRENT vs DO VOLTAGE ICP = HIGH FIGURE 6. CHARGE PUMP CURRENT vs DO VOLTAGE ICP = LOW 25 SINK 20 VARIATION (%) SOURCE MISMATCH (%) 20 15 10 5 0 -5 -10 -15 -20 VP = 3.0V VP = 5.0V 15 VP = 3.0V 10 VP = 5.0V 5 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE OFFSET (V) DO VOLTAGE (V) NOTE: See charge pump current specification definitions. FIGURE 7. CHARGE PUMP CURRENT VARIATION FIGURE 8. SINK vs SOURCE MISMATCH vs DO VOLTAGE 7 HFA3524 Typical HFA3524 Performance Curves VCC = 2.7V TO 5.5V, fIN = 0.5GHz TO 3GHz (Continued) VCC = 2.7V TO 5.5V, fIN = 10MHz TO 1000MHz 4 3 1 2 4 3 1 2 Marker 1 = 1GHz, Real = 101, Imaginary = -144 Marker 2 = 2GHz, Real = 37, Imaginary = -54 Marker 3 = 3GHz, Real = 22, Imaginary = -2 Marker 4 = 500MHz, Real = 209, Imaginary = -232 FIGURE 9. RF INPUT IMPEDANCE -10 -15 SENSITIVITY (dBm) Marker 1 = 100MHz, Real = 589, Imaginary = -209 Marker 2 = 200MHz, Real = 440, Imaginary = -286 Marker 3 = 300MHz, Real = 326, Imaginary = -287 Marker 4 = 500MHz, Real = 202, Imaginary = -234 FIGURE 10. IF INPUT IMPEDANCE -10 -15 SENSITIVITY (dBm) -20 -25 -30 -35 -40 -45 VCC = 2.7V -50 0 100 200 300 400 500 600 FREQUENCY (MHz) VCC = 5.5V -20 -25 -30 -35 VCC = 2.7V -40 -45 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 FREQUENCY (MHz) VCC = 5.5V FIGURE 11. RF SENSITIVITY vs FREQUENCY 0 -10 SENSITIVITY (dBm) VCC = 5.5V -20 -30 -40 -50 -60 0 10 20 30 VCC = 2.7V FIGURE 12. IF INPUT SENSITIVITY vs FREQUENCY 0.200 0.063 0.020 0.006 0.002 SENSITIVITY (VPP) 40 50 FREQUENCY (MHz) FIGURE 13. OSCILLATOR INPUT SENSITIVITY vs FREQUENCY 8 HFA3524 Functional Description The simplified block diagram in Figure 14 shows the 22-bit data register, two 15-bit R Counters and the 15-bit and 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA input, MSB first. The last two bits are the Control Bus. The DATA is transferred into the counters as follows: PHASE COMP CHARGE PUMP IF LD 15-BIT IF R COUNTER OSCIN OSC 15-BIT RF R COUNTER RF LD f OUT LOCK DETECT FASTLOCK MUX FO/LD DO IF CONTROL BITS C1 0 0 1 1 C2 0 1 0 1 DATA LOCATION IR R Counter RF R Counter IF N Counter RF N Counter fIN IF IF PRESCALER 15-BIT IF N COUNTER CHARGE PUMP fIN RF RF PRESCALER 18-BIT RF N COUNTER PHASE COMP DO RF CLOCK DATA LE 22-BIT DATA REGISTER FIGURE 14. SIMPLIFIED BLOCK DIAGRAM Programmable Reference Dividers (IF and RF R Counters) If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. LSB ↓ C1 C2 R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 R 9 R 10 R 11 R 12 R 13 R 14 R 15 R 16 R 17 R 18 R 19 MSB ↓ R 20 (Control bits) Divide ratio of the reference divider, R Program Modes 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) DIVIDE RATIO 3 4 • 32767 R 15 0 0 • 1 R 14 0 0 • 1 R 13 0 0 • 1 R 12 0 0 • 1 R 11 0 0 • 1 R 10 0 0 • 1 R 9 0 0 • 1 R 8 0 0 • 1 R 7 0 0 • 1 R 6 0 0 • 1 R 5 0 0 • 1 R 4 0 0 • 1 R 3 0 1 • 1 R 2 1 0 • 1 R 1 1 0 • 1 NOTES: 8. Divide ratios less than 3 are prohibited. 9. Divide ratio: 3 to 32767. 10. R1 to R15: These bits select the divide ratio of the programmable reference divider. 11. Data is shifted in MSB first. 9 HFA3524 Programmable Divide (N Counter) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care bits. LSB ↓ C1 C2 N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 N 10 N 11 N 12 N 13 N 14 N 15 N 16 N 17 N 18 N 19 Program MSB ↓ N 20 (Control bits) Divide ratio of the programmable divider, N 7-Bit Swallow Counter Divide Ratio (A Counter) RF DIVIDE RATIO A 0 1 • 127 NOTES: 12. Divide ratio 0 to 127. 13. B ≥ A. IF DIVIDE RATIO A 0 1 • 15 N 7 X X • X N 6 X X • X N 5 X X • X N 4 0 0 • 1 N 3 0 0 • 1 N 2 0 0 • 1 N 1 0 1 • 1 N 7 0 0 • 1 N 6 0 0 • 1 N 5 0 0 • 1 N 4 0 0 • 1 N 3 0 0 • 1 N 2 0 0 • 1 N 1 0 1 • 1 Pulse Swallow Function fVCO = [(P x B) + A] x fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) P: Preset modulus of dual modulus prescaler (for IF: P = 8 or 16; for RF: P = 32 or 64) Programmable Modes Several modes of operation can be programmed with bits R16-R19 including the phase detector polarity, charge pump High Z State and the output of the FO/LD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes are shown in Table 1. Truth table for the programmable modes and FO/LD output are shown in Table 2 and Table 3. TABLE 1. PROGRAMMABLE MODES C1 C2 0 0 0 1 R16 IF Phase Detector Polarity R17 R18 R19 IF LD RF LD R20 IF FO RF FO X = Don’t care condition. 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER DIVIDE N RATIO B 18 3 4 • 2047 NOTES: 14. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited). 15. B ≥ A. 0 0 • 1 N 17 0 0 • 1 N 16 0 0 • 1 N 15 0 0 • 1 N 14 0 0 • 1 N 13 0 0 • 1 N 12 0 0 • 1 N 11 0 0 • 1 N 10 0 1 • 1 N 9 1 0 • 1 N 8 1 0 • 1 IF ICPO IF DO High Z RF Phase RF ICPO RF DO Detector Polarity High Z C1 1 1 C2 0 1 N19 IF Prescaler RF Prescaler N20 Powerdown IF Powerdown RF 10 HFA3524 TABLE 2. MODE SELECT TRUTH TABLE ΦD POLARITY 0 1 NOTES: 16. The ICPO LOW current state = 1/4 x ICPO HIGH current. 17. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF and RF powerdown bits are activated. The OSCIN pin reverts to a high impedance state when this condition exists. The control register remains active and capable of loading and latching in data during all of the powerdown modes. TABLE 3. THE FO/LD (PIN 10) OUTPUT TRUTH TABLE RF R [19] (RF LD) 0 0 1 1 X X X X 0 0 1 1 1 X = Don’t care condition NOTES: 18. When the FO /LD output is disabled, it is actively pulled to a low logic state. 19. Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked. 20. The Fastlock mode utilizes the FO /LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock). 21. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated, the R counter is also forced to Reset, allowing smooth acquisition upon powering up. VCO OUTPUT FREQUENCY DO HIGH Z STATE Normal Operation High Z State (NOTE 16) ICPO LOW HIGH IF PRESCALER 8/9 16/17 RF PRESCALER 32/33 64/65 (NOTE 17) POWERDOWN Powered Up Powered Down Negative Positive IF R [19] (IF LD) 0 1 0 1 0 0 1 1 0 1 0 1 1 RF R [20] (RF FO) 0 0 0 0 0 1 0 1 1 1 1 1 1 IF R [20] (IF FO) 0 0 0 0 1 0 1 0 1 1 1 1 1 FO OUTPUT STATE Disabled (Note 18) IF Lock Detect (Note 19) RF Lock Detect (Note 19) RF/IF Lock Detect (Note 19) IF Reference Divider Output RF Reference Divider Output IF Programmable Divider Output RF Programmable Divider Output Fastlock (Note 20) For Internal Use Only For Internal Use Only For Internal Use Only Counter Reset (Note 21) Phase Detector Polarity Depending upon VCO characteristics, R16 bit should be set accordingly, (see Figure 15). • When VCO characteristics are positive like (1), R16 should be set HIGH. • When VCO characteristics are negative like (2), R16 should be set LOW. (1) (2) VCO INPUT VOLTAGE FIGURE 15. VCO CHARACTERISTICS 11 HFA3524 DATA N20: MSB (R20: MSB) N19 (R19) N10 (R8) N9 (R7) (R6) N1 (R1) CONTROL BIT: LSB CONTROL BIT: LSB CLOCK tCWL LE tCS OR tCH tCWH tES tEW LE NOTES: 22. Parenthesis data indicates programmable reference divider data. 23. Data shifted into register on clock rising edge. 24. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2V at VCC = 2.7V and 2.6V at VCC = 5.5V. FIGURE 16. SERIAL DATA INPUT TIMING fR fP LD DO H Z I L I I fR > fP fR = fP fR < fP fR < fP fR < fP NOTES: 25. Phase difference detection range: -2π to +2π 26. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked. 27. R16 = HIGH. FIGURE 17. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 12 HFA3524 Typical Application Example VP VCO (NOTE 28) C3 100pF R2 C4 RIN (NOTE 29) 10pF IF OUT 0.01µF VCC 100pF 0.01µF VCC 20 VP 19 DO IF 18 GND 17 16 fIN IF 100pF f IN IF 15 14 FROM CONTROLLER GND LE 13 DATA 12 CLOCK 11 HFA3524 1 VCC VCC 0.01µF 0.01µF 2 VP VP 3 4 DO RF GND 5 6 7 8 9 10 FO/LD FO/LD CRYSTAL OSCILLATOR INPUT fIN RF f IN RF GND 100pF RIN (NOTE 29) OSCIN GND 100pF 100pF 100pF 51Ω (NOTE 30) 10pF VCO (NOTE 28) R1 C1 C2 RF OUT NOTES: 28. VCO is assumed AC coupled. 29. RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω. fIN IF impedances are higher. 30. 50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSCIN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias (see Figure 16). 31. Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. 32. This is a static sensitive device. It should be handled only at static free work stations. FIGURE 18. VCC 100kΩ 100K OSCIN LD 33K 0.01µF 10K MMBT200 LOCK DETECT FIGURE 19. Typical Locked Detect Circuit A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown in Figure 20. 13 FIGURE 20. HFA3524 CHARGE PUMP PHASE DETECTOR φR VP LOOP FILTER DO Z(s) VCO fOUT 1/R CRYSTAL REFERENCE REFERENCE DIVIDER fR fP Φ φP FREQUENCY SYNTHESIZER REFERENCE FREQUENCY fREF fIN 1/N MAIN DIVIDER FIGURE 21. BASIC CHARGE PUMP PHASE LOCKED LOOP Application Information A block diagram of the basic phase locked loop is shown in Figure 21. The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, ω, the filter time constants T1 and T2, and the design constants Kφ, KVCO, and N. – K φ • K VCO ( 1 + j ω • T2 ) T1 G ( s ) • H ( s ) s = j • w = ------------------------------------------------------------------ • -----2 T2 ω C1 • N ( 1 + j ω • T1 ) (EQ. 4) Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 22. The open loop gain is the product of the phase comparator gain (Kφ), the VCO gain (KVCO/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 23, while the complex impedance of the filter is given in Equation 2. ΘR ∑ + From Equation 3 we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation 5. φ ( ω ) = tan –1 ( ω • T2 ) – tan –1 ( ω • T1 ) + 180 o (EQ. 5) ΘE ΘI - Kφ Z(s) KVCO s ΘO 1/N FIGURE 22. PLL LINEAR MODEL A plot of the magnitude and phase of G(s)H(s) for a stable loop, is shown in Figure 24 with a solid trace. The parameter φP shows the amount of phase margin that exists at the point the gain drops below zero (the cutoff frequency wp of the loop). In a critically damped system, the amount of phase margin would be approximately 45 degrees. If we were now to redefine the cut off frequency, wp’, as double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by approximately 6dB. In the proposed Fastlock scheme, the higher spur levels and wider loop filter conditions would exist only during the initial lock-on phase - just long enough to reap the benefits of locking faster. The objective would be to open up the loop bandwidth but not introduce any additional complications or compromises related to our original design criteria. We would ideally like to momentarily shift the curve of Figure 24 over to a different cutoff frequency, illustrated by the dotted line, without affecting the relative open loop gain and phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in the gain and phase Equations 4 and 5 will have to compensate by the corresponding “1/w” or 1/w2” factor. Examination of Equations 3 and 5 indicates the damping resistor variable R2 could be chosen to compensate the “w” terms for the phase margin. This implies that another resistor DO R2 C1 C2 VCO FIGURE 23. PASSIVE LOOP FILTER Open loop gain = H(s) G(s) = Θ I ⁄ Θ E = K φ Z(s) K VCO ⁄ Ns s ( C2 • R2 ) + 1 Z ( s ) = ---------------------------------------------------------------------------------2 s ( C1 • C2 • R2 ) + sC1 + sC2 (EQ. 1) (EQ. 2) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as: C1 • C2 T1 = R2 • --------------------C1 + C2 (EQ. 3A) and T2 = R2 • C2 (EQ. 3B) 14 HFA3524 of equal value to R2 will need to be switched in parallel with R2 during the initial lock period. We must also insure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp’ = 2wp. KVCO, Kφ, N, or the net product of these terms can be changed by a factor of 4, to counteract the w2 term present in the denominator of Equation 3. The Kφ term was chosen to complete the transformation because it can readily be switched between 1X and 4X values. This is accomplished by increasing the charge pump output current from 1mA in the standard mode to 4mA in Fastlock. normal current per unit phase error while an open drain NMOS on chip device switches in a second R2 resistor element to ground. The user calculates the loop filter component values for the normal steady state considerations. The device configuration ensures that as long as a second identical damping resistor is wired in appropriately, the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise operation by sending an instruction with the RF IcpO bit set low. This transition does not affect the charge on the loop filter capacitors and is enacted synchronous with the charge pump output. This creates a nearly seamless change between Fastlock and standard mode. Fastlock Circuit Implementation A diagram of the Fastlock scheme as implemented in Intersil Corporations HFA3524 PLL is shown in Figure 25. When a new frequency is loaded, and the RF IcpO bit is set high, the charge pump circuit receives an input to deliver 4 times the GAIN |