HFA3783

HFA3783 TM Data Sheet March 2000 File Number 4633.2 I/Q Modulator/Demodulator and Synthesizer The HFA3783 is a highly integrated and fully differential SiGe baseband converter for half duplex wireless applications. It features all the necessary blocks for quadrature modulation and demodulation of “I” and “Q” baseband signals. It has an integrated AGC receive IF amplifier with frequency response to 600MHz. The AGC has 70dB of voltage gain and better than 70dB of gain control range. The transmit output also features gain control with 70dB of range. The receive and transmit IF paths can share a common differential matching network to reduce the filter component count required for single IF half duplex transceivers. A pair of 2nd order antialiasing filters with an integrated DC offset cancellation architecture is included in the receive chain for baseband operation down to DC. In addition, an IF level detector is included in the AGC chain for threshold comparison. Up and down conversion are performed by doubly balanced mixers for “I” and “Q” IF processing. These converters are driven by a broadband quadrature LO generator with frequency of operation phase locked by an internal 3 wire interface synthesizer and PLL. The device operates at low LO levels from an external VCO with a PLL reference signal up to 50MHz. The HFA3783 is housed in a thin 48 lead LQFP package well suited for PCMCIA board applications. Features • Integrates All IF Transmit and Receive Functions • Broad Quadrature Frequency Range . . . . . .70 to 600MHz • 600MHz AGC IF Strip with Level Detector . . . . . . . . .69dB • DC Coupled Baseband Interfaces • Integrates a Receiver DC Offset Calibration Loop • Integrated 3 Wire Interface PLL For LO Applications • Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm • Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . Ref/R M(7) X X X 0 1 OUTPUT AT PIN LD Lock Detect Operation Short to GND Serial Register Read Back Ref. Divided by R Waveform LO Divided by [P*B+A] Waveform OPERATION/TEST M(3) 0 1 0 1 OUTPUT SINK/SOURCE 0.25mA 0.50mA 0.75mA 1.00mA 11 HFA3783 DC Offset Calibration Counter BIT C(0-6) DESCRIPTION Least Significant bit C(0) to Most significant bit C(6) of the offset calibration counter/divider. The calibration clock frequency and calibration time is defined by the Reference signal frequency divided down by this counter as follows: 2∗ C CAL TIME = 22 ∗ ----------------------------------REFIN (MHz) Set output bias level for AC coupling applications and TX/RX switching improvement in performance. C(11) CLK WIDTH HIGH CLK/LE SET UP CLK MSB CLK WIDTH LOW LSB DATA BIT 20 BIT 2 BIT 1 DAT/CLK SET UP DAT/CLK HOLD LE LE P. WIDTH FIGURE 1. PLL SYNTHESIZER SERIAL INTERFACE TIMING DIAGRAM 12 HFA3783 S Parameter Tables RX DIFFERENTIAL INPUT, LINEAR MODE FREQ (MHz) 70 140 200 280 380 500 600 MAG 0.886 0.886 0.886 0.885 0.885 0.883 0.883 RX DIFFERENTIAL INPUT, TX MODE FREQ (MHz) 70 140 200 280 380 500 600 MAG 0.877 0.873 0.870 0.866 0.862 0.857 0.853 ANGLE -4.4 -7.4 -10.5 -14.5 -19.6 -25.7 -30.5 REF IN SINGLE END RX DIFFERENTIAL INPUT, SATURATED FREQ (MHz) 70 140 200 280 380 500 600 MAG 0.883 0.881 0.878 0.875 0.869 0.859 0.850 TX DIFFERENTIAL OUTPUT FREQ (MHz) 70 140 200 280 380 500 600 MAG 1 1 0.999 0.999 0.999 0.999 0.997 ANGLE -1.1 -2.0 -2.8 -3.9 -5.4 -7.1 -8.3 ANGLE -2.5 -5.7 -8.4 -11.9 -16.2 -21.3 -25.4 FREQ (MHz) 10 30 50 RESISTOR /CAPACITANCE PARALLEL 5.8K 5.7K 5.7K RX SINGLE END IN LINEAR MODE FREQ (MHz) 70 140 200 280 380 500 600 MAG 0.873 0.872 0.870 0.869 0.870 0.872 0.872 ANGLE -4.0 -7.1 -10.1 -14.2 -19.3 -25.6 -30.8 0.840p 0.850p 0.860p FREQ (MHz) 140 400 560 760 1000 1200 ANGLE -2.6 -4.7 -6.6 -9.4 -12.8 -16.9 -20.1 FREQ (MHz) 70 140 200 280 380 500 600 TX DIFF OUT AT RX-MODE MAG 1 1 1 1 1 0.999 0.999 LO INPUT SINGLE END MAG 0.923 0.920 0.917 0.911 0.900 0.890 ANGLE -5.1 -13.4 -19.0 -25.9 -34.8 -42.3 ANGLE -1.0 -1.9 -2.8 -3.9 -5.2 -6.8 -8.0 13 HFA3783 Overall Device Description The HFA3783 is a highly integrated baseband converter for half duplex wireless data applications. It features all the necessary blocks for baseband modulation and demodulation of “I” and “Q” quadrature multiplexing signals including an on chip three wire interface PLL stage used with an external VCO for Local Oscillator applications. Device RF properties have been optimized through the thoughtful consideration of layout, device pinout, and a completely differential design. These RF properties include immunity from common mode signals such as noise and crosstalk, optimized dynamic range for low power requirements and reduced relevant parasitics and settling times. The single power supply requirements from 2.7VDC to 3.3VDC makes the HFA3783 a good choice for portable transceiver designs. Transmit Chain The HFA3783 modulator section has a frequency response of 70 to 600MHz. It consists of differential “I” and “Q” baseband inputs requiring pre-shaped analog data levels up to 500mVpp. A common mode voltage of around 1.3V is required for proper operation of the four differential input pins. There are no internal pre-shaping filters in the modulator section. Following the differential input stages, a DC coupled up conversion pair of quadrature doubly balanced mixers are used for “I” and “Q” baseband IF processing. These differential mixers are driven by the same internal LO quadrature generator used in the receive section. Their phase and gain characteristics, including I/Q matching, are well suitable for accurate data transmission. The final stage is an AGC amplifier with 70dB of dynamic range. Please refer to Figure 35. Receive Chain The HFA3783 has two cascaded very low distortion integrated AGC IF amplifiers with frequency response from 70 to 600MHz. These differential amplifiers exhibit better than 70dB of both voltage gain and AGC range. Noise figure, output compression and intercept point variations with the AGC range have been tailored to achieve cascaded performances as presented in the AC Electrical Specifications. To increase the receiver’s overall AGC dynamic range and conserve compression specifications, a Peak Detector has been added in parallel with the AGC’s input. The Peak Detector is used to control an external step attenuator or the RF gain of the front end LNA stage. Following the AGC stages, an AC coupled down conversion pair of quadrature doubly balanced mixers are used for “I” and “Q” baseband IF processing. These differential converters are driven by an internal differential quadrature generator with broadband response and excellent quadrature properties. For broadband operation, the Local Oscillator frequency input is twice the desired frequency of demodulation. Duty cycle and signal purity requirements for the 2XLO input using this type of quadrature architecture are less restrictive for the HFA3783. Ground reference or differential input signals from -15dBm to 0dBm and frequencies up to 1200MHz (2XLO) can be used. The output of the “I” and “Q” mixers are DC coupled to a pair of multistage differential 2nd pole antialiasing baseband filters with DC offset correction. The DC offset correction is enabled with an external control pin allowing for correction to occur during transmit, receive or power down modes. The baseband filter’s cut off frequency of 7.7MHz is optimized for 11M chips/s spread spectrum applications. The baseband outputs are differential, with common mode DC voltage outputs tracking an internal band gap voltage reference. The Band Gap reference is also available to the user by an external pin. The “I” and “Q” baseband voltages can swing up to 1Vpp differential, following the AC Electrical Specifications across the AGC range. Figure 16 illustrates the cascaded gain characteristics versus AGC voltage control for the HFA3783 receive section. Detailed Description Receive AGC/ Peak Detector The receive AGC amplifier section consists of 4 stages and each stage is built out of four parallel, distributed gain/degeneration differential pairs. In half duplex packet transmission linear systems, the receive AGC control’s thermal and supply voltage variations over the packet duration are more important than gain control linearity. Therefore, the chosen architecture addresses very constricted temperature, voltage and process variations. The control is based on a band gap voltage reference “gm” distribution scheme. In addition, the design provides fast AGC settling times as well as fast turn on/off characteristics for packetized information. The four stage AGC amplifier has a typical maximum voltage gain of 44dB and exhibits better than 70dB of dynamic range, providing an attenuation in excess of 26dB at minimum gain. The design can be used differential or single ended, exhibiting the same gain characteristics: however, consideration is necessary due to common mode spurious signals. One of the main features of this front end is the high impedance and small variation of S parameters when the HFA3783 is switched between transmit and receive modes. This feature permits the use of a combination match network and the use of a single SAW filter for both halves of the duplex operation. S parameters for the differential and single ended applications are available in the S Parameter Tables of this document. The matching network arrangements will be discussed later in IF Interface section. A Peak Detector is placed in parallel with the input of the first stage of the AGC amplifier. It consists of a high frequency differential full wave rectifier and a voltage to current converter. The Peak Detector has limited range and is used to trip a comparator in an external baseband processor when the voltage swing at the input of the AGC amplifier is about 150mVpp. Once the external comparator is tripped, its logic output level steps the LNA’s gain down keeping the RF 14 HFA3783 and IF mixers out of compression. An external resistor and capacitor set both the desired threshold voltage and time constant. Figures 29 and 30 illustrate the typical current output of the Peak Detector for input voltage levels between 100 and 200mVpp. The output of the calibration counter is again divided by 2 and the period used to generate the time slots of a state sequence. The calibration cycle is initialized by a rising edge on the HFA3783 CAL_EN pin. The state sequence slots 1 to 7 are used to settle all circuits in case the device is in the power down mode, slots 8 to 10 are used to calibrate the offset comparators (auto balancing) and slots 13 to 21 perform the search with an initial value of approximately + or - 400mV differential DC level. The comparator reads the direction and level of the offset and sets the next level and polarity at + or -400/2 mV. The process continues until slot 21 in a divide by 2 polarity and minimum offset search. The contents of the SAR are kept in slot 22 which holds the IDAC in storage mode until a new positive edge is provided to the CAL_EN pin. In receive mode, the AGC amplifiers are turned off during the calibration cycle. A typical calibration time from 10 to 25µS is suggested for optimum accuracy. The baseband outputs of the LPF buffer amplifier drive differential loads of 5KΩ with a common mode voltage of typically 1.17V. An extra feature of the LPF allows for AC coupling of the baseband differential outputs. To avoid discharging of the AC coupling capacitors between transmit and receive states a common mode voltage can be applied to all outputs. An onboard programmable bit control establishes the application with 4 internal resistors and switches. Quadrature Demodulator The output of the AGC amplifier is AC coupled to two doubly balanced quadrature differential mixers, for “I” and “Q” demodulation. With full balanced differential architecture, these mixers are driven by an accurate internal Local Oscillator (LO) chain as described later. The voltage gain for both mixers is well matched with a typical value of 8V/V. Low Pass Filter and DC Offset Correction To cover baseband signals from DC to 7.7MHz, the outputs of the baseband down converter mixers are DC coupled to the Low Pass Filter stages. For true DC response, the combination of all DC offsets (mixer, LPF and buffers) needs to be calibrated for accurate baseband processing. This calibration can be performed at any time during the receive, transmit or power down modes. Figure 2 depicts the baseband low pass receive filter implementation and Figure 3 shows the calibration internal timing diagram of the HFA3783. Referring to channel “I” for example, calibration begins with the auto balanced comparator measuring the differential offset between the RXI+ and RXI- outputs. The comparator’s output is fed to a decision circuit which changes the condition of a Successive Approximation Register (SAR) state control. The SAR controls 8 bits of a current output Digital to Analog Converter (IDAC) which is divided by weight into a LPF section (2 pole) and a buffer amplifier. The currents are searched and set to bring the offset to a minimum. The LPF has a fixed gain of 2.5V/V and the buffer adds a 1.25V/V final gain to the receive chain. Referring to Figure 2, clocking to the SAR is provided by a programmable division of the REF_IN signal. (Used for the PLL as the stable reference.) The frequency of the reference signal is divided down by the register setting of the offset calibration counter. (Details for setting this counter can be found in the Programming the PLL Synthesizer and DC Offset Clock section.) LO Quadrature Generator The In Phase and Quadrature Local oscillator signals are generated by a divide by two circuit that drives both the up and down conversion mixers. With a fully balanced approach, the phase relationship between the two quadrature signals is within 90o ±2o for a wide 70 to 600MHz frequency range. The input signal frequency at the LO_IN pin needs to be twice the desired Local Oscillator frequency. The high impedance differential LO_IN+ and LO_IN- inputs, which are driven by an external VCO, can be used single ended by capacitively bypassing one input to ground. The user needs to terminate the VCO transmission line into the desired impedance and AC couple the active LO_IN input. Divide by two LO generation often requires rigid control of signal purity or duty cycles. The HFA3783 has an internal duty cycle compensation circuit which eases the requirements of rigidly controlled duty cycles. Second harmonic contents up to 10% are acceptable. 15 HFA3783 LPF BUFFER CM VOLTAGE Bit C RXI+ PIN 38 RXIPIN 37 8 IDAC SAR CONTROL COMP AUTO BAL. 8 IDAC COMP CAL CLK LPF BUFFER CM VOLTAGE BITS C CAL_EN PIN 42 CAL COUNTER REF_IN PIN 14 RXQ+ PIN 36 BIT C RXQPIN 35 FIGURE 2. DC OFFSET CALIBRATION BLOCK DIAGRAM CAL_EN CALIBRATION STARTS AT NEXT RISE TIME OF (REF/COUNTER) SETTING FROM THE SERIAL INTERFACE (CAL CLK) REF/C REF/2C SLOT 10 SLOT 13 SLOT 21 2 3 5 4 6 7 8 AGC AMP ON-BASEBAND NATURAL OFFSET IF CAL_EN IS LOW CALIBRATE COMPARATORS AGC AMP ON CALIBRATED OFFSET AT BASEBAND AGC AMP TURNED OFF IN RX MODE FIGURE 3. DC OFFSET CALIBRATION TIMING DIAGRAM 16 STORE CAL ALLOCATED SETTLING TIME 1 SLOT 22 SLOT 1 SLOT 2 SLOT 8 HFA3783 N COUNTER RESET A R COUNTER REF_IN R PIN 14 TO DC OFFSET CAL V ISOURCE ISINK RESET B DUAL MODULUS CONTROL P/P+1 PRESCALER LO_IN+ PIN 27 OR 26 CP_D0 PIN 22 VCONTROL VCO FIGURE 4. PLL SIMPLIFIED BLOCK DIAGRAM VCO [P*B+A] REF R 1/2VCC FIGURE 5. CHARGE PUMP OUTPUT FOR TWO SLIGHTLY DIFFERENT FREQUENCY SIGNALS PLL The HFA3783 includes a classical architecture Phase Lock Loop circuit with a three wire serial control interface to be used with an external VCO. Figure 4 depicts a simplified block diagram of the PLL. It consists of a programmable “R” counter used to divide down the frequency of a very stable reference signal up to 50MHz to a phase comparator. A couple of counters (“A” and “B”) with a front end prescaler (“P or P+1”), with dual modulus control, divides down the frequency of an external VCO signal to the same phase comparator. The comparator controls a charge pump circuit and an external loop filter closes the loop for VCO control. The VCO frequency dividing chain works with a dual modulus control as follows: At the beginning of a count cycle, and if the A counter is programmed with a value greater than zero, the prescaler is set to a division ratio of (P+1) where P can take programmable values of 16 or 32. 17 Notice that the prescaler output signal is always fed simultaneously to both A and B counters. Upon filling counter A, the prescaler division ratio becomes P and the B counter continues on its own with A in standby. This process is known as “pulse swallowing”. The expression B-A (counts) is the remainder of counts carried out by the B counter after A is full. Both A and B counters are reset at the end of the counting cycle when B fills up. As a result, the total count or division ratio used for the VCO signal is A*(P+1) + (B-A)*P which simplifies to [P*B+A]. (A and B counters are referred as the “N” counter). The Charge Pump (current source/sink) has 4 programmable current settings. This variation allows the user to change the reference frequency for different objectives without changing the loop filter components. The user can program the charge pump sign based on the direction of increase or decrease of the VCO frequency. The TO LO DIVIDE BY 2 DRIVERS HFA3783 most often used VCO’s in the market have positive KVCO’s where the VCO frequency increases with an increase in control voltage. In this case, the charge pump current shall “source” current (to the main capacitor of the loop filter) when the VCO frequency becomes less than the desired frequency of operation. The phase comparison and charge pump output behavior in a open loop system is illustrated in Figure 5. The comparator’s inputs (the top two waveforms of Figure 5 are from the N and R counters. The output from the “N” counter and the prescaler, labelled as “VCO/[P*B+A]” shows a lower frequency than the output from the “R” counter labeled “REF/R”. REF/R is usually called “reference” frequency. The bottom waveform represents the charge pump sourcing current as it has been programmed. Because it is an open loop system, the charge pump current pulse width will increase and follow the phase comparator’s output. The charge pump signal can be developed across a resistor connected between pin 22 and a power supply of half the VCC voltage. In the case where the VCO/[P*B+A] frequency is higher than the REF/R frequency, the bottom waveform would have negative pulse width variations indicating the Charge Pump sinking current. The closed loop concept can be understood intuitively by observing the bottom waveform and noticing the tendency of the Charge Pump to “charge” a capacitor (loop filter) and increase the VCO voltage control accordingly. As the VCO/[P*B+A] frequency becomes higher than the REF/R frequency, the Charge Pump begins to sink current and the VCO control voltage begins to drop. The process would continue in equilibrium with expected sharp reverting polarity pulses at the REF/R reference frequency. Figure 6 depicts a simple Charge Pump polarity concept and includes the output of the Lock Detect Pin of the HFA3783. This pin has other applications and will be covered in the next section. PLL Synthesizer and DC Offset Clock Programming A three wire CMOS Serial interface (CLK, DATA, LE) programs various counters and operational modes of the HFA3783 PLL. It also programs the DC offset adjust counter and operation of the LPF section. Figure 1 in the Specification section shows the Timing Diagram for this interface. Short clock periods in the order of 20ns can be used to program this interface. The serial data is clocked on the rising edge of the serial clock into a serial 20-bit shift register with the MSB first. See the PLL synthesizer and DC Clock Programming Table for details. The serial register is always active when the LE pin is held low. On the rising edge of the LE pin, the serial register is loaded and latched into the addressed registers for the particular function. The two least significant bits address the intended register for loading the serial data. This interface has been designed for a minimum LE pulse width. There is no need to discontinue the clock during loading of the 4 intended registers. NOTE: Upon a rising edge on LE, the HFA3783 PLL unlocks the loop during a random period varying from 0 to 1/(reference frequency). Fast frequency hopping applications may be affected during this time. ÷N REF CP LD FIGURE 6. SIMPLIFIED CP AND LOCK DETECT OUTPUT WAVEFORMS 18 HFA3783 The four registers are as follows: R Counter: Division factor “R” in binary weight format with R(0) as 20 and so on, for a decimal integer division ratio for the stable reference signal. A/B Counter: A combination of binary weighted integer division factors for the “N” counter as explained by the relationship P*B+A. Operational Mode: These register bits control the Charge Pump operation, Prescaler “P” setting, the power down feature of the PLL and the functions of the LD output pin. Offset Calibration: These register bits control the division ratio, in binary weight, for the SAR clock and a special baseband output state for the Low Pass Filter. NOTE: At power up (VCC application), it is important to load the Operational Mode register before any sequence of the remaining registers. DC Offset Calibration Counter Description Bits C(0) to C(6): Set a binary weighted decimal integer number for the stable reference input frequency division ratio. The ratio is used by the SAR for DC Offset Calibration in the HFA3783 and previously described in the Low Pass Filters section of this document. Bit C(11): Enables a DC hold circuit which allows AC coupling of the baseband signals to a processor A/D’s. A common mode voltage applied to the baseband outputs during transmit mode switching reduces the coupling capacitors charging times. Quadrature Modulator The differential baseband signals for the HFA3783 modulator require a controlled common mode voltage for proper operation of the device. Carrier suppression is consequently a function of the common mode DC match between the differential legs of each of the “I” and “Q” channels. The modulator bandwidth is very wide and need to be limited by external means. The inputs are equivalent to driving the up conversion quadrature mixers directly; therefore provisions for shaping the baseband signals before up conversion have to be made externally. Shaping can be accomplished either by an external filter or by pre-shaping in a baseband processor. Baseband signals up to 500mVpp differential can be used at the “I” and “Q” ports. Centered upon a common mode voltage, the 500mVpp preshaped differential signals were used for the compression characteristics specified in this document. By reducing the magnitude of these signals improved low distortion modulation characteristics can be realized. The quiescent current for the upconversion mixers is established by the common mode input DC signal. By setting the common mode voltage to zero during the receive mode, power dissipation and mixer noise in the transmit path is reduced. The common mode voltage, routed through the baseband processor for temperature and VCC tracking, is normally established by the HFA3783’s on board 1.2V reference. This reference is inactive during the power down mode. The quadrature up converter mixers are also of a doubly balanced design. “I” and “Q” up converter signals are summed and buffered to drive the next stage, the AGC amplifier. As with the demodulators, both modulator mixers are driven from the same quadrature LO generator. These mixers feature a phase balance of ±2o and amplitude balance of 0.5dB from 70 to 600MHz. These qualities are reflected into the SSB characteristics. For differential “I” and “Q”, 100KHz sinusoidal inputs of 375mVpp, 90o apart, the carrier feedthrough is typical -43dBc with typical sideband suppression of 43dBc at 374MHz. A differential open collector linear output AGC amplifier with 70dB of dynamic range follows the mixers. This amplifier is based in a tight controlled voltage and temperature current Operational Modes Description Bit M(0): This bit is normally set at one for the PLL operation. Setting to zero can save up to 6mA of supply current by disabling the PLL, although the serial interface is always active for loading data. This operational mode bit controls the serial interface at power up and it is important to be loaded first, after application of VCC. Bit M(2): Selects the prescaler “P” for either 16 or 32. Bits M(3),M(4): These bits select the desired Charge Pump current from 250µA to 1mA in four steps. Bits M(5), M(6): Programming 00 will set the Charge Pump to “source” current when the VCO frequency is below the desired frequency. It is used for VCO’s where the frequency increases with increase in the voltage control. Programming 01 sets the Charge Pump to sink current when the VCO frequency is below the desired frequency. It is used for VCO’s where the frequency increases with decrease in the voltage control (Negative KVCO). Bits M(8), M(7) and M(13): These bits define the LD output multiple operation. During the lock detect operation, the LD output follows the phase comparator output and can be used with external integration, as a frequency lock monitor function. LD output can be shorted to ground or used as a monitor pin for either the output of the “R” counter divider or the [P*B+A] dual modulus divider. In addition, it can be used as the serial register read back for testing purposes in a FIFO mode (not the latched register/counters themselves) by reading the MSB on the falling edge of LE and the remaining bits on the rising CLK edges. Bits M(14), M(15): These bits set the Charge Pump operation for normal operation, constant sink or source and in a high impedance state. The high impedance state allows for external control. 19 HFA3783 steering mechanism for gain control. The amplifier main function is controlling the power output of the transmit signal and has very linear AGC characteristics as shown in Figure 35. The differential open collector outputs require VCC biasing as with any open collector application and exhibit high isolation. The HFA3783 output impedance is constant whether in the receive or transmit mode. Consequently, a combination matching network with the use of a single SAW filter can be used for both halves of the duplex operation. Single ended operation is discouraged due to; TX and RX return loss variation, loss of power output and lack of cancellation of PLL induced spurious signals. Differential summing match networks are strongly recommended when using single end SAW devices. S parameters for the output port are available in the S Parameter Tables section. The AGC amplifier feature an output compression level of 1VP-P, with a cascaded performance capable of generating a typical CW power of -10dBm into 250Ω when differential inputs of 250mV DC are applied to both “I” and “Q” inputs. maybe optional depending of the differential network used to match an external filter to a 250Ω system. † AVOID GROUND RETURN FILTER MATCH NETWORK FILTER 250Ω FOR VCC BYPASS CLOSE TO PIN 5 GND. 250Ω VCC † PIN 9 PIN 8 PIN 4 PIN 3 HFA3783 IF interface Both modulator and demodulator of the HFA3783 AC Cascaded Specifications in this document were characterized in a 250Ω system. The high impedance of the receive input and the open collector output structure of the transmit channel permit the use of a combination match network capable of interfacing with only one differential filter device in duplex operation. In addition, the HFA3783 input and output impedances have small variations when the device changes its mode of operation from transmit to receive. The system impedance (250Ω) is defined by the filter input/output impedance including its own match networks and this value has been chosen as a compromise between current consumption, voltage swing and therefore compression. A higher system Zo can compromise the voltage swing capabilities due to the low voltage operation of the HFA3783 and a low system Zo affects the power supply current consumed by the application in general, for the same RF power budget. The output match network of the transmit output, includes a differential “L” match network used to bias the differential collectors which are of high impedance. This high impedance is lowered to a value of around 2KΩ by a parallel resistor placed across the collector terminals. This value sets the output impedance of the two collectors and also serves as a compromise value for the loaded “Q” of the network for a desired system bandwidth. The other side of the match network is set to match 250Ω (from a filter match application) and is directly connected to the receive differential terminals; therefore presenting a controlled termination to the high input impedance port of the receive AGC. The use of DC blocking capacitors is needed to avoid a DC path between the HFA3783 receive terminals and is FIGURE 7. SIMPLIFIED IF INPUT/OUTPUT COMBINED MATCH NETWORK As with any differential network, symmetry is paramount. The use of matched length lines and good differential isolation, helps the structure reject common mode induced signals from other parts of the system. Special attention to the collector outputs is necessary to reject VCC induced spurious signals and to reject internally induced PLL spurious tones. Although the network topology is simple theoretically, its implementation is challenged by layout routing and parasitics which have to be taken into consideration. 20 HFA3783 Typical Performance Curves 39 38 +85, 2.7V 37 36 +85, 3.3V 35 34 33 +25, 2.7V 32 31 +25, 3.3V 30 29 28 27 -40, 2.7V 26 25 -40, 3.3V 24 23 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 RX POWER GAIN (dB) 33 32 31 TX ICC (mA) 30 3.3V 29 28 27 26 25 24 -40 20 30 80 90 2.7V RX ICC (mA) TEMPERATURE (C) FIGURE 8. RX ICC vs POWER GAIN OVER TEMPERATURE FIGURE 9. TX ICC WITH TXI/Q = 1.3V OVER TEMPERATURE AND VOLTAGE 1.1990 1.1980 3.3V 160 140 STANDBY ICC (µA) 120 100 VREF (V) +85 1.1970 1.1960 1.1950 1.1940 1.1930 1.1920 -40 2.7V 80 60 40 20 0 2.7 2.8 2.9 3.0 VCC 3.1 +25 -40 3.2 3.3 20 30 TEMPERATURE (C) 80 90 FIGURE 10. STANDBY ICC vs VCC FIGURE 11. 1.2V VREF VOLTAGE OVER VCC AND TEMPERATURE 244 242 240 238 250µA SETTING (µA) 236 234 232 230 228 226 224 222 220 -40 20 30 80 90 0.85 -40 20 30 TEMPERATURE (oC) 80 90 2.7V, SOURCE 2.7V, SINK 3.6V, SINK 1mA SETTING (mA) 0.97 3.6V, SOURCE 0.95 0.93 0.91 0.89 0.87 2.7V SOURCE 3.6V, SOURCE 0.99 3.6V SINK 2.7V SINK TEMPERATURE (oC) FIGURE 12. CHARGE PUMP 250µA SETTING SINK AND SOURCE CURRENT OVER TEMPERATURE AND VOLTAGE FIGURE 13. CHARGE PUMP 1mA SETTING SINK AND SOURCE CURRENT OVER TEMPERATURE AND VOLTAGE 21 HFA3783 Typical Performance Curves 0.3 0.2 2.7V CP CURRENT 0.1 0 -0.1 -0.2 3.3V -0.3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -1.0 3.3V -1.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.3V CP CURRENT 0.5 (Continued) 1.5 3.3V 1.0 2.7V 0 2.7V -0.5 2.7V CP VOLTAGE CP VOLTAGE FIGURE 14. CHARGE PUMP CHARACTERISTICS AT 250µA 65 60 55 50 45 40 35 RX GAIN (dB) 30 25 20 15 10 5 0 -5 -10 -15 -20 0.0 0.2 0.4 -40 +85 +25 FIGURE 15. CHARGE PUMP CHARACTERISTICS AT 1mA 0.6 0.8 1.0 1.2 1.4 VAGC (V) 1.6 1.8 2.0 2.2 2.4 FIGURE 16. RX AGC POWER GAIN vs VAGC OVER TEMPERATURE AT ALL VCC 22 HFA3783 Typical Performance Curves (Continued) AMPLITUDE RELATIVE SCALE DELAY AMP, 1dB/DIV DELAY, 10ns/DIV RBW, 300Hz 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 FREQUENCY (MHz) FIGURE 17. RX BASEBAND LPF PROFILE REF 4.0dBm RES BW = 100kHz VIDEO BW = 1kHz REF 4.0dBm RES BW = 100kHz VIDEO BW = 1kHz 10dB/DIV 10dB/DIV 10kHz FREQUENCY 10kHz FREQUENCY 15MHz 15MHz FIGURE 18. RX BASEBAND SPECTRUM, TONE AT 1.5MHz POWER GAIN OF 56dB. OUTPUT CONVERTED TO SINGLE ENDED 50Ω FIGURE 19. RX BASEBAND SPECTRUM, TONE AT 1.5MHz POWER GAIN OF -16dB. OUTPUT CONVERTED TO SINGLE ENDED 50Ω 23 HFA3783 Typical Performance Curves (Continued) 0.01dB/DIV GAIN MATCH VARIATION (dB) +85, 2.7V +85, 3.3V +25, 2.7V, 3.3V -40, 2.7V -40, 3.3V -20 -10 0 10 20 30 40 50 60 70 RX POWER GAIN FIGURE 20. RX I/Q CHANNEL GAIN MATCH vs POWER OVER TEMPERATURE AND VCC 0.05 DEG/DIV -40, 2.7V PHASE MATCH VARIATION (DEG) -40, 2.7V +25, 2.7V +25, 3.3V +85, 3.3V +85, 2.7V -20 -10 0 10 20 30 40 50 60 70 RX POWER GAIN (dB) FIGURE 21. RX I, Q CHANNEL PHASE MATCH vs POWER GAIN OVER TEMPERATURE AND VCC 24 HFA3783 Typical Performance Curves 80 70 DEGREES (RELATIVE) 60 50 40 30 20 10 0 0.2 VAGC BB (NOMINAL) (Continued) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 CH1 1.00V CH2 1.00V 100ns/DIV VAGC (V) FIGURE 22. RX INSERTION PHASE vs VAGC FIGURE 23. RX BASEBAND AGC RESPONSE TIME, 0dBm INPUT BB (NOMINAL) CH1 BB (NOMINAL) VAGC CH2 (PE2) PE1 = 1 CH1, 1.00V CH2 1.00V 100ns/DIV CH1, 500mV CH2, 2.00V 100ns/DIV FIGURE 24. RX BASEBAND AGC RESPONSE TIME, 0dBm INPUT FIGURE 25. TX TO RX BASEBAND SWITCHING TIME BB (NOMINAL) CH1 BB (NOMINAL) CH1 CH2 PE2 CH2, PE1 PE1 = 1 PE2 = 1 CH1, 500mV CH2, 2.00V 100ns/DIV CH1, 500mV CH2, 2.00V 100ns/DIV FIGURE 26. RX TO TX BASEBAND SWITCHING TIME FIGURE 27. RX BASEBAND AT POWER UP 25 HFA3783 Typical Performance Curves BB (NOMINAL) CH1 OUTPUT CURRENT DISTRIBUTION (µA) (Continued) 300 250 200 150 -3σ 100 50 0 100 +3σ CH2, PE1 PE2 = 0 120 140 160 180 200 CH1, 500mV CH2 2.00V 100ns/DIV INPUT LEVEL AT 374MHz, (mVPP) FIGURE 28. RX BASEBAND AT POWER DOWN FIGURE 29. IF DETECTOR OUTPUT CURRENT, ±3 SIGMA DISTRIBUTION AT ALL TEMPERATURE AND VCC 250 IF INPUT (374MHz) OUTPUT CURRENT (µA) 200 +25 150 +85 100 -40 50mV/DIV 50 IF DET OUTPUT 200mV/DIV 0 100 120 140 160 180 200 INPUT SIGNAL AT 374MHz, (mVPP) 50ns/DIV FIGURE 30. TYPICAL IF DETECTOR OUTPUT CURRENT AT ALL VCC FIGURE 31. IF DETECTOR RESPONSE, RISE TIME IF INPUT (374MHz) 50mV/DIV IF DET OUTPUT 200mV/DIV 50ns/DIV FIGURE 32. IF DETECTOR RESPONSE, FALL TIME 26 HFA3783 Typical Performance Curves (Continued) 0.5mV/DIV CALIBRATED OFFSET VARIATION 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VAGC (V) FIGURE 33. BASEBAND OUTPUT OFFSET VOLTAGE VARIATION vs VAGC, IF = 0V 0 RELATIVE BB OUTPUT (dB) -2 -4 -6 -8 70 170 270 370 470 570 670 770 870 FREQUENCY (MHz) FIGURE 34. CASCADED RX FREQUENCY RESPONSE, BB AT 1MHz 27 HFA3783 Typical Performance Curves -5 -10 -15 -20 -25 SSB TX OUTPUT POWER (dBm) -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TX VAGC (V) -40 +25 +85 (Continued) FIGURE 35. TX POWER OUT vs TX VAGC OVER TEMPERATURE AT ALL VCC CENTER FREQ = 374MHz SPAN = 1MHz RES BW = 3.0kHz VBW = 3.0kHz REF -8.0dBm 10dB/DIV 10dB/DIV REF -8.0dBm START FREQ = 0.005GHz STOP FREQ = 2.55GHz RES BW = 100kHz VBW = 30kHz 375MHz (SSB) FIGURE 36. TX SSB OUTPUT CHARACTERISTICS AT FULL GAIN FIGURE 37. TX SSB OUTPUT CHARACTERISTICS AT FULL GAIN AND WIDE SPECTRUM WITH MATCH NETWORK 28 HFA3783 Typical Performance Curves CENTER FREQ = 374MHz SPAN = 1MHz RES BW = 3kHz VBW = 3kHz PREAMP GAIN = 50dB 10dB/DIV 10dB/DIV (Continued) CNTR FREQ = 374MHz SPAN = 50MHz RES BW = 3kHz VBW = 100kHz REF -15.0dBm REF -68.0dBm FIGURE 38. TX SSB OUTPUT CHARACTERISTICS AT -60dB FROM FULL GAIN FIGURE 39. TX SPREAD SPECTRUM OUTPUT CHARACTERISTICS AT FULL GAIN, BB INPUTS AT 500mVPP REF -85.0dBm 10dB/DIV CENTER FREQ = 374MHz SPAN = 50MHz RES BW = 300kHz VBW = 100kHz PREAMP GAIN = 50dB FIGURE 40. TX SPREAD SPECTRUM OUTPUT CHARACTERISTICS AT -70dB FROM FULL GAIN, BB INPUTS AT 500mVPP 29 HFA3783 Typical Performance Curves (Continued) -40.5 -41.0 -41.5 -42.0 CARRIER SUPPRESSION (dBc) -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 +25, 2.7V AND 3.3V -45.5 -46.0 -46.5 -40, 3.3V -47.0 0.0 0.2 0.4 0.6 0.8 VAGC (V) 1.0 1.2 1.4 1.6 -40, 2.7V +85, 3.3V +85, 2.7V FIGURE 41. TYPICAL TX CARRIER SUPPRESSION vs VAGC OVER TEMPERATURE -40 -41 -42 SIDEBAND SUPPRESSION (dBc) -43 +25, 3.3V -44 -45 -46 -47 +25, 2.7V -40, 2.7V -40, 3.3V +85, 3.3V +85, 2.7V -48 -49 0 0.2 0.4 0.6 0.8 VAGC (V) 1.0 1.2 1.4 1.6 FIGURE 42. TYPICAL TX LOWER SIDE BAND SUPPRESSION vs VAGC OVER TEMPERATURE 30 HFA3783 Typical Performance Curves 0.25 0.20 0.15 AMP ERROR (dB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -150 -100 -50 0 50 100 150 -0.4 -0.6 -0.8 200 AMP ERROR 0.4 0.2 0 -0.2 PHASE ERROR (DEG) PHASE ERROR (Continued) 0.8 INSERTION PHASE, DEG (RELATIVE) 0.6 90 80 70 60 50 40 30 20 10 0 -10 0 0.5 1.0 1.5 VAGC (V) 2.0 2.5 3.0 NOMINAL ANGLE FIGURE 43. TYPICAL TX CARRIER STATIC AMPLITUDE AND PHASE BALANCE AT 250mV DC DIFFERENTIAL BB INPUTS FIGURE 44. TX INSERTION PHASE vs VAGC CH1 IF OUTPUT CH1 IF OUTPUT CH2 VAGC VAGC CH2 CH1, 200mV CH2, 1.00V 200ns/DIV CH1, 200mV CH2, 1.00V 200ns/DIV FIGURE 45. TX AGC RESPONSE TIME, FULL GAIN FIGURE 46. TX AGC RESPONSE TIME, FULL GAIN IF OUTPUT AT FULL GAIN IF OUTPUT AT FULL GAIN CH1 CH1 PE2 PE1 = 1 CH2 PE2 PE1 = 1 CH2 CH1, 200mV CH2 2.00V 50ns/DIV CH1, 200mV CH2 2.00V 50ns/DIV FIGURE 47. RX TO TX IF OUTPUT SWITCHING TIME FIGURE 48. TX TO RX IF OUTPUT SWITCHING TIME 31 HFA3783 Typical Performance Curves (Continued) IF OUTPUT AT FULL GAIN CH1 PE1 CH1 CH2 PE2 = 0 CH2 PE1 PE2 = 0 CH1, 200mV CH2 2.00V 50ns/DIV CH1 200mV CH2 2.00V 50.0ns/DIV FIGURE 49. TX IF OUTPUT AT POWER UP FIGURE 50. TX IF OUTPUT AT POWER DOWN -12 -13 CARRIER POWER (dBm) -14 -30 -40 -50 -60 REF LEVEL -30dBm CTR FREQ = 748kHz SPAN = 5kHz RES BW = 100Hz VBW = 100Hz -15 -16 -17 REFER TO TEST DIAGRAM -18 -19 70 -70 -80 -90 -100 -110 170 270 370 470 570 670 770 870 -120 -130 -75.5dBc/Hz FREQUENCY (MHz) FIGURE 51. TX OUT POWER vs FREQUENCY, BB AT DC FIGURE 52. EVAL BOARD TYPICAL SYNTHESIZER CLOSE IN PHASE NOISE -30 -40 -50 -60 REF LEVEL -30dBm -70 -80 -90 -100 -110 -120 -130 CTR FREQ = 748MHz SPAN = 100kHz RES BW = 1kHz VBW = 100Hz -30 -40 -50 -60 REF LEVEL -30dBm -70 -80 -90 -100 -110 -120 -130 CTR FREQ = 748MHz SPAN = 100kHz RES BW = 1kHz VBW = 100Hz FIGURE 53. EVAL BOARD TYPICAL SYNTHESIZER OUTPUT WITH PLL AT 10kHz BW FIGURE 54. EVAL BOARD TYPICAL SYNTHESIZER OUTPUT WITH PLL AT 1kHz BW 32 HFA3783 Typical Performance Curves -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 CTR FREQ = 748kHz SPAN = 10kHz RES BW = 100Hz VBW = 10Hz REF LEVEL -30dBm (Continued) FIGURE 55. EVAL BOARD SYNTHESIZER TX TO RX SWITCHING SPURIOUS RESPONSE AT 1kHz SWITCHING FREQUENCY, PLL BW = 10kHz 33 HFA3783 Thin Plastic Quad Flatpack Packages (LQFP) D D1 -D- Q48.7x7A (JEDEC MS-026BBC ISSUE B) 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 A2 MIN 0.002 0.054 0.007 0.007 0.350 0.272 0.350 0.272 0.018 48 0.020 BSC MAX 0.062 0.005 0.057 0.010 0.009 0.358 0.280 0.358 0.280 0.029 MILLIMETERS MIN 0.05 1.35 0.17 0.17 8.90 6.90 8.90 6.90 0.45 48 0.50 BSC MAX 1.60 0.15 1.45 0.27 0.23 9.10 7.10 9.10 7.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 1/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 0.08 A-B S 0.003 M C DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING -AE E1 -B- b b1 D D1 E e PIN 1 SEATING A PLANE 0.08 0.003 -C- E1 L N e -H- 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. “N” is the number of terminal positions. 11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1 0.09/0.20 0.004/0.008 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 34